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* llvm-mc: Match a few X86 instructions.Daniel Dunbar2009-07-311-8/+71
| | | | | | | | | | | - This is "experimental" code, I am feeling my way around and working out the best way to do things (and learning tblgen in the process). Comments welcome, but keep in mind this stuff will change radically. - This is enough to match "subb" and friends, but not much else. The next step is to automatically generate the matchers for individual operands. llvm-svn: 77657
* Manage MachineFunctions with an analysis Pass instead of the AnnotableDan Gohman2009-07-3111-104/+119
| | | | | | | mechanism. To support this, make MachineFunctionPass a little more complete. llvm-svn: 77654
* Fix cmake build.Benjamin Kramer2009-07-311-1/+0
| | | | llvm-svn: 77649
* Add getOrInsertNamedMetadata().Devang Patel2009-07-301-3/+14
| | | | llvm-svn: 77646
* When fp is not eliminated, instructions with T2_i12 modes will be changed to ↵Evan Cheng2009-07-302-3/+10
| | | | | | T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. llvm-svn: 77642
* Removed the BigBlock register allocator.Lang Hames2009-07-301-892/+0
| | | | llvm-svn: 77640
* Do not use abbrev while writing NamedMDNode name.Devang Patel2009-07-301-9/+4
| | | | llvm-svn: 77637
* Enumerate NamedMDNode elements first.Devang Patel2009-07-301-4/+0
| | | | llvm-svn: 77636
* Move more code back to 2.5 APIs.Owen Anderson2009-07-3041-221/+180
| | | | llvm-svn: 77635
* Remove redundant match for frame index from imm8 addrmode, it is handled by ↵David Goodwin2009-07-301-24/+14
| | | | | | the imm12 addrmode. llvm-svn: 77632
* Darwin assembler now recognizes "orn", so remove workaround.David Goodwin2009-07-301-5/+3
| | | | llvm-svn: 77627
* Darwin assembler now supports "rrx", so remove workaround.David Goodwin2009-07-301-2/+1
| | | | llvm-svn: 77625
* Twine: Directly support int, long, and long long types.Daniel Dunbar2009-07-301-17/+29
| | | | | | - This should resolve Cygwin gcc ambiguities. llvm-svn: 77624
* Use CallbackVH in AliasSetTracker to avoid getting stuck withDan Gohman2009-07-301-4/+20
| | | | | | dangling Value*s. llvm-svn: 77623
* Cleanup and include code selection for some frame index cases.David Goodwin2009-07-301-20/+49
| | | | llvm-svn: 77622
* Start using DebugInfoFinder.Devang Patel2009-07-301-13/+11
| | | | llvm-svn: 77621
* Do not use getNamedValue() to lookup NamedMDNode. NamedMDNode is not a ↵Devang Patel2009-07-301-1/+1
| | | | | | | | GlobalValue. Thanks Benjamin Kramer! llvm-svn: 77619
* Twine: Use raw_ostream::write_hex, remove unused itohexstr method.Daniel Dunbar2009-07-301-2/+1
| | | | llvm-svn: 77617
* s/DebugInfoEnumerator/DebugInfoFinder/gDevang Patel2009-07-301-31/+31
| | | | llvm-svn: 77615
* Add raw_ostream::write_hexDaniel Dunbar2009-07-301-4/+7
| | | | llvm-svn: 77614
* Add missing D* register clobbers for Thumb-2 call.David Goodwin2009-07-301-0/+1
| | | | llvm-svn: 77611
* Twines: Don't allow implicit conversion from integers, this is too tricky.Daniel Dunbar2009-07-304-13/+13
| | | | llvm-svn: 77605
* walk DbgRegionStartInst and DbgRegionEndInstDevang Patel2009-07-301-2/+20
| | | | llvm-svn: 77604
* Minor whitespace tidiness.Dan Gohman2009-07-301-3/+0
| | | | llvm-svn: 77602
* Rename GRAD to GR32_AD, to follow the naming convention of otherDan Gohman2009-07-302-2/+4
| | | | | | classes. And define its SubRegClassList. llvm-svn: 77601
* add a random codegen deficiency.Chris Lattner2009-07-301-0/+46
| | | | llvm-svn: 77598
* fix a unitialized pointer in NamedMDNode (and reenable unittest)Benjamin Kramer2009-07-301-1/+1
| | | | llvm-svn: 77597
* Allow targets to define libcall names for mem(cpy,set,move) intrinsics, ↵Sanjiv Gupta2009-07-302-3/+9
| | | | | | rather than hardcoding them in DAG lowering. llvm-svn: 77586
* Add a note.Evan Cheng2009-07-301-0/+20
| | | | llvm-svn: 77584
* Optimize some common usage patterns of atomic built-ins ↵Evan Cheng2009-07-306-14/+281
| | | | | | | | | | | | __sync_add_and_fetch() and __sync_sub_and_fetch. When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. llvm-svn: 77582
* Switch obvious clients to Twine instead of utostr (when they were already usingDaniel Dunbar2009-07-305-20/+15
| | | | | | | | | a Twine, e.g., for names). - I am a little ambivalent about this; we don't want the string conversion of utostr, but using overload '+' mixed with string and integer arguments is sketchy. On the other hand, this particular usage is something of an idiom. llvm-svn: 77579
* Keep track of references to mem(cpy,move,set) and then print only one externSanjiv Gupta2009-07-302-2/+41
| | | | | | declaration for them. llvm-svn: 77578
* Twine: Provide [u]int{32,64} conversions via implicit constructors instead ofDaniel Dunbar2009-07-301-6/+18
| | | | | | explicitly. llvm-svn: 77576
* Equal SCEVs of a subscript give rise to dependence.Andreas Bolka2009-07-301-1/+11
| | | | llvm-svn: 77570
* TypoNate Begeman2009-07-301-1/+1
| | | | llvm-svn: 77568
* Add a new register class to describe operands that can't be SP,Dan Gohman2009-07-305-38/+189
| | | | | | | due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
* Check null NameMDNode elements.Devang Patel2009-07-301-4/+8
| | | | llvm-svn: 77559
* Eliminate a bunch of redundant tables.Dan Gohman2009-07-301-167/+61
| | | | llvm-svn: 77558
* Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.Bob Wilson2009-07-301-1/+19
| | | | llvm-svn: 77557
* Use array_endof instead of doing it manually.Dan Gohman2009-07-301-27/+20
| | | | llvm-svn: 77553
* print single NamedMDNode.Devang Patel2009-07-301-3/+45
| | | | llvm-svn: 77549
* tbb / tbh instructions only branch forward, not backwards.Evan Cheng2009-07-291-2/+4
| | | | llvm-svn: 77522
* Add VFP3 D registers to the DPR register class.Evan Cheng2009-07-291-1/+3
| | | | llvm-svn: 77521
* In TrimAllocationToSize, if a block is below the minimum allocation size,Nicolas Geoffray2009-07-291-1/+4
| | | | | | | there is no new block added to the free list. Therefore on the next startFunctionBody call, a new slab must be allocated. llvm-svn: 77520
* Eliminate a few unused-variable warningsDouglas Gregor2009-07-294-7/+0
| | | | llvm-svn: 77519
* Read and write NamedMDNode.Devang Patel2009-07-293-1/+68
| | | | llvm-svn: 77517
* Move types back to the 2.5 API.Owen Anderson2009-07-2953-356/+235
| | | | llvm-svn: 77516
* Print named metadata.Devang Patel2009-07-291-0/+25
| | | | llvm-svn: 77513
* Fix PR4645 which was fallout from the fix for PR4641.Daniel Dunbar2009-07-291-8/+15
| | | | | | - Call RAUW to delete all instructions (this is a patch from Nick Lewycky). llvm-svn: 77512
* There is no need to keep name ref in NamedMDNode.Devang Patel2009-07-292-10/+6
| | | | llvm-svn: 77511
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