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* Remove the variable only used by assert to avoid the build failureJiangning Liu2013-11-281-2/+2
| | | | | | caused by build options [-Werror,-Wunused-variable]. llvm-svn: 195905
* AArch64: Fix a bug about disassembling post-index load single element to 4 ↵Hao Liu2013-11-281-4/+4
| | | | | | vectors llvm-svn: 195903
* Check in conditional branches for constant islands. Still need to finishReed Kotler2013-11-282-5/+157
| | | | | | | | | | | | conditional branches for very large targets. That will be the next small patch. Everything now should in principle work as good (functionality wise) as without constant islands so we decided at Mips/Imagination to make constant islands the default for Mips16 now so that it will get excercised a lot and this port is still experimentatl though hopefully soon we will change the status. Some more cleanup and code review is in order but things are converging fast. llvm-svn: 195902
* [mips] Redefine TAILCALL as a pseudo instruction.Akira Hatanaka2013-11-273-10/+15
| | | | | | No functionality change. llvm-svn: 195896
* DebugInfo: Do not include variables only referenced by templates in aranges.David Blaikie2013-11-271-3/+6
| | | | | | | | ARanges included even extern variables referenced by pointer non-type template parameters even though that variable isn't part of this compilation unit. llvm-svn: 195895
* Add MipsOptimizePICCall.cpp to CMakeLists.txt.Akira Hatanaka2013-11-271-0/+1
| | | | llvm-svn: 195894
* [mips] Implement the following optimizations using dominance information toAkira Hatanaka2013-11-274-8/+305
| | | | | | | | | | | make PIC calls a little more efficient: 1. Remove instructions setting up $gp if it is known that a function has been called at least once. 2. Save the address of a called function in a register instead of loading it from the GOT at every call site. llvm-svn: 195892
* Add IIC_ prefix to PPC instruction-class namesHal Finkel2013-11-2713-2355/+2366
| | | | | | | | | | | | | This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
* Don't set GlobalPrefix to the default value.Rafael Espindola2013-11-272-2/+0
| | | | llvm-svn: 195884
* The R600 has its own asm printer which doesn't use GlobalPrefix. Drop it.Rafael Espindola2013-11-271-1/+0
| | | | llvm-svn: 195883
* R600: Expand vector FABSTom Stellard2013-11-271-0/+1
| | | | | NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195881
* R600/SI: Implement spilling of SGPRs v5Tom Stellard2013-11-276-13/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions. v2: - Fix encoding of Lane Mask - Use correct register flags, so we don't overwrite the low dword when restoring multi-dword registers. v3: - Register spilling seems to hang the GPU, so replace all shaders that need spilling with a dummy shader. v4: - Fix *LANE definitions - Change destination reg class for 32-bit SMRD instructions v5: - Remove small optimization that was crashing Serious Sam 3. https://bugs.freedesktop.org/show_bug.cgi?id=68224 https://bugs.freedesktop.org/show_bug.cgi?id=71285 NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195880
* R600/SI: Use SGPR_32 register class for 32-bit SMRD outputsTom Stellard2013-11-271-2/+5
| | | | | | | | Writing to the M0 register from an SMRD instruction hangs the GPU, so we need to use the SGPR_32 register class, which does not include M0. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195879
* R600: Add support for ISD::FROUNDTom Stellard2013-11-273-4/+18
| | | | | NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195878
* Show stackmap entry encodings in stackmap debug logs. This makes it easier toLang Hames2013-11-271-23/+27
| | | | | | | cross-reference debug output with encoded stack-maps, and to create stackmap test-cases. llvm-svn: 195874
* Remove dead code.Rafael Espindola2013-11-271-36/+4
| | | | | | MO_ExternalSymbol and MO_JumpTableIndex don't show up in inline asm. llvm-svn: 195861
* Convert two if sequences to switches.Rafael Espindola2013-11-271-10/+21
| | | | llvm-svn: 195859
* Use a switch.Rafael Espindola2013-11-271-5/+11
| | | | llvm-svn: 195857
* Use the same tls section name as msvc.Rafael Espindola2013-11-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently error in clang with: "error: thread-local storage is unsupported for the current target", but we can start to get the llvm level ready. When compiling template<typename T> struct foo { static __declspec(thread) int bar; }; template<typename T> __declspec(therad) int foo<T>::bar; template struct foo<int>; msvc produces SECTION HEADER #3 .tls$ name 0 physical address 0 virtual address 4 size of raw data 12F file pointer to raw data (0000012F to 00000132) 0 file pointer to relocation table 0 file pointer to line numbers 0 number of relocations 0 number of line numbers C0301040 flags Initialized Data COMDAT; sym= "public: static int foo<int>::bar" (?bar@?$foo@H@@2HA) 4 byte align Read Write gcc produces a ".data$__emutls_v.<symbol>" for the testcase with __declspec(thread) replaced with thread_local. llvm-svn: 195849
* Remove more dead code now that this is only used for inline asm.Rafael Espindola2013-11-271-4/+1
| | | | | | | MO_ConstantPoolIndex is handled in printLeaMemReference. MO_JumpTableIndex and MO_ExternalSymbol don't show up in inline asm. llvm-svn: 195847
* Fix the AArch64 NEON bug exposed by checking constant integer argument range ↵Jiangning Liu2013-11-272-164/+82
| | | | | | of ACLE intrinsics. llvm-svn: 195843
* Convert more methods in static helpers.Rafael Espindola2013-11-272-33/+26
| | | | llvm-svn: 195826
* Convert these methods into static functions.Rafael Espindola2013-11-272-58/+56
| | | | llvm-svn: 195825
* Cleanup and test X86AsmPrinter::printPCRelImm.Rafael Espindola2013-11-271-4/+0
| | | | | | | | | | | | | | It is only used for asm printing. On X86 we put basic block addresses on register before passing them to inline asm, so the MO_MachineBasicBlock case was dead. MO_ExternalSymbol was dead since any symbol being passed to inline asm is represented as MO_GlobalAddress. The MO_GlobalAddress and MO_Register cases were not tested. llvm-svn: 195824
* Fix comment in PPCA2ModelHal Finkel2013-11-271-1/+1
| | | | llvm-svn: 195807
* Remove dead argument.Rafael Espindola2013-11-271-17/+14
| | | | llvm-svn: 195806
* [AArch64] Add support for NEON scalar floating-point absolute difference.Chad Rosier2013-11-271-0/+5
| | | | llvm-svn: 195803
* Use simple section names for COMDAT sections on COFF.Rafael Espindola2013-11-272-29/+32
| | | | | | | | | | | | With this patch we use simple names for COMDAT sections (like .text or .bss). This matches the MSVC behavior. When merging it is the COMDAT symbol that is used to decide if two sections should be merged, so there is no point in building a fancy name. This survived a bootstrap on mingw32. llvm-svn: 195798
* PR1860 - We can't save a list of ExtractElement instructions to CSE because ↵Nadav Rotem2013-11-261-16/+11
| | | | | | | | some of these instructions may be removed and optimized in future iterations. Instead we save a list of basic blocks that we need to CSE. llvm-svn: 195791
* 80-column fixups.Eric Christopher2013-11-263-3/+7
| | | | llvm-svn: 195790
* [AArch64] Add support for NEON scalar floating-point to integer convertChad Rosier2013-11-261-1/+63
| | | | | | instructions. llvm-svn: 195788
* LoopVectorizer: Truncate i64 trip counts of i32 phis if necessaryArnold Schwaighofer2013-11-261-0/+9
| | | | | | | | | | | In signed arithmetic we could end up with an i64 trip count for an i32 phi. Because it is signed arithmetic we know that this is only defined if the i32 does not wrap. It is therefore safe to truncate the i64 trip count to a i32 value. Fixes PR18049. llvm-svn: 195787
* Fix a bug related to constant islands for Mips16 and mips16/32 dual mode.Reed Kotler2013-11-261-3/+2
| | | | | | | The determination of when we are doing constant pools was being made too early in the asm printer. llvm-svn: 195781
* Refactor some code in SampleProfile.cppDiego Novillo2013-11-261-99/+112
| | | | | | | | | | | | | | | I'm adding new functionality in the sample profiler. This will require more data to be kept around for each function, so I moved the structure SampleProfile that we keep for each function into a separate class. There are no functional changes in this patch. It simply provides a new home where to place all the new data that I need to propagate weights through edges. There are some other name and minor edits throughout. llvm-svn: 195780
* Fix PR18054Michael Liao2013-11-261-7/+15
| | | | | | | | - Fix bug in (vsext (vzext x)) -> (vsext x) in SIGN_EXTEND_IN_REG lowering where we need to check whether x is a vector type (in-reg type) of i8, i16 or i32; otherwise, that optimization is not valid. llvm-svn: 195779
* DwarfDebug: Include type units in accelerator tables.David Blaikie2013-11-262-25/+31
| | | | | | | Since type units aren't in the CUMap, use the DwarfUnits list to iterate over units for tasks such as accelerator table building. llvm-svn: 195776
* Fix spurious return introduced by my earlier patch to DebugInfoRenato Golin2013-11-261-1/+0
| | | | llvm-svn: 195775
* PR18060 - When we RAUW values with ExtractElement instructions in some casesNadav Rotem2013-11-261-0/+8
| | | | | | | | we generate PHI nodes with multiple entries from the same basic block but with different values. Enabling CSE on ExtractElement instructions make sure that all of the RAUWed instructions are the same. llvm-svn: 195773
* Add return to DIType::VerifyRenato Golin2013-11-261-3/+3
| | | | | | | | Code scanner ran by Sylvestre Ledru got a no_return bug in DebugInfo.cpp. Adding the return statements that should be there. llvm-svn: 195772
* PR17925 bugfix.Stepan Dyatkovskiy2013-11-261-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Short description. This issue is about case of treating pointers as integers. We treat pointers as different if they references different address space. At the same time, we treat pointers equal to integers (with machine address width). It was a point of false-positive. Consider next case on 32bit machine: void foo0(i32 addrespace(1)* %p) void foo1(i32 addrespace(2)* %p) void foo2(i32 %p) foo0 != foo1, while foo1 == foo2 and foo0 == foo2. As you can see it breaks transitivity. That means that result depends on order of how functions are presented in module. Next order causes merging of foo0 and foo1: foo2, foo0, foo1 First foo0 will be merged with foo2, foo0 will be erased. Second foo1 will be merged with foo2. Depending on order, things could be merged we don't expect to. The fix: Forbid to treat any pointer as integer, except for those, who belong to address space 0. llvm-svn: 195769
* Rename DwarfException methods so the new names are consistent with ↵Timur Iskhodzhanov2013-11-266-50/+50
| | | | | | DwarfDebug and the style guide llvm-svn: 195763
* Darwin-ARM: use movw/movt for static relocationsTim Northover2013-11-262-8/+4
| | | | llvm-svn: 195759
* [PM] Factor the overwhelming majority of the interface boiler plate outChandler Carruth2013-11-261-49/+42
| | | | | | | | | | | | | | of the two analysis managers into a CRTP base class that can be shared and re-used in building any analysis manager. This will in turn simplify adding yet another analysis manager to the system. The base class provides all of the interface sugar for the analysis manager delegating the functionality back through DerivedT methods which operate on simple pass IDs. It also provides the pass registration, storage, and lookup system which is common across the various formulations of analysis managers. llvm-svn: 195747
* [SystemZ] Fix incorrect use of RISBG for a zero-extended right shiftRichard Sandiford2013-11-261-19/+8
| | | | | | | | | We would wrongly transform the testcase into the equivalent of an AND with 1. The problem was that, when testing whether the shifted-in bits of the right shift were significant, we used the width of the final zero-extended result rather than the width of the shifted value. llvm-svn: 195731
* [PM] Split the CallGraph out from the ModulePass which creates theChandler Carruth2013-11-2612-93/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CallGraph. This makes the CallGraph a totally generic analysis object that is the container for the graph data structure and the primary interface for querying and manipulating it. The pass logic is separated into its own class. For compatibility reasons, the pass provides wrapper methods for most of the methods on CallGraph -- they all just forward. This will allow the new pass manager infrastructure to provide its own analysis pass that constructs the same CallGraph object and makes it available. The idea is that in the new pass manager, the analysis pass's 'run' method returns a concrete analysis 'result'. Here, that result is a 'CallGraph'. The 'run' method will typically do only minimal work, deferring much of the work into the implementation of the result object in order to be lazy about computing things, but when (like DomTree) there is *some* up-front computation, the analysis does it prior to handing the result back to the querying pass. I know some of this is fairly ugly. I'm happy to change it around if folks can suggest a cleaner interim state, but there is going to be some amount of unavoidable ugliness during the transition period. The good thing is that this is very limited and will naturally go away when the old pass infrastructure goes away. It won't hang around to bother us later. Next up is the initial new-PM-style call graph analysis. =] llvm-svn: 195722
* [PM] Reformat some code with clang-format as I'm going to be editting asChandler Carruth2013-11-261-21/+12
| | | | | | | part of generalizing the call graph infrastructure for the new pass manager. llvm-svn: 195718
* Refactored the implementation of AArch64 NEON instruction ZIP, UZPKevin Qin2013-11-263-328/+226
| | | | | | | and TRN. Fix a bug when mixed use of vget_high_u8() and vuzp_u8(). llvm-svn: 195716
* [AArch64]Implement 128 bit register copy with NEON.Kevin Qin2013-11-261-17/+19
| | | | llvm-svn: 195713
* StackMap: Implement support for DirectMemRefOp.Andrew Trick2013-11-264-10/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A Direct stack map location records the address of frame index. This address is itself the value that the runtime requested. This differs from IndirectMemRefOp locations, which refer to a stack locations from which the requested values must be loaded. Direct locations can directly communicate the address if an alloca, while IndirectMemRefOp handle register spills. For example: entry: %a = alloca i64... llvm.experimental.stackmap(i32 <ID>, i32 <shadowBytes>, i64* %a) Since both the alloca and stackmap intrinsic are in the entry block, and the intrinsic takes the address of the alloca, the runtime can assume that LLVM will not substitute alloca with any intervening value. This must be verified by the runtime by checking that the stack map's location is a Direct location type. The runtime can then determine the alloca's relative location on the stack immediately after compilation, or at any time thereafter. This differs from Register and Indirect locations, because the runtime can only read the values in those locations when execution reaches the instruction address of the stack map. llvm-svn: 195712
* whitespaceAndrew Trick2013-11-261-5/+5
| | | | llvm-svn: 195711
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