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* Use getVNInfoBefore() when it makes sense.Jakob Stoklund Olesen2011-11-144-8/+7
| | | | llvm-svn: 144517
* Teach machine block placement to cope with unnatural loops. These don'tChandler Carruth2011-11-141-21/+60
| | | | | | | | | | | | | | | | | | get loop info structures associated with them, and so we need some way to make forward progress selecting and placing basic blocks. The technique used here is pretty brutal -- it just scans the list of blocks looking for the first unplaced candidate. It keeps placing blocks like this until the CFG becomes tractable. The cost is somewhat unfortunate, it requires allocating a vector of all basic block pointers eagerly. I have some ideas about how to simplify and optimize this, but I'm trying to get the logic correct first. Thanks to Benjamin Kramer for the reduced test case out of GCC. Sadly there are other bugs that GCC is tickling that I'm reducing and working on now. llvm-svn: 144516
* Use kill slots instead of the previous slot in shrinkToUses.Jakob Stoklund Olesen2011-11-131-13/+14
| | | | | | It's more natural to use the actual end points. llvm-svn: 144515
* Cleanup some 80-columns violations and poor formatting. These snuck byChandler Carruth2011-11-131-5/+9
| | | | | | when I was reading through the code for style. llvm-svn: 144513
* Terminate all dead defs at the dead slot instead of the 'next' slot.Jakob Stoklund Olesen2011-11-133-8/+8
| | | | | | | | | | | | | | | | | | | This makes no difference for normal defs, but early clobber dead defs now look like: [Slot_EarlyClobber; Slot_Dead) instead of: [Slot_EarlyClobber; Slot_Register). Live ranges for normal dead defs look like: [Slot_Register; Slot_Dead) as before. llvm-svn: 144512
* Simplify early clobber slots a bit.Jakob Stoklund Olesen2011-11-131-12/+3
| | | | llvm-svn: 144507
* Enhance the assertion mechanisms in place to make it easier to catchChandler Carruth2011-11-131-5/+28
| | | | | | | | when we fail to place all the blocks of a loop. Currently this is happening for unnatural loops, and this logic helps more immediately point to the problem. llvm-svn: 144504
* Rename SlotIndexes to match how they are used.Jakob Stoklund Olesen2011-11-1313-103/+107
| | | | | | | | | | | | | | | | | | | | The old naming scheme (load/use/def/store) can be traced back to an old linear scan article, but the names don't match how slots are actually used. The load and store slots are not needed after the deferred spill code insertion framework was deleted. The use and def slots don't make any sense because we are using half-open intervals as is customary in C code, but the names suggest closed intervals. In reality, these slots were used to distinguish early-clobber defs from normal defs. The new naming scheme also has 4 slots, but the names match how the slots are really used. This is a purely mechanical renaming, but some of the code makes a lot more sense now. llvm-svn: 144503
* Add BLSI, BLSMSK, and BLSR to getTargetNodeName.Craig Topper2011-11-131-2/+6
| | | | llvm-svn: 144502
* Teach MBP to force-merge layout successors for blocks with unanalyzableChandler Carruth2011-11-131-3/+20
| | | | | | | | | | | | | | | | | branches that also may involve fallthrough. In the case of blocks with no fallthrough, we can still re-order the blocks profitably. For example instruction decoding will in some cases continue past an indirect jump, making laying out its most likely successor there profitable. Note, no test case. I don't know how to write a test case that exercises this logic, but it matches the described desired semantics in discussions with Jakob and others. If anyone has a nice example of IR that will trigger this, that would be lovely. Also note, there are still assertion failures in real world code with this. I'm digging into those next, now that I know this isn't the cause. llvm-svn: 144499
* Hoist another gross nested loop into a helper method.Chandler Carruth2011-11-131-23/+44
| | | | llvm-svn: 144498
* Add a missing doxygen comment for a helper method.Chandler Carruth2011-11-131-0/+6
| | | | llvm-svn: 144497
* Hoist a nested loop into its own method.Chandler Carruth2011-11-131-33/+53
| | | | llvm-svn: 144496
* Rewrite #3 of machine block placement. This is based somewhat on theChandler Carruth2011-11-131-139/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | second algorithm, but only loosely. It is more heavily based on the last discussion I had with Andy. It continues to walk from the inner-most loop outward, but there is a key difference. With this algorithm we ensure that as we visit each loop, the entire loop is merged into a single chain. At the end, the entire function is treated as a "loop", and merged into a single chain. This chain forms the desired sequence of blocks within the function. Switching to a single algorithm removes my biggest problem with the previous approaches -- they had different behavior depending on which system triggered the layout. Now there is exactly one algorithm and one basis for the decision making. The other key difference is how the chain is formed. This is based heavily on the idea Andy mentioned of keeping a worklist of blocks that are viable layout successors based on the CFG. Having this set allows us to consistently select the best layout successor for each block. It is expensive though. The code here remains very rough. There is a lot that needs to be done to clean up the code, and to make the runtime cost of this pass much lower. Very much WIP, but this was a giant chunk of code and I'd rather folks see it sooner than later. Everything remains behind a flag of course. I've added a couple of tests to exercise the issues that this iteration was motivated by: loop structure preservation. I've also fixed one test that was exhibiting the broken behavior of the previous version. llvm-svn: 144495
* The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier2011-11-131-10/+16
| | | | | | mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. llvm-svn: 144494
* Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier2011-11-131-0/+1
| | | | | | failures. llvm-svn: 144492
* Fix comments.Chad Rosier2011-11-131-3/+3
| | | | llvm-svn: 144490
* Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier2011-11-131-32/+91
| | | | | | | | | | | | | SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 llvm-svn: 144488
* Prune more RALinScan. RALinScan was also here!NAKAMURA Takumi2011-11-131-1/+0
| | | | llvm-svn: 144487
* More dead code elimination in VirtRegMap.Jakob Stoklund Olesen2011-11-132-26/+0
| | | | | | This thing is looking a lot like a virtual register map now. llvm-svn: 144486
* Stop tracking spill slot uses in VirtRegMap.Jakob Stoklund Olesen2011-11-136-82/+2
| | | | | | | Nobody cared, StackSlotColoring scans the instructions to find used stack slots. llvm-svn: 144485
* Remove dead code and data from VirtRegMap.Jakob Stoklund Olesen2011-11-132-324/+2
| | | | | | | Most of this stuff was supporting the old deferred spill code insertion mechanism. Modern spillers just edit machine code in place. llvm-svn: 144484
* Stop tracking unused registers in VirtRegMap.Jakob Stoklund Olesen2011-11-133-82/+3
| | | | | | | The information was only used by the register allocator in StackSlotColoring. llvm-svn: 144482
* Remove the -color-ss-with-regs option.Jakob Stoklund Olesen2011-11-131-306/+2
| | | | | | | | | It was off by default. The new register allocators don't have the problems that made it necessary to reallocate registers during stack slot coloring. llvm-svn: 144481
* Delete VirtRegRewriter.Jakob Stoklund Olesen2011-11-133-2666/+0
| | | | | | And there was much rejoicing. llvm-svn: 144480
* Switch PBQP to VRM's trivial rewriter.Jakob Stoklund Olesen2011-11-131-4/+1
| | | | | | The very complicated VirtRegRewriter is going away. llvm-svn: 144479
* Delete the old spilling framework from LiveIntervalAnalysis.Jakob Stoklund Olesen2011-11-121-1193/+0
| | | | | | This is dead code, all register allocators use InlineSpiller. llvm-svn: 144478
* Delete the 'standard' spiller with used the old spilling framework.Jakob Stoklund Olesen2011-11-121-45/+2
| | | | | | The current register allocators all use the inline spiller. llvm-svn: 144477
* Switch PBQP to the modern InlineSpiller framework.Jakob Stoklund Olesen2011-11-121-40/+11
| | | | | | | | | | | It is worth noting that the old spiller would split live ranges around basic blocks. The new spiller doesn't do that. PBQP should do its own live range splitting with SplitEditor::splitSingleBlock() if desired. See RAGreedy::tryBlockSplit(). llvm-svn: 144476
* Delete the linear scan register allocator.Jakob Stoklund Olesen2011-11-123-1549/+0
| | | | | | | | | RegAllocGreedy has been the default for six months now. Deleting RegAllocLinearScan makes it possible to also delete VirtRegRewriter and clean up the spiller code. llvm-svn: 144475
* Add more AVX2 shift lowering support. Move AVX2 variable shift to use ↵Craig Topper2011-11-122-62/+153
| | | | | | patterns instead of custom lowering code. llvm-svn: 144457
* Don't try to loop on iterators that are potentially invalidated inside the ↵Nick Lewycky2011-11-121-0/+18
| | | | | | loop. Fixes PR11361! llvm-svn: 144454
* Fix typo.Akira Hatanaka2011-11-121-1/+1
| | | | llvm-svn: 144453
* Implement Mips64's handling of byval arguments in LowerCall.Akira Hatanaka2011-11-121-12/+100
| | | | llvm-svn: 144452
* Fixed the MCJIT so that it can emit not only instanceSean Callanan2011-11-121-6/+6
| | | | | | | | | | | | | | methods but also class methods for Objective-C. Clang emits Objective-C method names with '\1' at the beginning, and the JIT has pre-existing logic to try prepending a '\1' when searching a module for an instance method (that is, a method whose name begins with '-'). I simply extended it to do the same thing when it encountered a class method (a method whose name begins with '+'). llvm-svn: 144451
* Implement Mips64's handling of byval arguments in LowerFormalArguments.Akira Hatanaka2011-11-121-18/+60
| | | | llvm-svn: 144449
* 64-bit arbitrary immediate pattern.Akira Hatanaka2011-11-121-0/+4
| | | | llvm-svn: 144448
* Function for handling byval arguments.Akira Hatanaka2011-11-122-4/+43
| | | | llvm-svn: 144447
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar2011-11-1231-42/+31
| | | | | | | | versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. llvm-svn: 144444
* Make sure scalarrepl picks the correct alloca when it rewrites a bitcast. ↵Eli Friedman2011-11-121-2/+10
| | | | | | Fixes PR11353. llvm-svn: 144442
* The dwarf standard says that the only differences between a out-of-lineRafael Espindola2011-11-121-0/+7
| | | | | | | | | | | | | | instance and a concrete inlined instance are the use of DW_TAG_subprogram instead of DW_TAG_inlined_subroutine and the who owns the tree. We were also omitting DW_AT_inline from the abstract roots. To fix this, make sure we mark abstract instance roots with DW_AT_inline even when we have only out-of-line instances referring to them with DW_AT_abstract_origin. FileCheck is not a very good tool for tests like this, maybe we should add a -verify mode to llvm-dwarfdump. llvm-svn: 144441
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-124-79/+22
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
* Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman2011-11-122-11/+11
| | | | | | runs. Fixes PR11029. llvm-svn: 144438
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-123-11/+6
| | | | | | Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
* Some cleanup and bulletproofing for node replacement in LegalizeDAG. To ↵Eli Friedman2011-11-111-57/+59
| | | | | | | | maintain LegalizeDAG invariants, whenever we a node is replaced, we must attempt to delete it, and if it still has uses after it is replaced (which can happen in rare cases due to CSE), we must revisit it. llvm-svn: 144432
* Oops. Missed the isel half of this. revert while I sort that out.Jim Grosbach2011-11-111-3/+4
| | | | llvm-svn: 144431
* ARM assembly parsing for VST1 two-register encoding.Jim Grosbach2011-11-111-4/+3
| | | | llvm-svn: 144430
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+9
| | | | llvm-svn: 144427
* Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier2011-11-111-10/+60
| | | | llvm-svn: 144426
* CMake: Fix CMake build for new Mips tblgen file.Daniel Dunbar2011-11-111-0/+1
| | | | llvm-svn: 144423
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