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* ARM vldm and vstm VFP instructions can take a data type suffix.Jim Grosbach2011-11-112-1/+23
| | | | | | | | | | | | It's ignored by the assembler when present, but is legal syntax. Other instructions have something similar, but for some mnemonics it's only sometimes not significant, so this quick check in the parser will need refactored into something more robust soon-ish. This gets some basics working in the meantime. Partial for rdar://10435264 llvm-svn: 144422
* LLVMBuild: Alphabetize required_libraries lists.Daniel Dunbar2011-11-112-2/+2
| | | | llvm-svn: 144416
* Target/LLVMBuild: Order components alphabetically.Daniel Dunbar2011-11-111-16/+16
| | | | llvm-svn: 144415
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-1113-130/+475
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Nuke no longer accurate comment.Jim Grosbach2011-11-111-3/+0
| | | | llvm-svn: 144411
* Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick2011-11-111-0/+22
| | | | | | Fixes PR8113. llvm-svn: 144409
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-27/+45
| | | | | | rdar://9672822 llvm-svn: 144407
* Add a custom safepoint method, in order for language implementers to decide ↵Nicolas Geoffray2011-11-111-2/+15
| | | | | | which machine instruction gets to be a safepoint. llvm-svn: 144399
* Remove FIXME comment that should have been removed with r144351.Bob Wilson2011-11-111-1/+0
| | | | llvm-svn: 144392
* allow non-device function calls in PTX when natively handling device-side printfDan Bailey2011-11-114-23/+129
| | | | llvm-svn: 144388
* add rules in tabgen for PTX COPY_ADDRESS of frameindexDan Bailey2011-11-111-0/+6
| | | | llvm-svn: 144387
* Clients are responsible for initializing the targets, remove it from the ↵Benjamin Kramer2011-11-114-32/+1
| | | | | | | | | | disassembler API. This will break users of the LLVMCreateDisasm API (not that I know of any). They have to call the LLVMInitializeAll* functions from llvm-c/Target.h themselves now. edis' C API in all its horribleness should be unaffected. llvm-svn: 144385
* Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.Benjamin Kramer2011-11-111-1/+1
| | | | llvm-svn: 144384
* Remove the unnecessary dependency on libMBlazeCodeGen from ↵Benjamin Kramer2011-11-112-9/+2
| | | | | | libMBlazeDisassembler. llvm-svn: 144383
* Add lowering for AVX2 shift instructions.Craig Topper2011-11-112-117/+167
| | | | llvm-svn: 144380
* Rename variables to avoid confusion. No functionallity change intended.Chad Rosier2011-11-111-18/+18
| | | | llvm-svn: 144377
* Add support for using immediates with select instructions.Chad Rosier2011-11-111-8/+40
| | | | | | rdar://10412592 llvm-svn: 144376
* Do not try to detect DAG combine patterns for integer multiply-add/sub if valueAkira Hatanaka2011-11-111-2/+4
| | | | | | | type is not i32. MIPS does not have 64-bit integer multiply-add/sub instructions. llvm-svn: 144373
* 64-bit atomic instructions.Akira Hatanaka2011-11-113-64/+194
| | | | llvm-svn: 144372
* Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.Akira Hatanaka2011-11-111-1/+2
| | | | llvm-svn: 144371
* Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.Akira Hatanaka2011-11-113-12/+27
| | | | llvm-svn: 144370
* 64-bit versions of jal, jalr and bal.Akira Hatanaka2011-11-112-0/+27
| | | | llvm-svn: 144368
* Emit Mips64's sequence of instructions that set global register in prologue.Akira Hatanaka2011-11-111-1/+21
| | | | llvm-svn: 144367
* Fix printing of MCSymbolRegExpr. Needs three closing parentheses forAkira Hatanaka2011-11-111-1/+4
| | | | | | VK_Mips_GPOFF_HI/LO. llvm-svn: 144366
* Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman2011-11-111-0/+1
| | | | llvm-svn: 144361
* Initialize variable.Eric Christopher2011-11-111-1/+2
| | | | llvm-svn: 144360
* When loading a value, treat an i1 as an i8.Chad Rosier2011-11-111-0/+1
| | | | llvm-svn: 144356
* If we have a DIE with an AT_specification use that instead of the normalEric Christopher2011-11-111-7/+10
| | | | | | addr DIE when adding to the dwarf accelerator tables. llvm-svn: 144354
* Get rid of an optimization in SCCP which appears to have many issues. ↵Eli Friedman2011-11-111-167/+1
| | | | | | | | | | Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which lead to it trying to re-mark a value marked as a constant with a different value. It also appears to trigger very rarely. Fixes PR11357. llvm-svn: 144352
* Reenable compact unwinding now that <rdar://problem/10430076> is fixed.Bill Wendling2011-11-111-1/+1
| | | | llvm-svn: 144351
* If we have to reset the calculation of the compact encoding, then also reset theBill Wendling2011-11-111-0/+1
| | | | | | | "saved register" index. <rdar://problem/10430076> llvm-svn: 144350
* Add support for using MVN to materialize negative constants.Chad Rosier2011-11-111-3/+17
| | | | | | rdar://10412592 llvm-svn: 144348
* Disable compact unwind generation until I can solve the codegen problems.Bill Wendling2011-11-111-1/+2
| | | | llvm-svn: 144346
* LLVMBuild: Add explicit information on whether targets define an assembly ↵Daniel Dunbar2011-11-1110-0/+16
| | | | | | printer, assembly parser, or disassembler. llvm-svn: 144344
* Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.Jim Grosbach2011-11-101-0/+32
| | | | | | rdar://10429490 llvm-svn: 144338
* ARM let processInstruction() tranforms chain.Jim Grosbach2011-11-101-15/+37
| | | | llvm-svn: 144337
* Thumb2 parsing for push/pop w/ hi registers in the reglist.Jim Grosbach2011-11-101-2/+32
| | | | | | rdar://10130228. llvm-svn: 144331
* Thumb1 diagnostics for reglist on PUSH/POP fix.Jim Grosbach2011-11-101-2/+2
| | | | | | Was not checking the first register in the register list. llvm-svn: 144329
* Check in getOrCreateSubprogramDIE if a declaration exists and if so outputRafael Espindola2011-11-102-13/+12
| | | | | | | | it first. This is a more general fix to pr11300. llvm-svn: 144324
* Thumb MUL assembly parsing for 3-operand form.Jim Grosbach2011-11-101-7/+9
| | | | | | | | | Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 llvm-svn: 144322
* build/MBlazeDisassembler: Some compilers may generate an MBlaze disassemblerDaniel Dunbar2011-11-101-1/+7
| | | | | | | that depends on MBlazeCodeGen. This is a layering violation that should really be fixed. llvm-svn: 144321
* build/MCDisassembler: Fix required libraries list of MCDisassembler to useDaniel Dunbar2011-11-101-1/+3
| | | | | | all-targets instead of an explicit list. llvm-svn: 144320
* Make types and namespaces take multiple DIEs for the accelerator tablesEric Christopher2011-11-102-14/+24
| | | | | | as well. llvm-svn: 144319
* When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier2011-11-101-1/+2
| | | | | | | For correctness, disable this for now. rdar://10418009 llvm-svn: 144316
* ARM .thumb_func directive for quoted symbol names.Jim Grosbach2011-11-101-3/+3
| | | | | | | | | Use the getIdentifier() method of the token, not getString(), otherwise we keep the quotes as part of the symbol name, which we don't want. rdar://10428015 llvm-svn: 144315
* Fixed bug in DeadStoreElimination commit r144239Pete Cooper2011-11-101-1/+1
| | | | | | | | Size of data being pointed to wasn't always being checked so some small writes were killing big writes Fixes <rdar://problem/10426753> llvm-svn: 144312
* Move type handling to make sure we get all created types that aren'tEric Christopher2011-11-101-7/+5
| | | | | | forward decls and have names into the dwarf accelerator types table. llvm-svn: 144306
* Rework adding function names to the dwarf accelerator tables, allowEric Christopher2011-11-103-71/+86
| | | | | | multiple dies per function and support C++ basenames. llvm-svn: 144304
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-102-6/+50
| | | | | | More of rdar://9704684 llvm-svn: 144301
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-103-7/+37
| | | | | | Start of rdar://9704684 llvm-svn: 144293
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