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* Add bitcast to store of personality function.Kai Nacke2013-05-141-1/+3
| | | | | | | | | | The personality function is user defined and may have an arbitrary result type. The code assumes always i8*. This results in an assertion failure if a different type is used. A bitcast to i8* is added to prevent this failure. Reviewed by: Renato Golin, Bob Wilson llvm-svn: 181802
* PPC32: Fix stack collision between FP and CR save areas.Bill Schmidt2013-05-141-0/+1
| | | | | | | | | | | | | | | | | The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. llvm-svn: 181800
* Hexagon: Remove dead-code after unconditional return from addPreSched2.Jyotsna Verma2013-05-141-3/+0
| | | | llvm-svn: 181797
* R600/SI: Add processor type for Hainan asicTom Stellard2013-05-142-1/+3
| | | | | | | | | | Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181792
* Declare __clear_cache.Rafael Espindola2013-05-141-0/+1
| | | | | | | | GCC declares __clear_cache in the gnu modes (-std=gnu++98, -std=gnu++11), but not in the strict modes (-std=c++98, -std=c++11). This patch declares it and therefore fixes the build when using one of the strict modes. llvm-svn: 181785
* [SystemZ] Add disassembler supportRichard Sandiford2013-05-1411-6/+399
| | | | llvm-svn: 181777
* [SystemZ] Rework handling of constant PC-relative operandsRichard Sandiford2013-05-143-20/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GNU assembler treats things like: brasl %r14, 100 in the same way as: brasl %r14, .+100 rather than as a branch to absolute address 100. We implemented this in LLVM by creating an immediate operand rather than the usual expr operand, and by handling immediate operands specially in the code emitter. This was undesirable for (at least) three reasons: - the specialness of immediate operands was exposed to the backend MC code, rather than being limited to the assembler parser. - in disassembly, an immediate operand really is an absolute address. (Note that this means reassembling printed disassembly can't recreate the original code.) - it would interfere with any assembly manipulation that we might try in future. E.g. operations like branch shortening can change the relative position of instructions, but any code that updates sym+offset addresses wouldn't update an immediate "100" operand in the same way as an explicit ".+100" operand. This patch changes the implementation so that the assembler creates a "." label for immediate PC-relative operands, so that the operand to the MCInst is always the absolute address. The patch also adds some error checking of the offset. llvm-svn: 181773
* [SystemZ] Remove bogus isAsmParserOnlyRichard Sandiford2013-05-141-28/+22
| | | | | | | | | | Marking instructions as isAsmParserOnly stops them from being disassembled. However, in cases where separate asm and codegen versions exist, we actually want to disassemble to the asm ones. No functional change intended. llvm-svn: 181772
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-143-57/+79
| | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. llvm-svn: 181771
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-145-312/+326
| | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. llvm-svn: 181769
* Removed trailing whitespace.Michael Gottesman2013-05-141-4/+4
| | | | llvm-svn: 181760
* Fix typo.Reed Kotler2013-05-141-1/+1
| | | | llvm-svn: 181759
* Removed an unnamed namespace and forgot to make two of the functions insideReed Kotler2013-05-141-3/+5
| | | | | | "static". llvm-svn: 181754
* This is the first of three patches which creates stubs used forReed Kotler2013-05-141-0/+275
| | | | | | | | | | | | | | | | | | | | | | | Mips16/32 floating point interoperability. When Mips16 code calls external functions that would normally have some of its parameters or return values passed in floating point registers, it needs (Mips32) helper functions to do this because while in Mips16 mode there is no ability to access the floating point registers. In Pic mode, this is done with a set of predefined functions in libc. This case is already handled in llvm for Mips16. In static relocation mode, for efficiency reasons, the compiler generates stubs that the linker will use if it turns out that the external function is a Mips32 function. (If it's Mips16, then it does not need the helper stubs). These stubs are identically named and the linker knows about these tricks and will not create multiple copies and will delete them if they are not needed. llvm-svn: 181753
* StackColoring: don't clear an instruction's mem operand if the underlyingAkira Hatanaka2013-05-141-0/+5
| | | | | | | object is a PseudoSourceValue and PseudoSourceValue::isConstant returns true (i.e., points to memory that has a constant value). llvm-svn: 181751
* Assert that DIEEntries are constructed with non-null DIEsDavid Blaikie2013-05-141-1/+3
| | | | | | | This just brings a crash a little further forward from DWARF emission to DIE construction to make errors easier to diagnose. llvm-svn: 181748
* LoopVectorize: Handle loops with multiple forward inductionsArnold Schwaighofer2013-05-141-17/+40
| | | | | | | | | | | | We used to give up if we saw two integer inductions. After this patch, we base further induction variables on the chosen one like we do in the reverse induction and pointer induction case. Fixes PR15720. radar://13851975 llvm-svn: 181746
* [objc-arc-opts] Added debug statements when we set and unset whether a ↵Michael Gottesman2013-05-141-0/+2
| | | | | | pointer is known positive. llvm-svn: 181745
* [objc-arc-opts] In the presense of an alloca unconditionally remove RR pairs ↵Michael Gottesman2013-05-131-5/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if and only if we are both KnownSafeBU/KnownSafeTD rather than just either or. In the presense of a block being initialized, the frontend will emit the objc_retain on the original pointer and the release on the pointer loaded from the alloca. The optimizer will through the provenance analysis realize that the two are related (albiet different), but since we only require KnownSafe in one direction, will match the inner retain on the original pointer with the guard release on the original pointer. This is fixed by ensuring that in the presense of allocas we only unconditionally remove pointers if both our retain and our release are KnownSafe (i.e. we are KnownSafe in both directions) since we must deal with the possibility that the frontend will emit what (to the optimizer) appears to be unbalanced retain/releases. An example of the miscompile is: %A = alloca retain(%x) retain(%x) <--- Inner Retain store %x, %A %y = load %A ... DO STUFF ... release(%y) call void @use(%x) release(%x) <--- Guarding Release getting optimized to: %A = alloca retain(%x) store %x, %A %y = load %A ... DO STUFF ... release(%y) call void @use(%x) rdar://13750319 llvm-svn: 181743
* Move a couple more statistics inside '#ifndef NDEBUG'.Matt Beaumont-Gay2013-05-131-1/+1
| | | | | | Suppresses an unused-variable warning in -Asserts builds. llvm-svn: 181733
* Mips assembler: Assembler macro ADDIU $rs,immJack Carter2013-05-131-1/+2
| | | | | | | | | | | | | | This patch adds alias for addiu instruction which enables following syntax: addiu $rs,imm The macro is translated as: addiu $rs,$rs,imm Contributer: Vladimir Medic llvm-svn: 181729
* [objc-arc-opts] Add comment to BBState making it clear that ↵Michael Gottesman2013-05-131-0/+6
| | | | | | get{TopDown,BottomUp}PtrState will create a new PtrState object if it does not find a PtrState for Arg. llvm-svn: 181726
* Fix goofy commentary in PPCTargetObjectFile.cpp.Bill Schmidt2013-05-131-2/+2
| | | | llvm-svn: 181725
* PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.Bill Schmidt2013-05-134-0/+94
| | | | | | | | | | | | | | | | | | | | | This fixes warning messages observed in the oggenc application test in projects/test-suite. Special handling is needed for the 64-bit PowerPC SVR4 ABI when a constant is initialized with a pointer to a function in a shared library. Because a function address is implemented as the address of a function descriptor, the use of copy relocations can lead to problems with initialization. GNU ld therefore replaces copy relocations with dynamic relocations to be resolved by the dynamic linker. This means the constant cannot reside in the read-only data section, but instead belongs in .data.rel.ro, which is designed for constants containing dynamic relocations. The implementation creates a class PPC64LinuxTargetObjectFile inheriting from TargetLoweringObjectFileELF, which behaves like its parent except to place constants of this sort into .data.rel.ro. The test case is reduced from the oggenc application. llvm-svn: 181723
* Remove redundant variable introduced by r181682.Bob Wilson2013-05-131-1/+0
| | | | llvm-svn: 181721
* [objc-arc] Move the before optimization statistics gathering phase out of ↵Michael Gottesman2013-05-131-8/+7
| | | | | | | | | | | OptimizeIndividualCalls. This makes the statistics gathering completely independent of the actual optimization occuring, preventing any sort of bleeding over from occuring. Additionally, it simplifies a switch statement in the non-statistic gathering case. llvm-svn: 181719
* [mips] Add option -mno-ldc1-sdc1.Akira Hatanaka2013-05-133-4/+75
| | | | | | | | This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. llvm-svn: 181718
* Fix a bug that APFloat::fusedMultiplyAdd() mistakenly evaluate "14.5f * ↵Shuxin Yang2013-05-131-2/+27
| | | | | | -14.5f + 225.0f" to 225.0f. llvm-svn: 181715
* [mips] Define a helper function which creates an instruction with the sameAkira Hatanaka2013-05-132-0/+19
| | | | | | operands as the prototype instruction but with a different opcode. llvm-svn: 181714
* [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-137-29/+29
| | | | llvm-svn: 181713
* Remove unused fields and arguments.Rafael Espindola2013-05-133-13/+6
| | | | llvm-svn: 181706
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-134-11/+43
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
* Correctly preserve the input chain for potential tailcall nodes whoseLang Hames2013-05-131-1/+1
| | | | | | | | | | | | return values are bitcasts. The chain had previously been being clobbered with the entry node to the dag, which sometimes caused other code in the function to be erroneously deleted when tailcall optimization kicked in. <rdar://problem/13827621> llvm-svn: 181696
* Suppress GCC compiler warnings in release builds about variables that are onlyDuncan Sands2013-05-133-0/+3
| | | | | | read in asserts. llvm-svn: 181689
* SLPVectorizer: Swap LHS and RHS. No functionality change.Nadav Rotem2013-05-131-4/+4
| | | | llvm-svn: 181684
* Fix PR15950 A bug in DAG Combiner about undef maskHao Liu2013-05-131-10/+25
| | | | llvm-svn: 181682
* Remove the MachineMove class.Rafael Espindola2013-05-1329-115/+131
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* SLPVectorizer: Fix a bug in the code that generates extracts for values with ↵Nadav Rotem2013-05-121-7/+27
| | | | | | | | multiple users. The external user does not have to be in lane #0. We have to save the lane for each scalar so that we know which vector lane to extract. llvm-svn: 181674
* SLPVectorizer: Clear the map that maps between scalars to vectors after each ↵Nadav Rotem2013-05-121-0/+1
| | | | | | | | round of vectorization. Testcase in the next commit. llvm-svn: 181673
* InstCombine: Flip the order of two urem transformsDavid Majnemer2013-05-121-6/+6
| | | | | | | | | | | | | | There are two transforms in visitUrem that conflict with each other. *) One, if a divisor is a power of two, subtracts one from the divisor and turns it into a bitwise-and. *) The other unwraps both operands if they are surrounded by zext instructions. Flipping the order allows the subtraction to go beneath the sign extension. llvm-svn: 181668
* LoopVectorize: Use the widest induction variable typeArnold Schwaighofer2013-05-111-21/+69
| | | | | | | | | | | | | | | | | | | | | | Use the widest induction type encountered for the cannonical induction variable. We used to turn the following loop into an empty loop because we used i8 as induction variable type and truncated 1024 to 0 as trip count. int a[1024]; void fail() { int reverse_induction = 1023; unsigned char forward_induction = 0; while ((reverse_induction) >= 0) { forward_induction++; a[reverse_induction] = forward_induction; --reverse_induction; } } radar://13862901 llvm-svn: 181667
* LoopVectorize: Use variable instead of repeated function callArnold Schwaighofer2013-05-111-3/+4
| | | | | | No functionality change intended. llvm-svn: 181666
* LoopVectorize: Use IRBuilder interface in more placesArnold Schwaighofer2013-05-111-25/+13
| | | | | | No functionality change intended. llvm-svn: 181665
* StringRefize some debug accel table bits.Benjamin Kramer2013-05-113-7/+7
| | | | llvm-svn: 181663
* InstCombine: Turn urem to bitwise-and more oftenDavid Majnemer2013-05-111-20/+2
| | | | | | | Use isKnownToBeAPowerOfTwo in visitUrem so that we may more aggressively fold away urem instructions. llvm-svn: 181661
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-119-57/+46
| | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. llvm-svn: 181657
* Remove more dead code.Rafael Espindola2013-05-112-13/+0
| | | | llvm-svn: 181656
* Remove dead code.Rafael Espindola2013-05-102-82/+0
| | | | llvm-svn: 181649
* SLPVectorizer: Add support for trees with external users.Nadav Rotem2013-05-102-9/+55
| | | | | | | | | | | | | For example: bar() { int a = A[i]; int b = A[i+1]; B[i] = a; B[i+1] = b; foo(a); <--- a is used outside the vectorized expression. } llvm-svn: 181648
* Add a debug printNadav Rotem2013-05-101-0/+2
| | | | llvm-svn: 181647
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