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* Use the 'count' attribute to calculate the upper bound of an array.Bill Wendling2012-12-043-17/+20
| | | | | | | | | The count attribute is more accurate with regards to the size of an array. It also obviates the upper bound attribute in the subrange. We can also better handle an unbound array by setting the count to -1 instead of the lower bound to 1 and upper bound to 0. llvm-svn: 169312
* Reapply r160148 (reverted in r163570) fixing spurious breakpoints in modern GDBDavid Blaikie2012-12-041-1/+1
| | | | | | | | | | | | | | | | | This reapplies the fix for PR13303 now with more justification. Based on my execution of the GDB 7.5 test suite this results in: expected passes: 16101 -> 20890 (+30%) unexpected failures: 4826 -> 637 (-77%) There are 23 checks that used to pass and now fail. They are all in gdb.reverse. Investigating a few looks like they were accidentally passing due to extra breakpoints being set by this bug. They're generally due to the difference in end location between gcc and clang, the test suite is trying to set breakpoints on the closing '}' that clang doesn't associate with any instructions. llvm-svn: 169304
* Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky2012-12-043-4/+4
| | | | | | | | | textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. llvm-svn: 169291
* Add support for reduction variables when IF-conversion is enabled. Nadav Rotem2012-12-041-10/+23
| | | | llvm-svn: 169288
* Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count ↵Jyotsna Verma2012-12-043-17/+97
| | | | | | | | trailing/leading zeros) instructions. llvm-svn: 169287
* Add constant extender support to ALU32 instructions for V2.Jyotsna Verma2012-12-041-51/+79
| | | | llvm-svn: 169284
* This patch introduces initial-exec model support for thread-local storageBill Schmidt2012-12-0414-15/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on 64-bit PowerPC ELF. The patch includes code to handle external assembly and MC output with the integrated assembler. It intentionally does not support the "old" JIT. For the initial-exec TLS model, the ABI requires the following to calculate the address of external thread-local variable x: Code sequence Relocation Symbol ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x add 9,9,x@tls R_PPC64_TLS x The register 9 is arbitrary here. The linker will replace x@got@tprel with the offset relative to the thread pointer to the generated GOT entry for symbol x. It will replace x@tls with the thread-pointer register (13). The two test cases verify correct assembly output and relocation output as just described. PowerPC-specific selection node variants are added for the two instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted when an initial-exec global variable is encountered by PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo that uses the same LDrs support added for medium code model's LDtocL, with a different relocation type. The rest of the processing is straightforward. llvm-svn: 169281
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-0484-173/+170
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Give scalar if-converted blocks half the score because they are not always ↵Nadav Rotem2012-12-041-5/+5
| | | | | | executed due to CF. llvm-svn: 169223
* Add a comment about the requirement that the Windows.h header be last.Chandler Carruth2012-12-041-0/+2
| | | | | | | This comment has the dual effect of blocking reorderings with the sort_include script. llvm-svn: 169221
* Add a 'count' field to the DWARF subrange.Bill Wendling2012-12-042-3/+7
| | | | | | | | | The count field is necessary because there isn't a difference between the 'lo' and 'hi' attributes for a one-element array and a zero-element array. When the count is '0', we know that this is a zero-element array. When it's >=1, then it's a normal constant sized array. When it's -1, then the array is unbounded. llvm-svn: 169218
* Add the last part that is needed for vectorization of if-converted code.Nadav Rotem2012-12-041-162/+251
| | | | | | | | | | | | | | | | | Added the code that actually performs the if-conversion during vectorization. We can now vectorize this code: for (int i=0; i<n; ++i) { unsigned k = 0; if (a[i] > b[i]) <------ IF inside the loop. k = k * 5 + 3; a[i] = k; <---- K is a phi node that becomes vector-select. } llvm-svn: 169217
* [asan] add experimental -asan-realign-stack option (true by default, which ↵Kostya Serebryany2012-12-041-2/+7
| | | | | | does not change the current behavior) llvm-svn: 169216
* Add 'using' declarations to suppress -Woverloaded-virtual warnings.Matt Beaumont-Gay2012-12-043-0/+7
| | | | llvm-svn: 169214
* Move all operand definitions into HexagonOperands.tdJyotsna Verma2012-12-042-53/+57
| | | | llvm-svn: 169213
* Move generic Hexagon subtarget information into Hexagon.tdJyotsna Verma2012-12-042-64/+101
| | | | llvm-svn: 169212
* rdar://12329730 (2nd part, revised)Shuxin Yang2012-12-041-1/+2
| | | | | | | The type of shirt-right (logical or arithemetic) should remain unchanged when transforming "X << C1 >> C2" into "X << (C1-C2)" llvm-svn: 169209
* ASan: add initial support for handling llvm.lifetime intrinsics in ASan - ↵Alexey Samsonov2012-12-041-3/+108
| | | | | | emit calls into runtime library that poison memory for local variables when their lifetime is over and unpoison memory when their lifetime begins. llvm-svn: 169200
* Simplify code. No functionality change.Jakub Staszak2012-12-041-3/+1
| | | | llvm-svn: 169198
* Stack Alignment: when creating stack objects in MachineFrameInfo, make sureManman Ren2012-12-041-1/+24
| | | | | | | | | | | | | | | | the alignment is clamped to TargetFrameLowering.getStackAlignment if the target does not support stack realignment or the option "realign-stack" is off. This will cause miscompile if the address is treated as aligned and add is replaced with or in DAGCombine. Added a bool StackRealignable to TargetFrameLowering to check whether stack realignment is implemented for the target. Also added a bool RealignOption to MachineFrameInfo to check whether the option "realign-stack" is on. rdar://12713765 llvm-svn: 169197
* Use dyn_cast instead of isa and cast. No functionality change.Jakub Staszak2012-12-041-4/+4
| | | | llvm-svn: 169196
* LoopVectorize.cpp: Suppress a warning. [-Wunused-variable]NAKAMURA Takumi2012-12-041-2/+2
| | | | llvm-svn: 169195
* Fix whitespace.NAKAMURA Takumi2012-12-041-4/+3
| | | | llvm-svn: 169194
* Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.Jakob Stoklund Olesen2012-12-042-270/+0
| | | | | | | These functions have been replaced by TRI::getRegAllocationHints() which provides the same capabilities. llvm-svn: 169192
* Remove VirtRegMap::getRegAllocPref().Jakob Stoklund Olesen2012-12-041-11/+0
| | | | | | | Now that there can be multiple hint registers from targets, it doesn't make sense to have a function that returns 'the' preferred register. llvm-svn: 169190
* Use MRI::getSimpleHint() instead of getRegAllocPref() in remaining cases.Jakob Stoklund Olesen2012-12-042-1/+10
| | | | | | | | | Targets can provide multiple hints now, so getRegAllocPref() doesn't make sense any longer because it only returns one preferred register. Replace it with getSimpleHint() in the remaining heuristics. This function only llvm-svn: 169188
* Stack Alignment: move functions from header file MachineFrameInfo.h.Manman Ren2012-12-041-0/+44
| | | | | | | | | No functional change for this commit. The follow-up patch will add more stuff to these functions. rdar://12713765 llvm-svn: 169186
* RuntimeDyld: Fix up r169178. MSVC doesn't like "or".NAKAMURA Takumi2012-12-042-2/+2
| | | | llvm-svn: 169183
* rdar://12329730 (2nd part)Shuxin Yang2012-12-042-1/+90
| | | | | | | | | | | This change tries to simmplify E1 = " X >> C1 << C2" into : - E2 = "X << (C2 - C1)" if C2 > C1, or - E2 = "X >> (C1 - C2)" if C1 > C2, or - E2 = X if C1 == C2. Reviewed by Nadav. Thanks! llvm-svn: 169182
* Add VirtRegMap::hasKnownPreference().Jakob Stoklund Olesen2012-12-032-1/+10
| | | | | | | | Virtual registers with a known preferred register are prioritized by RAGreedy. This function makes the condition explicit without depending on getRegAllocPref(). llvm-svn: 169179
* Runtime dynamic linker for MCJIT should support MIPS BigEndian architecture.Akira Hatanaka2012-12-033-3/+4
| | | | | | | | | This small change adds support for that. It will make all MCJIT tests pass in make-check on BigEndian platforms. Patch by Petar Jovanovic. llvm-svn: 169178
* Classic JIT is still being supported by MIPS, along with MCJIT.Akira Hatanaka2012-12-033-11/+24
| | | | | | | | | This change adds endian-awareness to MipsJITInfo and emitWordLE in MipsCodeEmitter has become emitWord now to support both endianness. Patch by Petar Jovanovic. llvm-svn: 169177
* Minor tweaking to SmallVector static size.Michael Ilseman2012-12-031-1/+1
| | | | llvm-svn: 169176
* minor renaming, documentation and cleanups.Nadav Rotem2012-12-031-25/+21
| | | | llvm-svn: 169175
* Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are deadAkira Hatanaka2012-12-031-103/+0
| | | | | | | | code. Removing it. Patch by Petar Jovanovic. llvm-svn: 169174
* Use the new getRegAllocationHints() hook from AllocationOrder.Jakob Stoklund Olesen2012-12-032-79/+49
| | | | | | | This simplifies the hinting code quite a bit while making the targets easier to write at the same time. llvm-svn: 169173
* constify the cost APINadav Rotem2012-12-031-7/+7
| | | | llvm-svn: 169172
* IF-conversion: teach the cost-model how to grade if-converted loops.Nadav Rotem2012-12-031-15/+26
| | | | llvm-svn: 169171
* Implement ARMBaseRegisterInfo::getRegAllocationHints().Jakob Stoklund Olesen2012-12-032-0/+65
| | | | | | | This provides the same functionality as getRawAllocationOrder() for the even/odd hints, but without the many constant register arrays. llvm-svn: 169169
* Define store instructions with base+immediate offset addressing modeJyotsna Verma2012-12-032-185/+78
| | | | | | using multiclass. llvm-svn: 169168
* [Support] Make FileOutputBuffer work on Windows.Michael J. Spencer2012-12-031-55/+27
| | | | llvm-svn: 169167
* [Support][FileSystem] Fix open mode in resize_file on Windows.Michael J. Spencer2012-12-031-1/+1
| | | | llvm-svn: 169166
* Revert the header sort on this file.Michael J. Spencer2012-12-031-1/+1
| | | | | | | | "Windows.h" includes <Windows.h> which defines a bunch of stuff it shouldn't (even with all the restriction macros). We have no control over this file, so make it's scope as small as possible. llvm-svn: 169165
* moves doInitialization and doFinalization to the Pass class and removes some ↵Pedro Artigas2012-12-033-35/+6
| | | | | | | | unreachable code in MachineModuleInfo reviewed by Evan Cheng <evan.cheng@apple.com> llvm-svn: 169164
* Now that we have a basic if-conversion infrastructure we can rename theNadav Rotem2012-12-031-18/+18
| | | | | | "single basic block loop vectorizer" to "innermost loop vectorizer". llvm-svn: 169158
* Since this SmallVector immediately grows on the next line, don't waste stack ↵Michael Ilseman2012-12-031-1/+1
| | | | | | space. SmallVector is still needed due to existing APIs growing their arguments llvm-svn: 169157
* Add a new hook for providing register allocator hints more flexibly.Jakob Stoklund Olesen2012-12-031-0/+38
| | | | | | | | | | | | | | | | | | The TargetRegisterInfo::getRegAllocationHints() function is going to replace the existing mechanisms for providing target-dependent hints to the register allocator: ResolveRegAllocHint() and getRawAllocationOrder(). The new hook is more flexible because it allows the target to provide multiple preferred candidate registers for each virtual register, and it is easier to use because targets are not required to return a reference to a constant array like getRawAllocationOrder(). An optional VirtRegMap argument can be used to provide target-dependent hints that depend on the provisional assignments of other virtual registers. llvm-svn: 169154
* Define load instructions with base+immediate offset addressing modeJyotsna Verma2012-12-031-203/+73
| | | | | | using multiclass. llvm-svn: 169153
* Add initial support for IF-conversion. This patch implements the first 1/3,Nadav Rotem2012-12-031-134/+253
| | | | | | | | which is the legality of the if-conversion transformation. The next step is to implement the cost-model for the if-converted code as well as the vectorization itself. llvm-svn: 169152
* Define unsigned const-ext predicates.Jyotsna Verma2012-12-031-0/+128
| | | | llvm-svn: 169149
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