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* Define class MipsMCInstLower.Akira Hatanaka2011-07-073-0/+161
| | | | llvm-svn: 134633
* Change visibility of MipsAsmPrinter.Akira Hatanaka2011-07-072-60/+87
| | | | llvm-svn: 134630
* Define class MipsMCSymbolRefExpr.Akira Hatanaka2011-07-073-0/+126
| | | | llvm-svn: 134629
* Simplify MipsRegisterInfo::eliminateFrameIndex.Akira Hatanaka2011-07-071-33/+13
| | | | llvm-svn: 134628
* Rewrite comment in English.Evan Cheng2011-07-071-1/+1
| | | | llvm-svn: 134627
* Rename attribute 'thumb' to a more descriptive 'thumb-mode'.Evan Cheng2011-07-074-9/+10
| | | | llvm-svn: 134626
* Reverse order of operands of address operand mem so that the base operand comesAkira Hatanaka2011-07-077-50/+50
| | | | | | | before the offset. This change will enable simplification of function MipsRegisterInfo::eliminateFrameIndex. llvm-svn: 134625
* Add missing return statement.Akira Hatanaka2011-07-071-1/+3
| | | | llvm-svn: 134622
* If known DebugLocs do not match then two DBG_VALUE machine instructions are ↵Devang Patel2011-07-071-0/+5
| | | | | | | | | | | not identical. For example, DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ] DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ] These two MIs represent identical value, 3.31..., for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". llvm-svn: 134620
* Recognize mipseb as alias for mips for symmetry with mipsel.Joerg Sonnenberger2011-07-071-1/+2
| | | | llvm-svn: 134617
* Update CMake library dependenciesOscar Fuentes2011-07-071-2/+0
| | | | llvm-svn: 134616
* Fix CMake buildDouglas Gregor2011-07-071-0/+2
| | | | llvm-svn: 134614
* The VMLA instruction and its friends are not actually fused; they're plain oldCameron Zwarich2011-07-072-2/+2
| | | | | | multiply-accumulate instructions with separate rounding steps. llvm-svn: 134609
* Sink feature IsThumb into MC layer.Evan Cheng2011-07-074-15/+34
| | | | llvm-svn: 134608
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-0730-76/+118
| | | | llvm-svn: 134606
* type can be nullChris Lattner2011-07-071-1/+1
| | | | llvm-svn: 134601
* use a more efficient check for 'is metadata'Chris Lattner2011-07-071-5/+4
| | | | llvm-svn: 134599
* Use ArrayRef instead of a std::vector&.Bill Wendling2011-07-072-3/+3
| | | | llvm-svn: 134595
* Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. TheLang Hames2011-07-072-16/+36
| | | | | | | | | | | | | | | | hasPredecessorHelper function allows predecessors to be cached to speed up repeated invocations. This fixes PR10186. X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X) Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with empty Visited and Worklist sets (i.e. no caching over invocations). Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited and Worklist to speed up repeated calls. The Visited set is searched for X before going to the worklist to further search the DAG if necessary. llvm-svn: 134592
* Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng2011-07-074-113/+124
| | | | | | them down to MC layer. Also fix tests. llvm-svn: 134590
* Add a target hook to encode the compact unwind information.Bill Wendling2011-07-074-9/+114
| | | | llvm-svn: 134577
* Add DEBUG messages.Devang Patel2011-07-071-2/+9
| | | | llvm-svn: 134572
* Factor ARM triple parsing out of ARMSubtarget. Another step towards making ↵Evan Cheng2011-07-077-91/+84
| | | | | | ARM subtarget info available to MC. llvm-svn: 134569
* Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion.Devang Patel2011-07-071-2/+2
| | | | llvm-svn: 134568
* Fix a bug in the "expect" intrinsic lowering.Jakub Staszak2011-07-061-1/+4
| | | | llvm-svn: 134566
* When tail-merging multiple blocks, make sure to correctly update the live-in ↵Eli Friedman2011-07-062-10/+23
| | | | | | | | | | list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces. <rdar://problem/9716278> llvm-svn: 134565
* Remove dead code.Devang Patel2011-07-061-2/+0
| | | | llvm-svn: 134561
* Typo.Devang Patel2011-07-061-1/+1
| | | | llvm-svn: 134559
* Clean up the #includes.Bill Wendling2011-07-061-5/+4
| | | | llvm-svn: 134557
* Grammar and 80-col.Eric Christopher2011-07-061-7/+7
| | | | llvm-svn: 134555
* Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to ↵Devang Patel2011-07-061-11/+58
| | | | | | one alloca. llvm-svn: 134549
* Add ARM MC registry routines.Evan Cheng2011-07-067-12/+129
| | | | llvm-svn: 134547
* Rename files for consistency.Evan Cheng2011-07-067-10/+10
| | | | llvm-svn: 134546
* Mark ARM pseudo-instructions as isPseudo.Jim Grosbach2011-07-061-5/+3
| | | | | | | | | | This allows us to remove the (bogus and unneeded) encoding information from the pseudo-instruction class definitions. All of the pseudos that haven't been converted yet and still need encoding information instance from the normal instruction classes and explicitly set isCodeGenOnly, and so are distinct from this change. llvm-svn: 134540
* Simplify. Consolidate dbg.declare handling in AllocaPromoter.Devang Patel2011-07-063-25/+22
| | | | llvm-svn: 134538
* indvars -disable-iv-rewrite: ExprToMap lives in Pass data, so be moreAndrew Trick2011-07-061-1/+2
| | | | | | careful about referencing values. llvm-svn: 134537
* Remove un-used encoding info from Pseudo MLAv5.Jim Grosbach2011-07-061-4/+1
| | | | | | | Pseudo-instructions don't have encoding information, as they're lowered to real instructions by the time we're doing binary encoding. llvm-svn: 134533
* Fix missing triple support for RTEMS target.Eli Friedman2011-07-061-0/+2
| | | | llvm-svn: 134532
* indvars -disable-iv-rewrite: Added SimplifyCongruentIVs.Andrew Trick2011-07-061-1/+58
| | | | llvm-svn: 134530
* Constify getCompactUnwindRegNum.Bill Wendling2011-07-062-3/+3
| | | | llvm-svn: 134527
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-0617-32/+17
| | | | llvm-svn: 134525
* LICM: Remove trailing white spacesTobias Grosser2011-07-061-32/+32
| | | | llvm-svn: 134521
* LICM: Do not loose alignment on promotionTobias Grosser2011-07-061-8/+30
| | | | | | | | The promotion code lost any alignment information, when hoisting loads and stores out of the loop. This lead to incorrect aligned memory accesses. We now use the largest alignment we can prove to be correct. llvm-svn: 134520
* Introduce "expect" intrinsic instructions.Jakub Staszak2011-07-066-0/+183
| | | | llvm-svn: 134516
* Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that aKevin Enderby2011-07-061-1/+1
| | | | | | push with a small constant produces a 2-byte push. llvm-svn: 134501
* Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo.Evan Cheng2011-07-062-5/+0
| | | | llvm-svn: 134457
* Remove the ObjC ARC passes from the default optimization list, and addDan Gohman2011-07-051-4/+0
| | | | | | extension points to be used by clang. llvm-svn: 134444
* Preserve debug loc.Devang Patel2011-07-052-2/+2
| | | | llvm-svn: 134441
* Use memcmp.Benjamin Kramer2011-07-051-3/+1
| | | | llvm-svn: 134439
* Really fix typo :-(Rafael Espindola2011-07-051-1/+1
| | | | llvm-svn: 134436
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