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* MIRParser: Fix MIRParser not reporting nullptr on error.Matthias Braun2016-07-141-1/+1
| | | | | | | While some code paths in MIRParserImpl::parse() already returned nullptr in case of error one of the important ones did not. llvm-svn: 275355
* Synchronize LLVM and clang's ObjCDeclSpec::ObjCPropertyAttributeKind.Adrian Prantl2016-07-141-0/+6
| | | | | | | | | | This adds Clang-specific DWARF constants for nullability and ObjC class properties that are already generated by clang. This patch adds dwarfdump support and a more comprehensive testcase. <rdar://problem/27335745> llvm-svn: 275354
* [Object] Revert r275316, Archive::child_iterator changes, while I update lld.Lang Hames2016-07-144-47/+30
| | | | | | Should fix the bots broken by r275316. llvm-svn: 275353
* [ConstantFolding] Fold masked loadsDavid Majnemer2016-07-141-1/+36
| | | | | | | | | We can constant fold a masked load if the operands are appropriately constant. Differential Revision: http://reviews.llvm.org/D22324 llvm-svn: 275352
* Add EnableIPRA to TargetOptions, and move the cl::opt -enable-ipra to ↵Mehdi Amini2016-07-133-9/+12
| | | | | | | | | | | | TargetMachine.cpp Avoid exposing a cl::opt in a public header and instead promote this option in the API. Alternatively, we could land the cl::opt in CommandFlags.h so that it is available to every tool, but we would still have to find an option for clang. llvm-svn: 275348
* [IPRA] Set callee saved registers to none for local function when IPRA is ↵Mehdi Amini2016-07-133-10/+29
| | | | | | | | | | | | | | | | | | | | enabled. IPRA try to optimize caller saved register by propagating register usage information from callee to caller so it is beneficial to have caller saved registers compare to callee saved registers when IPRA is enabled. Please find more detailed explanation here https://groups.google.com/d/msg/llvm-dev/XRzGhJ9wtZg/tjAJqb0eEgAJ. This change makes local function do not have any callee preserved register when IPRA is enabled. A simple test case is also added to verify this change. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D21561 llvm-svn: 275347
* [JumpThreading] Delete commented out debug code; NFCSanjoy Das2016-07-131-3/+0
| | | | llvm-svn: 275346
* [ConstantFolding] Extend FoldReinterpretLoadFromConstPtr to handle negative ↵David Majnemer2016-07-131-10/+20
| | | | | | | | | offsets Treat loads which clip before the start of a global initializer the same way we treat clipping beyond the end of the initializer: use zeros. llvm-svn: 275345
* Move a transform from InstCombine to InstSimplify.David Majnemer2016-07-132-4/+9
| | | | | | | This transform doesn't require any new instructions, it can safely live in InstSimplify. llvm-svn: 275344
* Fix copy/paste bug in r275340.Michael Kuperstein2016-07-131-1/+1
| | | | llvm-svn: 275343
* MIRParser: Move SlotMapping and SourceMgr refs to PFS; NFCMatthias Braun2016-07-133-88/+69
| | | | | | | | Code cleanup: Move references to SlotMapping and SourceMgr into the PerFunctionMIParsingState to avoid unnecessary passing around in parameters. llvm-svn: 275342
* [DAG] Correctly chain masked loadsMichael Kuperstein2016-07-131-9/+8
| | | | | | | | | If a masked loads is not added to the chain, it should not reset the chain's root. This fixes the remaining part of PR28515. llvm-svn: 275340
* [SCCP] Have the logic for replacing insts with constant in a single place.Davide Italiano2016-07-131-53/+50
| | | | | | | | | The code was pretty much copy-pasted between SCCP and IPSCCP. The situation became clearly worse after I introduced the support for folding structs in SCCP. This commit is NFC as we currently (still) skip the replacement step in IPSCCP, but I'll change this soon. llvm-svn: 275339
* [Coverage] Mark a few methods const (NFC)Vedant Kumar2016-07-131-1/+1
| | | | llvm-svn: 275337
* [LAA] Don't hold on to DominatorTree in the analysis resultAdam Nemet2016-07-131-4/+5
| | | | llvm-svn: 275335
* [LAA] Don't hold on to TargetLibraryInfo in the analysis resultAdam Nemet2016-07-131-3/+4
| | | | llvm-svn: 275334
* [MI] Clean up some loops over MachineInstr::memoperands(). NFCJustin Lebar2016-07-131-14/+11
| | | | | | | Use range-based for loops and llvm::any_of instead of explicit iterators. llvm-svn: 275332
* [MI] Fix MachineInstr::isInvariantLoad.Justin Lebar2016-07-131-2/+1
| | | | | | | | | | | | | | | | | | | | Summary: Previously it would say we had an invariant load if any of the memory operands were invariant. But the load should be invariant only if *all* the memory operands are invariant. No testcase because this has proven to be very difficult to tickle in practice. As just one example, ARM's ldrd instruction, which loads 64 bits into two 32-bit regs, is theoretically affected by this. But when it's produced, it loses its memoperands' invariance bits! Reviewers: jfb Subscribers: llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D22318 llvm-svn: 275331
* MIRParser: Move MachineFunction reference into PFS; NFCMatthias Braun2016-07-133-141/+132
| | | | | | | | | | Code cleanup: The PerFunctionMIParsingState is per function, moving a reference into PFS we can avoid passing around the MachineFunction in an extra parameter most of the time. Also change most signatures to consistently pass PFS reference first. llvm-svn: 275329
* [LAA] Don't hold on to DataLayout in the analysis resultAdam Nemet2016-07-131-11/+8
| | | | | | | In fact, don't even pass this to the ctor since we can get it from the module. llvm-svn: 275326
* [LAA] Don't hold on to LoopInfo in the analysis resultAdam Nemet2016-07-131-3/+3
| | | | llvm-svn: 275325
* [LAA] Don't hold on to AliasAnalysis in the analysis resultAdam Nemet2016-07-131-3/+3
| | | | llvm-svn: 275322
* Fix a TODO in X86CallFrameOptimization to not rely on a codegen artifact.Nico Weber2016-07-131-10/+10
| | | | | | | | | This happens to make X86CallFrameOptimization in -O0 / FastISel builds as well, but it's not clear if the pass should run in that setup. http://reviews.llvm.org/D22314 llvm-svn: 275320
* Extended LoadStoreVectorizer to vectorize subchains.Alina Sbirlea2016-07-131-64/+118
| | | | | | | | | | | | | | Summary: LSV used to abort vectorizing a chain for interleaved load/store accesses that alias. Allow a valid prefix of the chain to be vectorized, mark just the prefix and retry vectorizing the remaining chain. Reviewers: llvm-commits, jlebar, arsenm Subscribers: mzolotukhin Differential Revision: http://reviews.llvm.org/D22119 llvm-svn: 275317
* [Object] Change Archive::child_iterator for better interop with Error/Expected.Lang Hames2016-07-134-30/+47
| | | | | | | | | | | | | | | | | | | | | | | See http://reviews.llvm.org/D22079 Changes the Archive::child_begin and Archive::children to require a reference to an Error. If iterator increment fails (because the archive header is damaged) the iterator will be set to 'end()', and the error stored in the given Error&. The Error value should be checked by the user immediately after the loop. E.g.: Error Err; for (auto &C : A->children(Err)) { // Do something with archive child C. } // Check the error immediately after the loop. if (Err) return Err; Failure to check the Error will result in an abort() when the Error goes out of scope (as guaranteed by the Error class). llvm-svn: 275316
* [MIR] Print on the given output instead of stderr.Quentin Colombet2016-07-131-1/+1
| | | | | | | | | | | | Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
* AMDGPU: Remove last AMDIL intrinsicsMatt Arsenault2016-07-132-11/+1
| | | | llvm-svn: 275309
* [SCCP] Factor out common code.Davide Italiano2016-07-131-8/+9
| | | | llvm-svn: 275308
* [SCCP] Use early return. NFCI.Davide Italiano2016-07-131-5/+5
| | | | llvm-svn: 275307
* Reverting r275284 due to platform-specific test failuresAndrew Kaylor2016-07-134-49/+0
| | | | llvm-svn: 275304
* [InstCombine] extend vector select matching for non-splat constantsSanjay Patel2016-07-131-3/+40
| | | | | | | | | | | | | | | In D21740, we discussed trying to make this a more general matcher. However, I didn't see a clean way to handle the regular m_Not cases and these non-splat vector patterns, so I've opted for the direct approach here. If there are other potential uses of areInverseVectorBitmasks(), we could move that helper function to a higher level. There is an open question as to which is of these forms should be considered the canonical IR: %sel = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> %b %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 3> Differential Revision: http://reviews.llvm.org/D22114 llvm-svn: 275289
* AMDGPU/SI: Emit the number of SGPR and VGPR spillsMarek Olsak2016-07-135-0/+30
| | | | | | | | | | | | | | | | | | | | | Summary: v2: don't count SGPRs spilled to scratch twice I think this is sufficient. It doesn't count private memory usage, which happens often and uses scratch but isn't technically a spill. The private memory usage can be computed by: [scratch_per_thread - vgpr_spills - a random multiple of SGPR spills]. The fact SGPR spills add very high numbers to the scratch size make that computation a guessing game, but I don't have a solution to that. Reviewers: tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D22197 llvm-svn: 275288
* Fix for Bug 26903, adds support to inline __builtin_mempcpyAndrew Kaylor2016-07-134-0/+49
| | | | | | | | Patch by Sunita Marathe Differential Revision: http://reviews.llvm.org/D21920 llvm-svn: 275284
* PatchableFunction: Skip pseudos that do not create codeMatthias Braun2016-07-131-5/+23
| | | | | | This fixes http://llvm.org/PR28524 llvm-svn: 275278
* [x86][SSE/AVX] optimize pcmp results better (PR28484)Sanjay Patel2016-07-131-0/+39
| | | | | | | | | | | | | | We know that pcmp produces all-ones/all-zeros bitmasks, so we can use that behavior to avoid unnecessary constant loading. One could argue that load+and is actually a better solution for some CPUs (Intel big cores) because shifts don't have the same throughput potential as load+and on those cores, but that should be handled as a CPU-specific later transformation if it ever comes up. Removing the load is the more general x86 optimization. Note that the uneven usage of vpbroadcast in the test cases is filed as PR28505: https://llvm.org/bugs/show_bug.cgi?id=28505 Differential Revision: http://reviews.llvm.org/D22225 llvm-svn: 275276
* [ConstantFolding] Use sdiv_ovDavid Majnemer2016-07-131-4/+4
| | | | | | This is a simplification, there should be no functional change. llvm-svn: 275273
* [X86][AVX512] Add support for VPERMILPD/VPERMILPS variable shuffle mask commentsSimon Pilgrim2016-07-131-9/+26
| | | | llvm-svn: 275272
* [X86][AVX] Add support for target shuffle combining to VPERMILPS variable ↵Simon Pilgrim2016-07-132-4/+37
| | | | | | | | shuffle mask Added AVX512F VPERMILPS shuffle decoding support llvm-svn: 275270
* AMDGPU/SI: Add support for R_AMDGPU_GOTPCRELTom Stellard2016-07-135-28/+69
| | | | | | | | | | Reviewers: rafael, ruiu, tony-tye, arsenm, kzhuravl Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21484 llvm-svn: 275268
* [MC] Fix lexing ordering in assembly label parsing to preserve same lineNirav Dave2016-07-131-7/+7
| | | | | | comment placement. llvm-svn: 275265
* [X86][SSE] Check for lane crossing shuffles before trying to combine to PSHUFBSimon Pilgrim2016-07-131-8/+11
| | | | | | Removes a return-on-fail that was making it tricky to add other variable mask shuffles. llvm-svn: 275262
* AMDGPU: Fold out no-op kill intrinsicsMatt Arsenault2016-07-131-0/+8
| | | | llvm-svn: 275253
* AMDGPU: WQM cleanupsMatt Arsenault2016-07-132-42/+39
| | | | | | | | - Add new TTI instruction checks - Don't use const for blocks that are mutated. - Checking isBranch and isTerminator should be redundant llvm-svn: 275252
* [ConstantFolding] Don't treat negative GEP offsets as positiveDavid Majnemer2016-07-131-4/+7
| | | | | | GEP offsets are signed, don't treat them as huge positive numbers. llvm-svn: 275251
* [BFI] Add new LazyBFI analysis passAdam Nemet2016-07-134-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This is necessary for D21771. In order to add the hotness attribute to optimization remarks we need BFI to be available in all passes that emit optimization remarks. However we don't want to pay for computing BFI unless the hotness attribute is requested. This is achieved by making BFI lazy at the very high-level through a new analysis pass -- BFI is not calculated unless requested. I am adding a test to check the laziness under D21771 where the first user of the analysis is added. Reviewers: hfinkel, dexonsmith, davidxl Subscribers: davidxl, dexonsmith, llvm-commits Differential Revision: http://reviews.llvm.org/D22141 llvm-svn: 275250
* [ConstantFolding] CleanupsDavid Majnemer2016-07-131-67/+66
| | | | | | No functional change is intended, just a minor cleanup. llvm-svn: 275249
* [IR] Make getIndexedOffsetInType return a signed resultDavid Majnemer2016-07-133-8/+8
| | | | | | | A GEPed offset can go negative, the result of getIndexedOffsetInType should according be a signed type. llvm-svn: 275246
* [ConstantFold] Don't incorrectly infer inbounds on array GEPDavid Majnemer2016-07-131-42/+59
| | | | | | | | The many levels of nesting inside the responsible code made it easy for bugs to sneak in. Flattening the logic makes it easier to see what's going on. llvm-svn: 275244
* [LoopVectorize] Further cleanupsDavid Majnemer2016-07-131-4/+2
| | | | | | No functional change is intended, just a minor cleanup. llvm-svn: 275243
* [X86] Remove some seemingly unnecessary patterns that supported vector ↵Craig Topper2016-07-132-33/+0
| | | | | | | | zext/sext with 256-bit source types producing a 256-bit result. These patterns just extracted the source down to 128-bits to use the instructions. AVX512 seems to have blindly copied them over for VLX, but did not create similar patterns for 512-bit sources. So I'm hoping the backend can't actually produce these cases. llvm-svn: 275240
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