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* [framelowering] Improve tracking of first CS pop instruction.Florian Hahn2016-12-061-5/+8
| | | | | | | | | | | | Summary: This patch makes sure FirstCSPop and MBBI never point to DBG_VALUE instructions, which affected the code generated. Reviewers: mkuper, aprantl, MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27343 llvm-svn: 288794
* Add missing parens in assert.Sam McCall2016-12-061-1/+1
| | | | | | | | | | Summary: Add missing parens in assert, which warn in GCC. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27448 llvm-svn: 288792
* [PM] Basic cleanups to CGSCC update code, NFC.Chandler Carruth2016-12-061-41/+36
| | | | | | | Just using InstIterator, simpler loop structures, and making better use of the visit callback infrastructure. llvm-svn: 288790
* [X86] Remove another weird scalar sqrt/rcp/rsqrt pattern.Craig Topper2016-12-061-6/+0
| | | | | | | | This pattern turned a vector sqrt/rcp/rsqrt operation of sse_load_f32/f64 into the the scalar instruction for the operation and put undef into the upper bits. For correctness, the resulting code should still perform the sqrt/rcp/rsqrt on the upper bits after the load is extended since that's what the operation asked for. Particularly in the case where the upper bits are 0, in that case we need calculate the sqrt/rcp/rsqrt of the zeroes and keep the result in the upper-bits. This implies we should be using the packed instruction still. The only test case for this pattern is one I just added so there was no coverage of this. llvm-svn: 288784
* [X86] Remove bad pattern that caused 128-bit loads being used by scalar ↵Craig Topper2016-12-061-3/+0
| | | | | | | | sqrt/rcp/rsqrt intrinsics to select the memory form of the corresponding instruction and violate the semantics of the intrinsic. The intrinsics are supposed to pass the upper bits straight through to their output register. This means we need to make sure we still perform the 128-bit load to get those upper bits to pass to give to the instruction since the memory form of the instruction only reads 32 or 64 bits. llvm-svn: 288781
* [X86] Correct pattern for VSQRTSSr_Int, VSQRTSDr_Int, VRCPSSr_Int, and ↵Craig Topper2016-12-061-1/+1
| | | | | | | | | | VRSQRTSSr_Int to not have an IMPLICIT_DEF on the first input. The semantics of the intrinsic are clear and not undefined. The intrinsic takes one argument, the lower bits are affected by the operation and the upper bits should be passed through. The instruction itself takes two operands, the high bits of the first operand are passed through and the low bits of the second operand are modified by the operation. To match this to the intrinsic we should pass the single intrinsic input to both operands. I had to remove the stack folding test for these instructions since they depended on the incorrect behavior. The same register is now used for both inputs so the load can't be folded. llvm-svn: 288779
* [ObjectYAML] First bit of support for encoding DWARF in MachOChris Bieneman2016-12-061-1/+16
| | | | | | This patch adds the starting support for encoding data from the MachO __DWARF segment. The first section supported is the __debug_str section because it is the simplest. llvm-svn: 288774
* [X86] Remove scalar logical op alias instructions. Just use ↵Craig Topper2016-12-064-56/+83
| | | | | | | | | | | | | | | | | | | COPY_FROM/TO_REGCLASS and the normal packed instructions instead Summary: This patch removes the scalar logical operation alias instructions. We can just use reg class copies and use the normal packed instructions instead. This removes the need for putting these instructions in the execution domain fixing tables as was done recently. I removed the loadf64_128 and loadf32_128 patterns as DAG combine creates a narrower load for (extractelt (loadv4f32)) before we ever get to isel. I plan to add similar patterns for AVX512DQ in a future commit to allow use of the larger register class when available. Reviewers: spatel, delena, zvi, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27401 llvm-svn: 288771
* [CMake] Cleanup TableGen include flagsChris Bieneman2016-12-061-0/+2
| | | | | | | | | | It is kinda crazy to have llvm/include and llvm/lib/Target in the include path for every tablegen invocation for every tablegen-like tool. This patch removes those flags from the tablgen function that is called everywhere by instead creating a variable LLVM_TABLEGEN_FLAGS which is setup in the LLVM source directories. This removes TableGen.cmake's dependency on LLVM_MAIN_SRC_DIR, and LLVM_MAIN_INCLUDE_DIR. llvm-svn: 288770
* [LVI] Remove dead code in mergeInPhilip Reames2016-12-061-18/+0
| | | | | | Integers are expressed in the lattice via constant ranges. They can never be represented by constants or not-constants; those are reserved for non-integer types. This code has been dead for literaly years. llvm-svn: 288767
* [LVI] Extract a helper functionPhilip Reames2016-12-061-32/+22
| | | | | | Extracting a helper function out of solveBlockValue makes the contract around the cache much easier to understand. llvm-svn: 288766
* [LVI] Hide the last markX function on LVILatticeValPhilip Reames2016-12-061-10/+10
| | | | | | This completes a small series of patches to hide the stateful updates of LVILatticeVal from the consuming code. The only remaining stateful API is mergeIn. llvm-svn: 288765
* [LVI] Hide a confusing internal interfacePhilip Reames2016-12-061-16/+19
| | | | llvm-svn: 288764
* [llvm] Fix D26214: Move error handling out of MC and to the callers.Mandeep Singh Grang2016-12-061-14/+5
| | | | | | | | | | | | Summary: Related clang patch; https://reviews.llvm.org/D27360 Reviewers: t.p.northover, grosbach, compnerd, echristo Subscribers: compnerd, mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D27359 llvm-svn: 288763
* [LVI] Remove duplicate code using existing helper functionPhilip Reames2016-12-061-6/+2
| | | | llvm-svn: 288761
* Revert "[SCCP] Remove manual folding of terminator instructions."Davide Italiano2016-12-061-2/+27
| | | | | | This reverts commit r288725 as it broke a bot. llvm-svn: 288759
* AMDGPU: Don't required structured CFGMatt Arsenault2016-12-061-2/+3
| | | | | | | | | | | The structured CFG is just an aid to inserting exec mask modification instructions, once that is done we don't really need it anymore. We also do not analyze blocks with terminators that modify exec, so this should only be impacting true branches. llvm-svn: 288744
* Summary: Currently there is no way to disable deprecated warning from asm ↵Weiming Zhao2016-12-051-1/+2
| | | | | | | | | | | | | | | | | | | | like this clang -target arm deprecated-asm.s -c deprecated-asm.s:30:9: warning: use of SP or PC in the list is deprecated stmia r4!, {r12-r14} We have to have an option what can disable it. Patched by Yin Ma! Reviewers: joey, echristo, weimingz Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27219 llvm-svn: 288734
* [libFuzzer] refactor the code to allow collecting features in different ↵Kostya Serebryany2016-12-053-37/+42
| | | | | | ways. Also initialize a couple of Fuzzer:: members that might have been used uninitialized :( llvm-svn: 288731
* GlobalISel: avoid looking too closely at PHIs when we bail.Tim Northover2016-12-051-9/+11
| | | | | | | | The function used to finish off PHIs by adding the relevant basic blocks can fail if we're aborting and still don't actually have the needed MachineBasicBlocks. So avoid trying in that case. llvm-svn: 288727
* [SCCP] Remove manual folding of terminator instructions.Davide Italiano2016-12-051-27/+2
| | | | | | | | | | | | | There are two cases handled here: 1) a branch on undef 2) a switch with an undef condition. Both cases are currently handled by ResolvedUndefsIn. If we have a branch on undef, we force its value to false (which is trivially foldable). If we have a switch on undef, we force to the first constant (which is also foldable). llvm-svn: 288725
* [TableGen] Centralize/Unify error handling.Davide Italiano2016-12-051-23/+21
| | | | llvm-svn: 288724
* [pdb] handle missing pdb streams more gracefullyBob Haarman2016-12-052-30/+75
| | | | | | | | | | | | Summary: The code we use to read PDBs assumed that streams we ask it to read exist, and would read memory outside a vector and crash if this wasn't the case. This would, for example, cause llvm-pdbdump to crash on PDBs generated by lld. This patch handles such cases more gracefully: the PDB reading code in LLVM now reports errors when asked to get a stream that is not present, and llvm-pdbdump will report missing streams and continue processing streams that are present. Reviewers: ruiu, zturner Subscribers: thakis, amccarth Differential Revision: https://reviews.llvm.org/D27325 llvm-svn: 288722
* GlobalISel: place constants correctly in the entry block.Tim Northover2016-12-051-1/+1
| | | | | | | | | When the entry block was empty after arg lowering, we were always placing constants at the end. This is probably hamrless while translating the same block, but horribly wrong once its terminator has been translated. So switch to inserting at the beginning. llvm-svn: 288720
* AMDGPU: Consolidate inline immediate predicate functionsMatt Arsenault2016-12-054-76/+66
| | | | llvm-svn: 288718
* GlobalISel: handle pointer arguments that get assigned to the stack.Tim Northover2016-12-051-1/+4
| | | | llvm-svn: 288717
* AMDGPU: Minor assembler refactoringMatt Arsenault2016-12-051-64/+71
| | | | | | | Fix return before else, check types for selecting fltSemantics, refactor immediate checks. llvm-svn: 288715
* GlobalISel: translate constants larger than 64 bits.Tim Northover2016-12-051-1/+1
| | | | llvm-svn: 288713
* GlobalISel: make G_CONSTANT take a ConstantInt rather than int64_t.Tim Northover2016-12-054-7/+24
| | | | | | | | This makes it more similar to the floating-point constant, and also allows for larger constants to be translated later. There's no real functional change in this patch though, just syntax updates. llvm-svn: 288712
* GlobalISel: improve translation fallback for constants.Tim Northover2016-12-051-1/+1
| | | | | | | | Returning 0 (NoReg) from getOrCreateVReg leads to unexpected situations later in the translation. It's better to return a valid (if undefined) register and let the rest of the instruction carry on as planned. llvm-svn: 288709
* GlobalISel: handle 1-element aggregates during ABI lowering.Tim Northover2016-12-051-2/+4
| | | | llvm-svn: 288706
* [LAA] Prevent invalid IR for loop-invariant bound in loop bodyKeno Fischer2016-12-051-7/+13
| | | | | | | | | | | | | | | | | | Summary: If LAA expands a bound that is loop invariant, but not hoisted out of the loop body, it used to use that value anyway, causing a non-domination error, because the memcheck block is of course not dominated by the scalar loop body. Detect this situation and expand the SCEV expression instead. Fixes PR31251 Reviewers: anemet Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D27397 llvm-svn: 288705
* [X86] Fix non-intrinsic roundss/roundsd to not read the destination registerMichael Kuperstein2016-12-052-82/+96
| | | | | | | | | | | | This changes the scalar non-intrinsic non-avx roundss/sd instruction definitions not to read their destination register - allowing partial dependency breaking. This fixes PR31143. Differential Revision: https://reviews.llvm.org/D27323 llvm-svn: 288703
* AMDGPU: Assembler support for expMatt Arsenault2016-12-053-27/+208
| | | | | | | | compr is not currently parsed (or printed) correctly, but that should probably be fixed along with intrinsic changes. llvm-svn: 288698
* AMDGPU: Change how exp is printedMatt Arsenault2016-12-055-7/+148
| | | | | | | This is an improvement over a long list of unreadable numbers. A follow up patch will try to match how sc formats these. llvm-svn: 288697
* AMDGPU: Refactor exp instructionsMatt Arsenault2016-12-0514-73/+156
| | | | | | | | | | | | | | | Structure the definitions a bit more like the other classes. The main change here is to split EXP with the done bit set to a separate opcode, so we can set mayLoad = 1 so that it won't be reordered before the other exp stores, since this has the special constraint that if the done bit is set then this should be the last exp in she shader. Previously all exp instructions were inferred to have unmodeled side effects. llvm-svn: 288695
* [AArch64][RegisterBankInfo] Fix typo in the logic used in assert.Quentin Colombet2016-12-051-1/+1
| | | | | | | Thanks to David Binderman <dcb314@hotmail.com> for bringing it to my attention. llvm-svn: 288688
* [DIExpression] Introduce a dedicated DW_OP_LLVM_fragment operationAdrian Prantl2016-12-0521-191/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | so we can stop using DW_OP_bit_piece with the wrong semantics. The entire back story can be found here: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20161114/405934.html The gist is that in LLVM we've been misinterpreting DW_OP_bit_piece's offset field to mean the offset into the source variable rather than the offset into the location at the top the DWARF expression stack. In order to be able to fix this in a subsequent patch, this patch introduces a dedicated DW_OP_LLVM_fragment operation with the semantics that we used to apply to DW_OP_bit_piece, which is what we actually need while inside of LLVM. This patch is complete with a bitcode upgrade for expressions using the old format. It does not yet fix the DWARF backend to use DW_OP_bit_piece correctly. Implementation note: We discussed several options for implementing this, including reserving a dedicated field in DIExpression for the fragment size and offset, but using an custom operator at the end of the expression works just fine and is more efficient because we then only pay for it when we need it. Differential Revision: https://reviews.llvm.org/D27361 rdar://problem/29335809 llvm-svn: 288683
* [TargetLowering] add special-case for demanded bits analysis of 'not'Sanjay Patel2016-12-051-5/+19
| | | | | | | | | | | | | | | | We treat bitwise 'not' as a special operation and try not to reduce its all-ones mask. Presumably, this is because a 'not' may be cheaper than a generic 'xor' or it may get folded into another logic op if the target has those. However, if we can remove a logic instruction by changing the xor's constant mask value, that should always be a win. Note that the IR version of SimplifyDemandedBits() does not treat 'not' as a special-case currently (although that's marked with a FIXME). So if you run this IR through -instcombine, you should get the same end result. I'm hoping to add a different backend transform that will expose this problem though, so I need to solve this first. Differential Revision: https://reviews.llvm.org/D27356 llvm-svn: 288676
* [x86] fold fand (fxor X, -1) Y --> fandn X, YSanjay Patel2016-12-051-0/+31
| | | | | | | | | | | I noticed this gap in the scalar FP-logic matching with: D26712 and: rL287171 Differential Revision: https://reviews.llvm.org/D27385 llvm-svn: 288675
* Use range based for loop. NFCI.Simon Pilgrim2016-12-051-7/+4
| | | | llvm-svn: 288671
* [PPC] Slightly Improve Assembly Parsing errors and add EOL commentNirav Dave2016-12-051-194/+119
| | | | | | | | parsing tests. NFC intended. llvm-svn: 288667
* [mips][ias] N32/N64 must not sort the relocation table.Simon Dardis2016-12-051-0/+7
| | | | | | | | | | | | Doing so changes the evaluation order for relocation composition. Patch By: Daniel Sanders Reviewers: vkalintiris, atanasyan Differential Revision: https://reviews.llvm.org/D26401 llvm-svn: 288666
* [X86][SSE] Add support for combining target shuffles to UNPCKL/UNPCKH.Simon Pilgrim2016-12-051-29/+63
| | | | llvm-svn: 288663
* [X86][SSE] Add helper function to create UNPCKL/UNPCKH shuffle masks. NFCI.Simon Pilgrim2016-12-051-27/+25
| | | | llvm-svn: 288659
* [GlobalISel] Extract handleAssignments out of AArch64CallLoweringDiana Picus2016-12-053-87/+42
| | | | | | | | | | | | This function seems target-independent so far: all the target-specific behaviour is isolated in the CCAssignFn and the ValueHandler (which we're also extracting into the generic CallLowering). The intention is to use this in the ARM backend. Differential Revision: https://reviews.llvm.org/D27045 llvm-svn: 288658
* [AMDGPU] Disassembler: fix s_buffer_store_dword instructionsSam Kolton2016-12-051-2/+11
| | | | | | | | | | | | Summary: s_buffer_store_dword instructions sdata operand was called sdst in encoding. This caused disassembler to fail. Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: arsenm, nhaehnle, rampitec Differential Revision: https://reviews.llvm.org/D27100 llvm-svn: 288657
* TableGen: Some more std::string->StringInit* replacementsMatthias Braun2016-12-053-37/+27
| | | | llvm-svn: 288653
* TableGen: TableGenStringKey is no longer necessary as of r288642Matthias Braun2016-12-051-55/+0
| | | | llvm-svn: 288651
* TableGen: Use range based for; reserve vectors where possibleMatthias Braun2016-12-051-18/+23
| | | | llvm-svn: 288650
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