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* [InstSimplify] Use cast instead of dyn_cast after isa<> check. NFCICraig Topper2017-04-101-2/+2
| | | | llvm-svn: 299870
* [MemCpyOpt] Only replace memcpy with bitcast if address spaces matchMatt Arsenault2017-04-101-0/+5
| | | | | | Patch by James Price llvm-svn: 299866
* MemorySSA: Make lifetime starts defs for mustaliased pointersDaniel Berlin2017-04-101-2/+4
| | | | | | | | | | | | | | | | | | Summary: While we don't want them aliasing with other pointers, there seems to be no point in not having them clobber must-aliased'd pointers. If some day, we split the aliasing and ordering chains, we'd make this not aliasing but an ordering barrier (IE it doesn't affect it's memory, but we can't hoist it above it). Reviewers: hfinkel, george.burgess.iv Subscribers: Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D31865 llvm-svn: 299865
* [ARM/AArch64] Ensure valid vector element types for interleaved accessesMatthew Simpson2017-04-106-39/+86
| | | | | | | | | | | This patch refactors and strengthens the type checks performed for interleaved accesses. The primary functional change is to ensure that the interleaved accesses have valid element types. The added test cases previously failed because the element type is f128. Differential Revision: https://reviews.llvm.org/D31817 llvm-svn: 299864
* [InstCombine] Use commutable matchers and m_OneUse in visitSub to shorten ↵Craig Topper2017-04-101-15/+11
| | | | | | | | code. Add missing test cases. In one case I removed commute handling for a multiply with a constant since we'll eventually get the constant on the right hand side. llvm-svn: 299863
* AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault2017-04-1010-19/+23
| | | | | | | | | | | | The unused dummy src2_modifiers is missing, so it crashes when trying to print it. I tried to fully remove src2_modifiers, but there are some irritations in the places where it is converted to mad since it starts to require modifying use lists while iterating over them. llvm-svn: 299861
* [InstCombine] Use m_c_Add to shorten some code. Add testcases for this fold ↵Craig Topper2017-04-101-2/+1
| | | | | | since they were missing. NFC llvm-svn: 299853
* [X86][MMX] Add fast-isel support for MMX non-temporal writesSimon Pilgrim2017-04-101-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D31754 llvm-svn: 299852
* [InstCombine] fix matching of or-of-icmps constants (PR32524)Sanjay Patel2017-04-101-12/+16
| | | | | | | | | | | Also, make the same change in and-of-icmps and remove a hack for detecting that case. Finally, add some FIXME comments because the code duplication here is awful. This should fix the remaining IR problem noted in: https://bugs.llvm.org/show_bug.cgi?id=32524 llvm-svn: 299851
* Improves pretty printing of variable types in llvm-pdbdumpAdrian McCarthy2017-04-103-0/+12
| | | | | | | | | | | | | | | | | * Adds support for pointers to arrays, which was missing * Adds some tests * Improves consistency of const and volatile qualifiers * Eliminates non-composable special case code for arrays and function by using a more general recursive approach * Has a hack for getting the calling convention into the right spot for pointer-to-functions Given the rapid changes happenning in llvm-pdbdump, this may be difficult to merge. Differential Revision: https://reviews.llvm.org/D31832 llvm-svn: 299848
* [InstCombine] Support folding of add instructions with vector constants into ↵Craig Topper2017-04-101-7/+2
| | | | | | | | | | select operations We currently only fold scalar add of constants into selects. This improves this to support vectors too. Differential Revision: https://reviews.llvm.org/D31683 llvm-svn: 299847
* [ARM] GlobalISel: Support G_FPOW for float and doubleDiana Picus2017-04-101-2/+3
| | | | | | Legalize to a libcall. llvm-svn: 299841
* [InstCombine] Use commutable and/or/xor matchers to simplify some codeCraig Topper2017-04-101-9/+4
| | | | | | | | | | | | | | | | | Summary: This is my first time using the commutable matchers so wanted to make sure I was doing it right. Are there any other matcher tricks to further shrink this? Can we commute the whole match so we don't have to LHS and RHS separately? Reviewers: davide, spatel Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31680 llvm-svn: 299840
* [SelectionDAG] TargetLowering::SimplifyDemandedBits how to properly ↵Craig Topper2017-04-101-1/+5
| | | | | | | | | | | | | | | | | | | | | calculate KnownZero bits for ISD::SETCC and ISD::AssertZExt Summary: For SETCC we aren't calculating the KnownZero bits at all. I've copied the code from computeKnownZero over for this. For AssertZExt we were only setting KnownZero for bits that were demanded. But the upper bits are zero whether they were demanded or not. I'm interested in fixing this because my belief is the first part of the ISD::AND handling code in SimplifyDemandedBits largely exists because of these two bugs. In that code we go to computeKnownBits for the LHS and optimize a RHS constant. Because computeKnownBits handles SETCC and AssertZExt correctly we get better information sometimes than when we call SimplifyDemandedBits on the LHS later. With these two issues fixed in SimplifyDemandedBits I was able to remove that computeKnownBits call and still pass all X86 tests. I'll submit that change in a separate patch. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31715 llvm-svn: 299839
* [InstCombine] Make sure we preserve fast math flags when folding fp ↵Craig Topper2017-04-101-2/+6
| | | | | | | | | | | | | | | | instructions into phi nodes Summary: I noticed in the select folding code that we copied fast math flags, but did not do the same for the similar handling in phi nodes. This patch fixes that to do the same thing as select Reviewers: spatel, davide, majnemer, hfinkel Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31690 llvm-svn: 299838
* [InstCombine] use m_c_And and m_c_Xor to handle commuted versions of a ↵Craig Topper2017-04-101-2/+2
| | | | | | transform. llvm-svn: 299837
* [InstCombine] Remove unnecessary dyn_cast to BinaryOperator around some ↵Craig Topper2017-04-101-31/+29
| | | | | | | | matcher checks in visitXor. The matchers themselves should be enough. llvm-svn: 299835
* [InstCombine] Make the (A|B)^B -> A & ~B transform code consistent with the ↵Craig Topper2017-04-101-5/+5
| | | | | | | | very similar (A&B)^B -> ~A & B code. This should be NFC except for the addition of hasOneUse check. I think this code is still overly complicated and should use matchers, but first I wanted to make it consistent. llvm-svn: 299834
* [InstCombine] Use m_OneUse to shorten some code. NFCCraig Topper2017-04-101-6/+3
| | | | llvm-svn: 299833
* General usability improvements to generic PDB library.Zachary Turner2017-04-1031-65/+110
| | | | | | | | | | | | | | | | | | | | 1. Added some asserts to make sure concrete symbol types don't get constructed with RawSymbols that have an incompatible SymTag enum value. 2. Added new forwarding macros that auto-define an Id/Sym method pair whenever there is a method that returns a SymIndexId. Previously we would just provide one method that returned only the SymIndexId and it was up to the caller to use the Session object to get a pointer to the symbol. Now we automatically get both the method that returns the Id, as well as a method that returns the pointer directly with just one macro. 3. Added some methods for dumping straight to stdout that can be used from inside the debugger for diagnostics during a debug session. 4. Added a clone() method and a cast<T>() method to PDBSymbol that can shorten some usage patterns. llvm-svn: 299831
* [SCCP] Resolve indirect branch target when possible.Xin Tong2017-04-101-8/+71
| | | | | | | | | | | | | | Summary: Resolve indirect branch target when possible. This potentially eliminates more basicblocks and result in better evaluation for phi and other things. Reviewers: davide, efriedma, sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30322 llvm-svn: 299830
* [InstCombine] remove dead cases from icmp pair switches; NFCISanjay Patel2017-04-091-32/+0
| | | | | | | | | | | | "PredicatesFoldable" returns false for signed/unsigned mismatched pairs, so these cases should never exist. We'll default to 'unreachable' on those predicate combos instead. Most of what's left in these switches belongs in InstSimplify (and may already be there), so there's probably more that can be done to reduce this code. llvm-svn: 299829
* [Mem2Reg] Remove AliasSetTracker updating logic from the pass.Davide Italiano2017-04-093-40/+8
| | | | | | No caller has been passing it for a long time. llvm-svn: 299827
* [MemorySSA] Fix use of pointsToConstantMemory in ↵Hal Finkel2017-04-091-1/+2
| | | | | | | | | | isUseTriviallyOptimizableToLiveOnEntry In isUseTriviallyOptimizableToLiveOnEntry, pointsToConstantMemory needs to be called on the load's pointer operand, not on the result of the load (which might not even be a pointer). llvm-svn: 299823
* [InstCombine] Extend some OR combines to support vectors.Craig Topper2017-04-091-19/+23
| | | | | | | | This adds support for these combines for vectors (X^C)|Y -> (X|Y)^C iff Y&C == 0 Y|(X^C) -> (X|Y)^C iff Y&C == 0 llvm-svn: 299822
* [InstCombine] Extend a canonicalization check to apply to vector constants too.Craig Topper2017-04-091-1/+2
| | | | llvm-svn: 299821
* [InstCombine] Use the SubOne helper function to shorten some code. NFCCraig Topper2017-04-091-7/+4
| | | | llvm-svn: 299819
* [InstCombine] rename variable for easier reading; NFCCraig Topper2017-04-091-9/+9
| | | | | | We usually give constants a 'C' somewhere in the name... llvm-svn: 299818
* MC: Remove unused virtual function MCObjectWriter::isWeak. NFC.Peter Collingbourne2017-04-083-45/+1
| | | | llvm-svn: 299817
* AMDGPU: Actually write nops for writeNopDataMatt Arsenault2017-04-081-1/+14
| | | | | | | Before this was just writing 0s, which ends up looking like a v_cndmask_b32 v0, s0, v0, vcc. Write out an encoded s_nop instead. llvm-svn: 299816
* [AsmParser]Emit an error if a macro has two (or more) parameters sharing the ↵Coby Tayree2017-04-081-0/+6
| | | | | | | | | | | | | same name Introducing a new error to macro parameters' parsing: currently, llvm-mc won't complain if a macro have two (or more) named params with the same name. this behavior is false, as there's no merit in having some params sharing a name. now, instead of tolerate such a phenomena - emit an appropriate error. Differential Revision: https://reviews.llvm.org/D31674 llvm-svn: 299815
* [IR] Inline Type::getScalarType() by using isVectorTy() and ↵Craig Topper2017-04-081-6/+0
| | | | | | | | getVectorElementType() that were already available inline. Seems to have very little compiled code size impact. But might give a tiny performance boost. llvm-svn: 299811
* [AArch64] Refine Falkor Machine Model - Part 3Balaram Makam2017-04-085-26/+135
| | | | | | | | | This concludes the refinements to Falkor Machine Model. It includes SchedPredicates for immediate zero and LSL Fast. Forwarding logic is also modeled for vector multiply and accumulate only. llvm-svn: 299810
* [coroutines] Make CoroSplit pass deterministicGor Nishanov2017-04-081-2/+0
| | | | | | | | | | | | | | | coro-split-after-phi.ll test was flaky due to non-determinism in the coroutine frame construction that was sorting the spill vector using a pointer to a def as a part of the key. The sorting was intended to make sure that spills for the same def are kept together, however, we populate the vector by processing defs in order, so the spill entires will end up together anyways. This change removes spill sorting and restores the determinism in the test. llvm-svn: 299809
* [cfi] Take over existing __cfi_check in CrossDSOCFI.Evgeniy Stepanov2017-04-071-0/+3
| | | | | | | https://reviews.llvm.org/D31796 will emit a dummy __cfi_check in the frontend. llvm-svn: 299805
* [ARM] Prefer BIC over BFC in ARM mode.Eli Friedman2017-04-071-0/+1
| | | | | | | | | | | | BIC is generally faster, and it can put the output in a different register from the input. We already do this in Thumb2 mode; not sure why the equivalent fix never got applied to ARM mode. Differential Revision: https://reviews.llvm.org/D31797 llvm-svn: 299803
* [GlobalISel]: Fix bug where we can report GISelFailure on erased instructionsAditya Nandakumar2017-04-072-38/+26
| | | | | | | | | | | | | The original instruction might get legalized and erased and expanded into intermediate instructions and the intermediate instructions might fail legalization. This end up in reporting GISelFailure on the erased instruction. Instead report GISelFailure on the intermediate instruction which failed legalization. Reviewed by: ab llvm-svn: 299802
* [ConstantFolding] Use Intrinsic::not_intrinsic instead of 0 for readability. ↵Craig Topper2017-04-071-1/+1
| | | | | | NFCI llvm-svn: 299801
* [AArch64] Allow global register asm("x18") or asm("w18") under -ffixed-x18Petr Hosek2017-04-071-0/+5
| | | | | | | | | | | | When using -ffixed-x18, the x18 (or w18) register can safely be used with the "global register variable" GCC extension, but the backend fails to recognize it. Patch by Roland McGrath. Differential Revision: https://reviews.llvm.org/D31793 llvm-svn: 299799
* NewGVN: Make CongruenceClass a real class in preparation for splittingDaniel Berlin2017-04-071-207/+259
| | | | | | NewGVN into analysis and eliminator. llvm-svn: 299792
* Revert "[SelectionDAG] Enable target specific vector scalarization of calls ↵Simon Dardis2017-04-0710-387/+80
| | | | | | | | | | | | | and returns" This reverts commit r299766. This change appears to have broken the MIPS buildbots. Reverting while I investigate. Revert "[mips] Remove usage of debug only variable (NFC)" This reverts commit r299769. Follow up commit. llvm-svn: 299788
* [AMDGPU] Unroll more to eliminate phis and conditionsStanislav Mekhanoshin2017-04-071-2/+52
| | | | | | | | | | | | | Increase threshold to unroll a loop which contains an "if" statement whose condition defined by a PHI belonging to the loop. This may help to eliminate if region and potentially even PHI itself, saving on both divergence and registers used for the PHI. Add a small bonus for each of such "if" statements. Differential Revision: https://reviews.llvm.org/D31693 llvm-svn: 299779
* Use PMADDWD to expand reduction in a loopDehao Chen2017-04-071-0/+47
| | | | | | | | | | | | | | | | | | Summary: PMADDWD can help improve 8/16 bit integer mutliply-add operation performance for cases like: for (int i = 0; i < count; i++) a += x[i] * y[i]; Reviewers: wmi, davidxl, hfinkel, RKSimon, zvi, mkuper Reviewed By: mkuper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31679 llvm-svn: 299776
* [GlobalISel] implement narrowing for G_CONSTANT.Igor Breger2017-04-072-0/+36
| | | | | | | | | | | | | | Summary: [GlobalISel] implement narrowing for G_CONSTANT. Reviewers: bogner, zvi, t.p.northover Reviewed By: t.p.northover Subscribers: llvm-commits, dberris, rovka, kristof.beyls Differential Revision: https://reviews.llvm.org/D31744 llvm-svn: 299772
* [coroutines] Insert spills of PHI instructions correctlyGor Nishanov2017-04-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Fix a bug where we were inserting a spill in between the PHIs in the beginning of the block. Consider this fragment: ``` begin: %phi1 = phi i32 [ 0, %entry ], [ 2, %alt ] %phi2 = phi i32 [ 1, %entry ], [ 3, %alt ] %sp1 = call i8 @llvm.coro.suspend(token none, i1 false) switch i8 %sp1, label %suspend [i8 0, label %resume i8 1, label %cleanup] resume: call i32 @print(i32 %phi1) ``` Unless we are spilling the argument or result of the invoke, we were always inserting the spill immediately following the instruction. The fix adds a check that if the spilled instruction is a PHI Node, select an appropriate insert point with `getFirstInsertionPt()` that skips all the PHI Nodes and EH pads. Reviewers: majnemer, rnk Reviewed By: rnk Subscribers: qcolombet, EricWF, llvm-commits Differential Revision: https://reviews.llvm.org/D31799 llvm-svn: 299771
* Reapply r298620: [LV] Vectorize GEPsMatthew Simpson2017-04-071-79/+206
| | | | | | | | | | | | | This patch reapplies r298620. The original patch was reverted because of two issues. First, the patch exposed a bug in InstCombine that caused the Chromium builds to fail (PR32414). This issue was fixed in r299017. Second, the patch introduced a bug in the vectorizer's scalars analysis that caused test suite builds to fail on SystemZ. The scalars analysis was too aggressive and marked a memory instruction scalar, even though it was going to be vectorized. This issue has been fixed in the current patch and several new test cases for the scalars analysis have been added. llvm-svn: 299770
* [mips] Remove usage of debug only variable (NFC)Simon Dardis2017-04-071-2/+2
| | | | | | | Fix the lld-x86_64-darwin13 buildbot by removing the declaration of a debug only variable and instead moving the value into the debug statement. llvm-svn: 299769
* [mips][msa] Fix generation of bm(n)zi and bins[lr]i instructionsPetar Jovanovic2017-04-072-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | We have two cases here, the first one being the following instruction selection from the builtin function: bm(n)zi builtin -> vselect node -> bins[lr]i machine instruction In case of bm(n)zi having an immediate which has either its high or low bits set, a bins[lr] instruction can be selected through the selectVSplatMask[LR] function. The function counts the number of bits set, and that value is being passed to the bins[lr]i instruction as its immediate, which in turn copies immediate modulo the size of the element in bits plus 1 as per specs, where we get the off-by-one-error. The other case is: bins[lr]i -> vselect node -> bsel.v In this case, a bsel.v instruction gets selected with a mask having one bit less set than required. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D30579 llvm-svn: 299768
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-072-36/+48
| | | | | | | | | | | | | | | | | | | | - corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
* [SelectionDAG] Enable target specific vector scalarization of calls and returnsSimon Dardis2017-04-0710-80/+387
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown, backends can request that LLVM to scalarize vector types for calls and returns. The MIPS vector ABI requires that vector arguments and returns are passed in integer registers. With SelectionDAG's new hooks, the MIPS backend can now handle LLVM-IR with vector types in calls and returns. E.g. 'call @foo(<4 x i32> %4)'. Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for calls and returns if vector types were not legal. If vector types were legal, a single 128bit vector argument would be assigned to a single 32 bit / 64 bit integer register. By teaching the MIPS backend to inspect the original types, it can now implement the MIPS vector ABI which requires a particular method of scalarizing vectors. Previously, the MIPS backend relied on clang to scalarize types such as "call @foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3, i32 inreg %4)". This patch enables the MIPS backend to take either form for vector types. Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur Differential Revision: https://reviews.llvm.org/D27845 llvm-svn: 299766
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