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* Speculative fix for build failures due to consumeInteger.Zachary Turner2016-09-221-0/+3
| | | | | | | | | | | | | | | | A recent patch added support for consumeInteger() and made getAsInteger delegate to this function. A few buildbots are failing as a result with an assertion failure. On a hunch, I tested what happens if I call getAsInteger() on an empty string, and sure enough it crashes the same way that the buildbots are crashing. I confirmed that getAsInteger() on an empty string did not crash before my patch, so I suspect this to be the cause. I also added a unit test for the empty string. llvm-svn: 282170
* GVN-hoist: fix store past load dependence analysis (PR30216)Sebastian Pop2016-09-221-29/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To hoist stores past loads, we used to search for potential conflicting loads on the hoisting path by following a MemorySSA def-def link from the store to be hoisted to the previous defining memory access, and from there we followed the def-use chains to all the uses that occur on the hoisting path. The problem is that the def-def link may point to a store that does not alias with the store to be hoisted, and so the loads that are walked may not alias with the store to be hoisted, and even as in the testcase of PR30216, the loads that may alias with the store to be hoisted are not visited. The current patch visits all loads on the path from the store to be hoisted to the hoisting position and uses the alias analysis to ask whether the store may alias the load. I was not able to use the MemorySSA functionality to ask for whether load and store are clobbered: I'm not sure which function to call, so I used a call to AA->isNoAlias(). Store past store is still working as before using a MemorySSA query: I added an extra test to pr30216.ll to make sure store past store does not regress. Differential Revision: https://reviews.llvm.org/D24517 llvm-svn: 282168
* GVN-hoist: fix typoSebastian Pop2016-09-221-1/+1
| | | | llvm-svn: 282165
* [Support] Add StringRef::consumeInteger.Zachary Turner2016-09-221-25/+55
| | | | | | | | | | | | | | | | | | | | | StringRef::getInteger() exists and treats the entire string as an integer of the specified radix, failing if any invalid characters are encountered or the number overflows. Sometimes you might have something like "123456foo" and you want to get the number 123456 and leave the string "foo" remaining. This is similar to what would be possible by using the standard runtime library functions strtoul et al and specifying an end pointer. This patch adds consumeInteger(), which does exactly that. It consumes as much as possible until an invalid character is found, and modifies the StringRef in place so that upon return only the portion of the StringRef after the number remains. Differential Revision: https://reviews.llvm.org/D24778 llvm-svn: 282164
* [compiler-rt] fix typo in option description [NFC]Etienne Bergeron2016-09-221-1/+1
| | | | llvm-svn: 282163
* GVN-hoist: only hoist relevant scalar instructionsSebastian Pop2016-09-221-0/+4
| | | | | | | | | | | | | | | | | | | Without this patch, GVN-hoist would think that a branch instruction is a scalar instruction and would try to value number it. The patch filters out all such kind of irrelevant instructions. A bit frustrating is that there is no easy way to discard all those very infrequent instructions, a bit like isa<TerminatorInst> that stands for a large family of instructions. I'm thinking that checking for those very infrequent other instructions would cost us more in compilation time than just letting those instructions getting numbered, so I'm still thinking that a simpler check: if (isa<TerminatorInst>(I)) return false; is better than listing all the other less frequent instructions. Differential Revision: https://reviews.llvm.org/D23929 llvm-svn: 282160
* Reapplying r281895 (and follow-up r281964) after fixing pr30468.Keith Walker2016-09-222-5/+53
| | | | | | | | | | | | | | | | The additional fix is: When adding debug information to a lowered phi node in mem2reg check that we have a valid insertion point after the phi for adding the debug information. This change addresses the issue in pr30468 where a lowered phi was added before a catchswitch and no debug information should be added after the phi in this case. Differential Revision: https://reviews.llvm.org/D24797 llvm-svn: 282155
* GlobalISel: handle stack-based parameters on AArch64.Tim Northover2016-09-223-73/+208
| | | | llvm-svn: 282153
* [RS4GC] Remat in presence of phi and use live valueAnna Thomas2016-09-221-8/+21
| | | | | | | | | | Summary: Reviewers: Subscribers: llvm-svn: 282150
* [AMDGPU][mc] Add support for absolute expressions in DPP modifiers.Artem Tamazov2016-09-221-35/+22
| | | | | | | | | Also added range checking for DPP attributes. Assembler tests added as well. Differential Revision: https://reviews.llvm.org/D24755 llvm-svn: 282145
* [PowerPC] Remove LE patterns matching generic stores/loads to VSX permuting opsNemanja Ivanovic2016-09-221-5/+10
| | | | | | | | | | | | | This patch corresponds to: https://reviews.llvm.org/D21409 The LXVD2X, LXVW4X, STXVD2X and STXVW4X instructions permute the two doublewords in the vector register when in little-endian mode. Custom code ensures that the necessary swaps are inserted for these. This patch simply removes the possibilty that a load/store node will match one of these instructions in the SDAG as that would not insert the necessary swaps. llvm-svn: 282144
* [Power9] Add exploitation of non-permuting memory opsNemanja Ivanovic2016-09-225-21/+68
| | | | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D19825 The new lxvx/stxvx instructions do not require the swaps to line the elements up correctly. In order to select them over the lxvd2x/lxvw4x instructions which require swaps, the patterns for the old instruction have a predicate that ensures they won't be selected on Power9 and newer CPUs. llvm-svn: 282143
* [EfficiencySanitizer] Using '$' instead of '#' for struct counter nameSagar Thakur2016-09-221-6/+6
| | | | | | | | | For MIPS '#' is the start of comment line. Therefore we get assembler errors if # is used in the structure names. Differential: D24334 Reviewed by: zhaoqin llvm-svn: 282141
* Fix revision 281960Dorit Nuzman2016-09-221-2/+4
| | | | llvm-svn: 282139
* [AVX-512] Add support for commuting VPTERNLOG instructions.Craig Topper2016-09-224-39/+171
| | | | | | | | | | VPTERNLOG is a ternary instruction with an immediate specifying the logical operation to perform. For each bit position in the 3 source vectors the bit from each source is concatenated together and the resulting 3-bit value is used to select a bit in the immediate. This bit value is written to the result vector. We can commute this by swapping operands and modifying the immediate. To modify the immediate we need to swap two pairs of bits. The pairs correspond to the locations in the immediate where the commuted operands bits have opposite values and the uncommuted operand has the same value. Bits 0 and 7 will never be swapped since the relevant bits from all sources are the same value. This refactors and reuses parts of the FMA3 commuting code which is also a three operand instruction. llvm-svn: 282132
* [RegisterBankInfo] Move to statically allocated RegisterBank.Quentin Colombet2016-09-224-4/+59
| | | | | | | | | | | | This commit is basically the first step toward what will RegisterBankInfo look when it gets TableGen'ed. It introduces a XXXGenRegisterBankInfo.def file that is what TableGen will issue at some point. Moreover, the RegBanks field in RegisterBankInfo changed to reflect the static (compile time) aspect of the information. llvm-svn: 282131
* [RegisterBankInfo] Take advantage of the extra argument of SmallVector::resize.Quentin Colombet2016-09-221-3/+1
| | | | | | | | When initializing an instance of OperandsMapper, instead of using SmallVector::resize followed by std::fill, use the function that directly does that in SmallVector. llvm-svn: 282130
* [libFuzzer] add 'features' to the corpus elements, allow mutations with Size ↵Kostya Serebryany2016-09-228-44/+66
| | | | | | > MaxSize, fix sha1 in corpus stats; various refactorings llvm-svn: 282129
* [libFuzzer] one more test Kostya Serebryany2016-09-223-0/+30
| | | | llvm-svn: 282127
* [libFuzzer] add stats to the corpus; more refactoringKostya Serebryany2016-09-2110-49/+53
| | | | llvm-svn: 282121
* [libFuzzer] more refactoring; don't compute sha1sum every time we mutate a ↵Kostya Serebryany2016-09-214-57/+53
| | | | | | unit from the corpus, use the stored one. llvm-svn: 282115
* [libFuzzer] more refactoringKostya Serebryany2016-09-2110-8/+13
| | | | llvm-svn: 282113
* Next set of additional error checks for invalid Mach-O files for bad LC_UUIDKevin Enderby2016-09-211-2/+6
| | | | | | | load commands. Added a missing check and made the check for more than one like other other “more than one” checks. And of course added test cases. llvm-svn: 282104
* [LoopInterchange] Track all dependencies, not just anti dependencies.Chad Rosier2016-09-211-50/+47
| | | | | | | | | | | | | | | | | Currently, we give up on loop interchange if we encounter a flow dependency anywhere in the loop list. Worse yet, we don't even track output dependencies. This patch updates the dependency matrix computation to track flow and output dependencies in the same way we track anti dependencies. This improves an internal workload by 2.2x. Note the loop interchange pass is off by default and it can be enabled with '-mllvm -enable-loopinterchange' Differential Revision: https://reviews.llvm.org/D24564 llvm-svn: 282101
* [ThinLTO] Emit files for distributed builds for all modulesTeresa Johnson2016-09-211-20/+20
| | | | | | | | | | | | | | | | | | | | With the new LTO API in r278338, we stopped emitting the individual index files and imports files for some modules in the distributed backend case (thinlto-index-only plugin option). Specifically, this is when the linker decides not to include a module in the link, because it was in an archive library and did not have a strong reference to it. Not creating the expected output files makes the distributed build system implementation more difficult, in terms of checking for the expected outputs of the thin link, and scheduling the backend jobs. To address this, the gold-plugin will write dummy empty .thinlto.bc and .imports files for modules not included in the link (which LTO never sees). Augmented a gold v1.12+ test, since that version of gold has the handling for notifying on modules not being included in the link. llvm-svn: 282100
* [MIRParser] Delete dead code. NFCI.Davide Italiano2016-09-211-12/+0
| | | | llvm-svn: 282098
* revert 281908 because 281909 got revertedNico Weber2016-09-211-46/+7
| | | | llvm-svn: 282097
* Disable tail calls if there is an swifterror argumentArnold Schwaighofer2016-09-211-0/+5
| | | | | | | | | ISel does not handle them correctly yet i.e we crash trying to emit tail call code. radar://28407842 llvm-svn: 282088
* [LV] Don't emit unused scalars for uniform instructionsMatthew Simpson2016-09-211-14/+58
| | | | | | | | | | | | If we identify an instruction as uniform after vectorization, we know that we should only use the value corresponding to the first vector lane of each unroll iteration. However, when scalarizing such instructions, we still produce values for the other vector lanes. This patch prevents us from generating the unused scalars. Differential Revision: https://reviews.llvm.org/D24275 llvm-svn: 282087
* [AMDGPU][mc] Add support for ds_add_[rtn_]f32.Artem Tamazov2016-09-211-0/+5
| | | | | | | | | Lit tests added. Resolves https://github.com/RadeonOpenCompute/hcc/issues/122. Differential Revision: https://reviews.llvm.org/D24765 llvm-svn: 282086
* Change the basic block weight calculation algorithm to use max instead of ↵Dehao Chen2016-09-211-14/+6
| | | | | | | | | | | | | | voting. Summary: Now that we have more precise debug info, we should change back to use maximum to get basic block weight. Reviewers: dnovillo Subscribers: andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D24788 llvm-svn: 282084
* [LV] Rename "Width" to "Lane" (NFC)Matthew Simpson2016-09-211-6/+6
| | | | llvm-svn: 282083
* Revert r281895 "Add @llvm.dbg.value entries for the phi node created by ↵Hans Wennborg2016-09-212-49/+5
| | | | | | | | | | -mem2reg" (And follow-up r281964.) It caused PR30468. llvm-svn: 282077
* Revert r281715, it caused PR30475Nico Weber2016-09-215-214/+3
| | | | llvm-svn: 282076
* DeadArgElim: Don't mark swifterror arguments as unusedArnold Schwaighofer2016-09-211-1/+1
| | | | | | | | Replacing swifterror arguments with undef creates invalid IR. rdar://28300490 llvm-svn: 282075
* [LoopInterchange] Various cleanup. NFC.Chad Rosier2016-09-211-23/+19
| | | | llvm-svn: 282071
* GlobalISel: produce correct code for signext/zeroext ABI flags.Tim Northover2016-09-216-99/+200
| | | | | | | | We still don't really have an equivalent of "AssertXExt" in DAG, so we don't exploit the guarantees on the receiving side yet, but this should produce conservatively correct code on iOS ABIs. llvm-svn: 282069
* GlobalISel: pass Function to lowerFormalArguments directly (NFC).Tim Northover2016-09-215-15/+11
| | | | | | | | The only implementation that exists immediately looks it up anyway, and the information is needed to handle various parameter attributes (stored on the function itself). llvm-svn: 282068
* [AMDGPU] Assembler: remove unused AMDGPUMCObjectWriter.Sam Kolton2016-09-211-25/+0
| | | | | | | | | | | | Summary: It is replaced by AMDGPUELFObjectWriter Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl Differential Revision: https://reviews.llvm.org/D24654 llvm-svn: 282065
* [mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mipsSimon Dardis2016-09-211-1/+3
| | | | | | | | | | | | | | | | | The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
* Revert "AArch64: Set shift bit of TLSLE HI12 add instruction"Diana Picus2016-09-211-6/+0
| | | | | | | This reverts commit r282057 because it broke the buildbots - see e.g. http://lab.llvm.org:8011/builders/clang-cmake-aarch64-42vma/builds/12063 llvm-svn: 282058
* AArch64: Set shift bit of TLSLE HI12 add instructionLei Liu2016-09-211-0/+6
| | | | | | | | | | | | Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model. This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000. Reviewers: t.p.northover, peter.smith, rovka Subscribers: salim.nasser, aemerson, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D24702 llvm-svn: 282057
* [AVX-512] Split the 3 different usages of the X86ISD::FSETCC opcode into 3 ↵Craig Topper2016-09-214-12/+19
| | | | | | | | | | | | different opcodes. It turns out isel is really not robust against having different type profiles for the same opcode. It turns out that if you put an illegal rounding mode(i.e. not CUR_DIRECTION or NO_EXC) on a comiss intrinsic we would generate the FSETCC form with the rounding mode added, but then pattern match to an instruction with ROUND_CUR_DIRECTION. We can probably get away with just one FSETCCM opcode that always contains the rounding mode and explicitly put ROUND_CUR_DIRECTION in the pattern, but I'll leave that for future work. With this change the clang tests for the comiss intrinsics that used an incorrect rounding mode of 3 properly fail isel instead of silently doing the wrong thing. Those clang tests will be fixed in a follow up commit and I also plan to add rounding mode checking to clang. llvm-svn: 282055
* [AVX-512] Don't add an additional rounding mode operand to the avx512 ↵Craig Topper2016-09-213-14/+11
| | | | | | | | | | vcvtps2ph intrinsic lowering. There was no way to control its value so it was always FROUND_CURRENT making it unnecessary. The true rounding mode is encoded in the immediate operand of the instruction. This also removes the pattern from the rb form of the instructions since there is no way to specify the FROUND_NO_EXC rounding mode it required. llvm-svn: 282052
* [AVX-512] Simplify handling of INTR_TYPE_1OP_MASK_RM to remove support for ↵Craig Topper2016-09-211-7/+1
| | | | | | | | the second opcode since its never used. This makes it consistent with INTR_TYPE_2OP_MASK_RM and INTR_TYPE_3OP_MASK_RM. And even if it was used we were passing the same operands to both so it wouldn't make sense to have two opcodes. llvm-svn: 282051
* [libFuzzer] fix libc++ buildKostya Serebryany2016-09-211-0/+1
| | | | llvm-svn: 282050
* [LV] When reporting about a specific instruction without debug location use ↵Adam Nemet2016-09-211-1/+4
| | | | | | | | loop's This can occur for example if some optimization drops the debug location. llvm-svn: 282048
* [libFuzzer] more refactoring; NFCKostya Serebryany2016-09-218-42/+74
| | | | llvm-svn: 282047
* [AVX-512] Don't lower avx512 vcvtps2ph/vcvtph2ps nodes to ↵Craig Topper2016-09-214-10/+15
| | | | | | ISD::FP16_TO_FP/ISD::FP_TO_FP16 with an extra x86 specific rounding mode operand. We should use a target specific ISD opcode. llvm-svn: 282046
* [NVPTX] Check if callsite is defined when computing argument allignmentJacques Pienaar2016-09-212-13/+20
| | | | | | | | | | | | Summary: In getArgumentAlignment check if the ImmutableCallSite pointer CS is non-null before dereferencing. If CS is 0x0 fall back to the ABI type alignment else compute the alignment as before. Reviewers: eliben, jpienaar Subscribers: jlebar, vchuravy, cfe-commits, jholewinski Differential Revision: https://reviews.llvm.org/D9168 llvm-svn: 282045
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