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* Testing for _XCR_XFEATURE_ENABLED_MASK instead of a specific MSVC version ↵Aaron Ballman2013-04-231-1/+1
| | | | | | because some MSVC 2010 SP1 installations do not have the _xgetbv intrinsic. Patch thanks to Serge Pavlov! llvm-svn: 180125
* R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune2013-04-235-16/+25
| | | | llvm-svn: 180124
* R600: Add CF_ENDVincent Lejeune2013-04-233-44/+77
| | | | llvm-svn: 180123
* LoopVectorizer: Fix 15830. When scalarizing and unrolling stores make sure ↵Nadav Rotem2013-04-231-4/+4
| | | | | | | | that the order in which the elements are scalarized is the same as the original order. This fixes a miscompilation in FreeBSD's regex library. llvm-svn: 180121
* Hexagon: Remove duplicate instructions to handle global/immediate valuesJyotsna Verma2013-04-232-321/+55
| | | | | | for absolute/absolute-set addressing modes. llvm-svn: 180120
* Call the potentially costly isAnnotatedParallel() only once. Pekka Jaaskelainen2013-04-231-3/+5
| | | | | | Made the uniform write test's checks a bit stricter. llvm-svn: 180119
* Add some constraints to use of 'returned':Stephen Lin2013-04-232-0/+8
| | | | | | | | | 1) Disallow 'returned' on parameter that is also 'sret' (no sensible semantics, as far as I can tell). 2) Conservatively disallow tail calls through 'returned' parameters that also are 'zext' or 'sext' (for consistency with treatment of other zero-extending and sign-extending operations in tail call position detection...can be revised later to handle situations that can be determined to be safe). This is a new attribute that is not yet used, so there is no impact. llvm-svn: 180118
* Wrap.h: Define wrap / unwrap function for ExecutionEngineTom Stellard2013-04-231-1/+0
| | | | llvm-svn: 180112
* Fixup for r180094: properly use MSan interface functionsAlexey Samsonov2013-04-231-2/+2
| | | | llvm-svn: 180103
* Expose IRBuilder::CreateAtomicRMW as LLVMBuildAtomicRMW in llvm-c.Carlo Kok2013-04-231-0/+36
| | | | llvm-svn: 180100
* Tell MSan that memory initialized by libz is validAlexey Samsonov2013-04-231-2/+9
| | | | llvm-svn: 180094
* Use zlib to uncompress debug sections in DWARF parser.Alexey Samsonov2013-04-232-0/+41
| | | | | | | This makes llvm-dwarfdump and llvm-symbolizer understand debug info sections compressed by ld.gold linker. llvm-svn: 180088
* Add llvm_unreachable after fully covered switch to pacify GCCHans Wennborg2013-04-231-0/+1
| | | | llvm-svn: 180087
* Add more guards around zlib-dependent codeAlexey Samsonov2013-04-231-1/+1
| | | | llvm-svn: 180084
* Add basic zlib support to LLVM. This would allow to use ↵Alexey Samsonov2013-04-232-0/+90
| | | | | | compression/uncompression in selected LLVM tools. llvm-svn: 180083
* Refuse to (even try to) vectorize loops which have uniform writes,Pekka Jaaskelainen2013-04-231-9/+9
| | | | | | | | | even if erroneously annotated with the parallel loop metadata. Fixes Bug 15794: "Loop Vectorizer: Crashes with the use of llvm.loop.parallel metadata" llvm-svn: 180081
* AArch64: remove unnecessary check that RS is validTim Northover2013-04-231-2/+3
| | | | | | | | AArch64 always demands a register-scavenger, so the pointer should never be NULL. However, in the spirit of paranoia, we'll assert it before use just in case. llvm-svn: 180080
* Struct-path aware TBAA: update getMostGenericTBAA Manman Ren2013-04-222-38/+60
| | | | | | | | | | The tag is of type TBAANode when flag EnableStructPathTBAA is off. Move implementation of MDNode::getMostGenericTBAA to TypeBasedAliasAnalysis.cpp since it depends on how to interprete the MDNodes for scalar TBAA and struct-path aware TBAA. llvm-svn: 180068
* Remove unused DwarfSectionOffsetDirective stringMatt Arsenault2013-04-224-5/+3
| | | | | | | The value isn't actually used, and setting it emits a COFF specific directive. llvm-svn: 180064
* Move C++ code out of the C headers and into either C++ headersEric Christopher2013-04-2219-0/+132
| | | | | | | or the C++ files themselves. This enables people to use just a C compiler to interoperate with LLVM. llvm-svn: 180063
* [ms-inline asm] Removed this unnecessary check. In the current implementation,Chad Rosier2013-04-221-1/+1
| | | | | | Disp will always be one of MCSymbolRefExpr or MCConstantExpr, and never NULL. llvm-svn: 180059
* [ms-inline asm] Get the OpDecl and remove a redundant lookup.Chad Rosier2013-04-221-2/+1
| | | | | | Part of rdar://13663589 llvm-svn: 180057
* [ms-inline asm] Add the OpDecl to the InlineAsmIdentifierInfo struct and in turnChad Rosier2013-04-221-13/+18
| | | | | | | the MCParsedAsmOperand. Part of rdar://13663589 llvm-svn: 180054
* Optimize MachineBasicBlock::getSymbol by caching the symbol. Since the symbolEli Bendersky2013-04-221-7/+11
| | | | | | | name computation is expensive, this helps save about 25% of the time spent in this function. llvm-svn: 180049
* Changed back (relative to commit 179786) the operations executed when ↵Anat Shemer2013-04-221-3/+3
| | | | | | extract(cast) is transformed to cast(extract). It uses the Builder class as before. In addition the result node is added to the Worklist, so all the previous extract users will become the new scalar cast users. llvm-svn: 180045
* Fix unused variable warning.Chad Rosier2013-04-221-1/+1
| | | | llvm-svn: 180044
* 80 columns.Akira Hatanaka2013-04-223-6/+9
| | | | llvm-svn: 180040
* [mips] In performDSPShiftCombine, check that all elements in the vector areAkira Hatanaka2013-04-222-10/+12
| | | | | | | shifted by the same amount and the shift amount is smaller than the element size. llvm-svn: 180039
* [ms-inline asm] Remove the identifier parsing logic from the AsmParser. This isChad Rosier2013-04-221-61/+55
| | | | | | | | now taken care of by the frontend, which allows us to parse arbitrary C/C++ variables. Part of rdar://13663589 llvm-svn: 180037
* [Support] Fix argv string escape bug on WindowsReid Kleckner2013-04-221-4/+42
| | | | | | | | | | | | | | | | Summary: This is http://llvm.org/PR15802. Backslashes preceding double quotes in arguments must be escaped. The interesting bit is that all other backslashes should *not* be escaped, because the un-escaping logic is only triggered by the presence of a double quote character. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D705 llvm-svn: 180035
* COFF: Fix weak external aliases.Peter Collingbourne2013-04-221-28/+29
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D700 llvm-svn: 180034
* Fix for PR 14965: Better error message for GEP with partially defined contentsEli Bendersky2013-04-221-2/+7
| | | | llvm-svn: 180030
* [ms-inline asm] Refactor/clean up the SemaLookup interface. No functionalChad Rosier2013-04-222-39/+25
| | | | | | | change indended. Part of rdar://13663589 llvm-svn: 180028
* Also verify llvm.compiler_used.Rafael Espindola2013-04-221-1/+2
| | | | llvm-svn: 180020
* Clarify that llvm.used can contain aliases.Rafael Espindola2013-04-226-17/+33
| | | | | | | Also add a check for llvm.used in the verifier and simplify clients now that they can assume they have a ConstantArray. llvm-svn: 180019
* No really, don't store anything to this since it's unconditionallyEric Christopher2013-04-221-1/+1
| | | | | | set below. llvm-svn: 180015
* Remove variable store that is never read.Eric Christopher2013-04-221-1/+1
| | | | llvm-svn: 180014
* Remove variable store that is never read.Eric Christopher2013-04-221-1/+0
| | | | llvm-svn: 180013
* Fix for 5.5 Parameter Passing --> Stage C:Stepan Dyatkovskiy2013-04-223-2/+8
| | | | | | | | | | | | | | | -- C.4 and C.5 statements, when NSAA is not equal to SP. -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a variadic procedure. Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are some exceptions in AAPCS. 1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs. 2. Check that for VA functions all params uses GPRs and then stack. No exceptions, no CPRCs here. llvm-svn: 180011
* Tidy.Eric Christopher2013-04-221-4/+6
| | | | llvm-svn: 180000
* Update comment. Whitespace.Eric Christopher2013-04-221-2/+2
| | | | llvm-svn: 179999
* Revert "Revert "PR14606: debug info imported_module support""David Blaikie2013-04-224-6/+73
| | | | | | | | | | This reverts commit r179840 with a fix to test/DebugInfo/two-cus-from-same-file.ll I'm not sure why that test only failed on ARM & MIPS and not X86 Linux, even though the debug info was clearly invalid on all of them, but this ought to fix it. llvm-svn: 179996
* Convert windows line endings to linux/unix line endings.Craig Topper2013-04-221-13/+13
| | | | llvm-svn: 179995
* Fix indentation. No functional change.Craig Topper2013-04-221-5/+5
| | | | llvm-svn: 179994
* Put 'else' on same line as preceding curly brace per coding standards. No ↵Craig Topper2013-04-221-12/+6
| | | | | | functional change. llvm-svn: 179993
* Remove an unreachable 'break' following a 'return'.Craig Topper2013-04-221-1/+0
| | | | llvm-svn: 179991
* Legalize vector truncates by parts rather than just splitting.Jim Grosbach2013-04-213-4/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than just splitting the input type and hoping for the best, apply a bit more cleverness. Just splitting the types until the source is legal often leads to an illegal result time, which is then widened and a scalarization step is introduced which leads to truly horrible code generation. With the loop vectorizer, these sorts of operations are much more common, and so it's worth extra effort to do them well. Add a legalization hook for the operands of a TRUNCATE node, which will be encountered after the result type has been legalized, but if the operand type is still illegal. If simple splitting of both types ends up with the result type of each half still being legal, just do that (v16i16 -> v16i8 on ARM, for example). If, however, that would result in an illegal result type (v8i32 -> v8i8 on ARM, for example), we can get more clever with power-two vectors. Specifically, split the input type, but also widen the result element size, then concatenate the halves and truncate again. For example on ARM, To perform a "%res = v8i8 trunc v8i32 %in" we transform to: %inlo = v4i32 extract_subvector %in, 0 %inhi = v4i32 extract_subvector %in, 4 %lo16 = v4i16 trunc v4i32 %inlo %hi16 = v4i16 trunc v4i32 %inhi %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16 %res = v8i8 trunc v8i16 %in16 This allows instruction selection to generate three VMOVN instructions instead of a sequences of moves, stores and loads. Update the ARMTargetTransformInfo to take this improved legalization into account. Consider the simplified IR: define <16 x i8> @test1(<16 x i32>* %ap) { %a = load <16 x i32>* %ap %tmp = trunc <16 x i32> %a to <16 x i8> ret <16 x i8> %tmp } define <8 x i8> @test2(<8 x i32>* %ap) { %a = load <8 x i32>* %ap %tmp = trunc <8 x i32> %a to <8 x i8> ret <8 x i8> %tmp } Previously, we would generate the truly hideous: .syntax unified .section __TEXT,__text,regular,pure_instructions .globl _test1 .align 2 _test1: @ @test1 @ BB#0: push {r7} mov r7, sp sub sp, sp, #20 bic sp, sp, #7 add r1, r0, #48 add r2, r0, #32 vld1.64 {d24, d25}, [r0:128] vld1.64 {d16, d17}, [r1:128] vld1.64 {d18, d19}, [r2:128] add r1, r0, #16 vmovn.i32 d22, q8 vld1.64 {d16, d17}, [r1:128] vmovn.i32 d20, q9 vmovn.i32 d18, q12 vmov.u16 r0, d22[3] strb r0, [sp, #15] vmov.u16 r0, d22[2] strb r0, [sp, #14] vmov.u16 r0, d22[1] strb r0, [sp, #13] vmov.u16 r0, d22[0] vmovn.i32 d16, q8 strb r0, [sp, #12] vmov.u16 r0, d20[3] strb r0, [sp, #11] vmov.u16 r0, d20[2] strb r0, [sp, #10] vmov.u16 r0, d20[1] strb r0, [sp, #9] vmov.u16 r0, d20[0] strb r0, [sp, #8] vmov.u16 r0, d18[3] strb r0, [sp, #3] vmov.u16 r0, d18[2] strb r0, [sp, #2] vmov.u16 r0, d18[1] strb r0, [sp, #1] vmov.u16 r0, d18[0] strb r0, [sp] vmov.u16 r0, d16[3] strb r0, [sp, #7] vmov.u16 r0, d16[2] strb r0, [sp, #6] vmov.u16 r0, d16[1] strb r0, [sp, #5] vmov.u16 r0, d16[0] strb r0, [sp, #4] vldmia sp, {d16, d17} vmov r0, r1, d16 vmov r2, r3, d17 mov sp, r7 pop {r7} bx lr .globl _test2 .align 2 _test2: @ @test2 @ BB#0: push {r7} mov r7, sp sub sp, sp, #12 bic sp, sp, #7 vld1.64 {d16, d17}, [r0:128] add r0, r0, #16 vld1.64 {d20, d21}, [r0:128] vmovn.i32 d18, q8 vmov.u16 r0, d18[3] vmovn.i32 d16, q10 strb r0, [sp, #3] vmov.u16 r0, d18[2] strb r0, [sp, #2] vmov.u16 r0, d18[1] strb r0, [sp, #1] vmov.u16 r0, d18[0] strb r0, [sp] vmov.u16 r0, d16[3] strb r0, [sp, #7] vmov.u16 r0, d16[2] strb r0, [sp, #6] vmov.u16 r0, d16[1] strb r0, [sp, #5] vmov.u16 r0, d16[0] strb r0, [sp, #4] ldm sp, {r0, r1} mov sp, r7 pop {r7} bx lr Now, however, we generate the much more straightforward: .syntax unified .section __TEXT,__text,regular,pure_instructions .globl _test1 .align 2 _test1: @ @test1 @ BB#0: add r1, r0, #48 add r2, r0, #32 vld1.64 {d20, d21}, [r0:128] vld1.64 {d16, d17}, [r1:128] add r1, r0, #16 vld1.64 {d18, d19}, [r2:128] vld1.64 {d22, d23}, [r1:128] vmovn.i32 d17, q8 vmovn.i32 d16, q9 vmovn.i32 d18, q10 vmovn.i32 d19, q11 vmovn.i16 d17, q8 vmovn.i16 d16, q9 vmov r0, r1, d16 vmov r2, r3, d17 bx lr .globl _test2 .align 2 _test2: @ @test2 @ BB#0: vld1.64 {d16, d17}, [r0:128] add r0, r0, #16 vld1.64 {d18, d19}, [r0:128] vmovn.i32 d16, q8 vmovn.i32 d17, q9 vmovn.i16 d16, q8 vmov r0, r1, d16 bx lr llvm-svn: 179989
* Passing arguments to varags functions under the SPARC v9 ABI.Jakob Stoklund Olesen2013-04-211-0/+47
| | | | | | | Arguments after the fixed arguments never use the floating point registers. llvm-svn: 179987
* Tidy up comment grammar.Jim Grosbach2013-04-211-2/+2
| | | | llvm-svn: 179986
* Fix the SETHIimm pattern for 64-bit code.Jakob Stoklund Olesen2013-04-211-2/+1
| | | | | | Don't ignore the high 32 bits of the immediate. llvm-svn: 179985
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