summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [PartiallyInlineLibCalls] Add DebugCounter supportGeorge Burgess IV2018-09-131-0/+6
| | | | | | | | | | | This adds DebugCounter support to the PartiallyInlineLibCalls pass, which should make debugging/automated bisection easier in the future. Patch by Zhizhou Yang! Differential Revision: https://reviews.llvm.org/D50093 llvm-svn: 342172
* [DCE] Add DebugCounter supportGeorge Burgess IV2018-09-131-0/+8
| | | | | | | | Patch by Zhizhou Yang! Differential Revision: https://reviews.llvm.org/D50092 llvm-svn: 342170
* [InstCombine] Fold (xor (min/max X, Y), -1) -> (max/min ~X, ~Y) when X and Y ↵Craig Topper2018-09-132-0/+13
| | | | | | | | | | | | | | are freely invertible. This allows the xor to be removed completely. This might help with recomitting r341674, but seems good regardless. Coincidentally fixes PR38915. Differential Revision: https://reviews.llvm.org/D51964 llvm-svn: 342163
* Common infrastructure for reading a profile remapping file and buildingRichard Smith2018-09-132-0/+82
| | | | | | | | a mangling remapper from it. Differential Revision: https://reviews.llvm.org/D51246 llvm-svn: 342161
* [RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand typesAna Pazos2018-09-131-14/+4
| | | | | | | | | | | | | | | | | | | | Summary: Fixed assertions due to invalid fixup when encoding compressed instructions (c.addi, c.addiw, c.li, c.andi) with bare symbols with/without modifiers. This matches GAS behavior as well. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D52005 llvm-svn: 342160
* [RISCV] Fix decoding of invalid instruction with C extension enabled.Ana Pazos2018-09-132-2/+20
| | | | | | | | | | | | | | | | | | | | | | Summary: The illegal instruction 0x00 0x00 is being wrongly decoded as c.addi4spn with 0 immediate. The invalid instruction 0x01 0x61 is being wrongly decoded as c.addi16sp with 0 immediate. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51815 llvm-svn: 342159
* [WebAssembly] Fix signature of `main` in FixFunctionBitcastsSam Clegg2018-09-131-2/+4
| | | | | | | | | Also, add a check to ensure that when main has the expected signature we do not create a wrapper. Differential Revision: https://reviews.llvm.org/D51562 llvm-svn: 342157
* [InstCombine] remove checks for IsFreeToInvert()Sanjay Patel2018-09-131-3/+1
| | | | | | | | | I accidentally committed this diff with rL342147 because I had applied D51964. We probably do need those checks, but D51964 has tests and more discussion/motivation, so they should be re-added with that patch. llvm-svn: 342149
* [InstCombine] reorder folds to reduce chance of infinite loopsSanjay Patel2018-09-131-22/+20
| | | | | | | | | | | | | | | | I don't have a test case for this, but it's motivated by the discussion in D51964, and I've added TODO comments for the better fix - move simplifications into instsimplify because that's more efficient and reduces risk of infinite loops in instcombine caused by transforms trying to do the opposite folds. In this case, we know that the transform that tries to move 'not' through min/max can be fooled by the multiple uses of a value in another min/max, so try to squash the foldSPFofSPF() patterns first. llvm-svn: 342147
* [ARM] Allow truncs as sources in ARM CGPSam Parker2018-09-131-19/+23
| | | | | | | | | | We previously only allowed truncs as sinks, but now allow them as sources too. We do this by checking that the result type is the narrow type that we're trying to optimise for. Differential Revision: https://reviews.llvm.org/D51978 llvm-svn: 342141
* [ARM] Fix FixConst for ARMCodeGenPrepareSam Parker2018-09-131-20/+3
| | | | | | | | | | Part of FixConsts wrongly assumes either a 8- or 16-bit constant which can result in the wrong constants being generated during promotion. Differential Revision: https://reviews.llvm.org/D52032 llvm-svn: 342140
* [MC/Dwarf] Unclamp DWARF linetables format on Darwin.Jonas Devlieghere2018-09-131-7/+1
| | | | | | | | | | | In r319995, we fixed the line table format to version 2 on Darwin because dsymutil didn't yet understand the new format which caused test failures for the LLDB bots. This has been resolved in the meantime so there's no reason to keep this limitation. rdar://problem/35968332 llvm-svn: 342136
* AMDGPU: Fix not preserving alignent in call setupsMatt Arsenault2018-09-131-1/+7
| | | | | | | | | | | | If an argument was passed on the stack, this was using the default alignment. I'm not sure there's an observable change from this. This was observable due to bugs in expansion of unaligned loads and stores, but since that is fixed I don't think this matters much. llvm-svn: 342133
* DAG: Fix expansion of unaligned FP loads and storesMatt Arsenault2018-09-131-4/+6
| | | | | | | | | This was trying to scalarizing a scalar FP type, resulting in an assert. Fixes unaligned f64 stack stores for AMDGPU. llvm-svn: 342132
* Fix unused variable warning. NFCI.Simon Pilgrim2018-09-131-1/+1
| | | | llvm-svn: 342128
* ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4.Tim Northover2018-09-135-1/+24
| | | | | | | | | | | | The Technical Reference Manuals for these two CPUs state that branching to an unaligned 32-bit instruction incurs an extra pipeline reload penalty. That's bad. This also enables the optimization at -Os since it costs on average one byte per loop in return for 1 cycle per iteration, which is pretty good going. llvm-svn: 342127
* [XRay] Bug fixes for FDR custom event and arg-loggingDean Michael Berris2018-09-132-21/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change has a number of fixes for FDR mode in compiler-rt along with changes to the tooling handling the traces in llvm. In the runtime, we do the following: - Advance the "last record" pointer appropriately when writing the custom event data in the log. - Add XRAY_NEVER_INSTRUMENT in the rewinding routine. - When collecting the argument of functions appropriately marked, we should not attempt to rewind them (and reset the counts of functions that can be re-wound). In the tooling, we do the following: - Remove the state logic in BlockIndexer and instead rely on the presence/absence of records to indicate blocks. - Move the verifier into a loop associated with each block. Reviewers: mboerger, eizan Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D51965 llvm-svn: 342122
* [AMDGPU] Load divergence predicate refactoringAlexander Timofeev2018-09-132-8/+26
| | | | | | | | Differential revision: https://reviews.llvm.org/D51931 Reviewers: rampitec llvm-svn: 342120
* [mips] Enable the mnemonic spell correctorSimon Atanasyan2018-09-131-1/+7
| | | | | | | | | | | | This implements suggesting alternative mnemonics when an invalid one is specified. For example `addru $9, $6, 17767` leads to the following error message: error: unknown instruction, did you mean: add, addiu, addu, maddu? Differential revision: https://reviews.llvm.org/D40646 llvm-svn: 342119
* [AMDGPU] Preliminary patch for divergence driven instruction selection. ↵Alexander Timofeev2018-09-131-0/+1
| | | | | | | | | | Load offset inlining pattern changed. Differential revision: https://reviews.llvm.org/D51975 Reviewers: rampitec llvm-svn: 342115
* [X86] Type legalize v2i32 div/rem by scalarizing rather than promotingCraig Topper2018-09-131-0/+17
| | | | | | | | | | | | | | | | | | | | | Summary: Previously we type legalized v2i32 div/rem by promoting to v2i64. But we don't support div/rem of vectors so op legalization would then scalarize it using i64 scalar ops since it doesn't know about the original promotion. 64-bit scalar divides on Intel hardware are known to be slow and in 32-bit mode they require a libcall. This patch switches type legalization to do the scalarizing itself using i32. It looks like the division by power of 2 optimization is still kicking in and leaving the code as a vector. The division by other constant optimization doesn't kick in pre type legalization since it ignores illegal types. And previously, after type legalization we scalarized the v2i64 since we don't have v2i64 MULHS/MULHU support. Another option might be to widen v2i32 to v4i32 so we could do division by constant optimizations, but we'd have to be careful to only do that for constant divisors or we risk scalaring to 4 scalar divides. Reviewers: RKSimon, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51325 llvm-svn: 342114
* ARM: correct the relocation type for `bl` on WoASaleem Abdulrasool2018-09-131-1/+1
| | | | | | | | | | The `IMAGE_REL_ARM_BRANCH20T` applies only to a `b.w` instruction. A thumb-2 `bl` should be relocated using a `IMAGE_REL_ARM_BRANCH24T`. Correct the relocation that we emit in such a case. Resolves PR38620! Based on the patch by Jordan Rhee! llvm-svn: 342109
* Remove isAsCheapAsAMove from v128.constThomas Lively2018-09-131-1/+1
| | | | llvm-svn: 342106
* Remove isAsCheapAsAMove from mem opsThomas Lively2018-09-131-2/+2
| | | | llvm-svn: 342105
* [WebAssembly] Add missing SIMD instruction attributesThomas Lively2018-09-131-2/+3
| | | | | | | | | | | | | | Summary: These attributes are copied from equivalent instructions in WebAssemblyInstrInfo.td. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51518 llvm-svn: 342104
* DebugInfo/PDB: Remove unused memberDavid Blaikie2018-09-131-2/+2
| | | | llvm-svn: 342101
* dwarfdump: Improve performance on large DWP filesDavid Blaikie2018-09-121-8/+21
| | | | llvm-svn: 342099
* [DAGCombiner] improve formatting for select+setcc code; NFCSanjay Patel2018-09-121-17/+15
| | | | llvm-svn: 342095
* fix 80-column violation with clang-formatAdrian Prantl2018-09-121-7/+4
| | | | llvm-svn: 342094
* [PDB] Remove all clone() methods.Zachary Turner2018-09-1218-98/+0
| | | | | | | These are dead code and encourage poor usage patterns, so I'm removing them. They weren't called anywhere anyway. llvm-svn: 342093
* [Hexagon] Use shuffles when lowering "gather" shufflevectorsKrzysztof Parzyszek2018-09-121-0/+70
| | | | | | | | Shufflevector instructions in LLVM IR that extract a subset of elements of a longer input into a shorter vector can be done using VECTOR_SHUFFLEs. This will avoid expanding them into constly extracts and inserts. llvm-svn: 342091
* [Hexagon] Improve the selection algorithm in scalarizeShuffleKrzysztof Parzyszek2018-09-121-22/+89
| | | | | | Use topological ordering for newly generated nodes. llvm-svn: 342090
* [Support] sys::fs::directory_entry includes the file_type.Kristina Brooks2018-09-123-77/+95
| | | | | | | | | | | | | | | | This is available on most platforms (Linux/Mac/Win/BSD) with no extra syscalls. On other platforms (e.g. Solaris) we stat() if this information is requested. This will allow switching clang's VFS to efficiently expose (path, type) when traversing a directory. Currently it exposes an entire Status, but does so by calling fs::status() on all platforms. Almost all callers only need the path, and all callers only need (path, type). Patch by sammccall (Sam McCall) Differential Revision: https://reviews.llvm.org/D51918 llvm-svn: 342089
* [ORC] Merge ExecutionSessionBase with ExecutionSession by moving a couple ofLang Hames2018-09-122-365/+385
| | | | | | | | | | template methods in JITDylib out-of-line. This also splits JITDylib::define into a pair of template methods, one taking an lvalue reference and the other an rvalue reference. This simplifies the templates at the cost of a small amount of code duplication. llvm-svn: 342087
* [ORC] Add a special 'main' JITDylib that is created on ExecutionSessionLang Hames2018-09-121-1/+14
| | | | | | | | | | | | | | | | | | | | | construction, a new convenience lookup method, and add-to layer methods. ExecutionSession now creates a special 'main' JITDylib upon construction. All subsequently created JITDylibs are added to the main JITDylib's search order by default (controlled by the AddToMainDylibSearchOrder parameter to ExecutionSession::createDylib). The main JITDylib's search order will be used in the future to properly handle cross-JITDylib weak symbols, with the first definition in this search order selected. This commit also adds a new ExecutionSession::lookup convenience method that performs a blocking lookup using the main JITDylib's search order, as this will be a very common operation for clients. Finally, new convenience overloads of IRLayer and ObjectLayer's add methods are introduced that add the given program representations to the main dylib, which is likely to be the common case. llvm-svn: 342086
* [WebAssembly] Make tied inline asm operands work againHeejin Ahn2018-09-121-0/+5
| | | | | | | | | | | | | | | | | Summary: rL341389 broke code with tied register operands in inline assembly. For example, `asm("" : "=r"(var) : "0"(var));` The code above specifies the input operand to be in the same register with the output operand, tying the two register. This patch makes this kind of code work again. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, eraman, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51991 llvm-svn: 342084
* revert r341288 - [Reassociate] swap binop operands to increase factoring ↵Sanjay Patel2018-09-121-64/+0
| | | | | | | | potential This causes or exposes indeterminism that is visible in the output of -reassociate. llvm-svn: 342083
* [PDB] Emit old fpo data to the PDB file.Zachary Turner2018-09-121-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | r342003 added support for emitting FPO data from the DEBUG_S_FRAMEDATA subsection of the .debug$S section to the PDB file. However, that is not the end of the story. FPO can end up in two different destinations in a PDB, each corresponding to a different FPO data source. The case handled by r342003 involves copying data from the DEBUG_S_FRAMEDATA subsection of the .debug$S section to the "New FPO" stream in the PDB, which is then referred to by the DBI stream. The case handled by this patch involves copying records from the .debug$F section of an object file to the "FPO" stream (or perhaps more aptly, the "Old FPO" stream) in the PDB file, which is also referred to by the DBI stream. The formats are largely similar, and the difference is mostly only visible in masm generated object files, such as some of the low-level CRT object files like memcpy. MASM doesn't appear to support writing the DEBUG_S_FRAMEDATA subsection, and instead just writes these records to the .debug$F section. Although clang-cl does not emit a .debug$F section ever, lld still needs to support it so we have good debugging for CRT functions. Differential Revision: https://reviews.llvm.org/D51958 llvm-svn: 342080
* [Hexagon] Use legalized type for extracted elements in scalarizeShuffleKrzysztof Parzyszek2018-09-121-2/+4
| | | | | | | | | Scalarization of a shuffle will break up the source vectors into individual elements, and use them to assemble the resulting vector. An element type of a legal vector type may not necessarily be a legal scalar type, so make sure that the extracted values are extended to a legal scalar type. llvm-svn: 342079
* AMDGPU: Print all kernel descriptor directives (including the ones with ↵Konstantin Zhuravlyov2018-09-121-101/+88
| | | | | | | | | | default values) Change by Tony Tye Differential Revision: https://reviews.llvm.org/D51954 llvm-svn: 342077
* AMDGPU: Re-apply r341982 after fixing the layering issueKonstantin Zhuravlyov2018-09-1212-401/+404
| | | | | | | | | | | | Move isa version determination into TargetParser. Also switch away from target features to CPU string when determining isa version. This fixes an issue when we output wrong isa version in the object code when features of a particular CPU are altered (i.e. gfx902 w/o xnack used to result in gfx900). llvm-svn: 342069
* [InstCombine] Inefficient pattern for high-bits checking (PR38708)Roman Lebedev2018-09-121-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: It is sometimes important to check that some newly-computed value is non-negative and only `n` bits wide (where `n` is a variable.) There are **many** ways to check that: https://godbolt.org/z/o4RB8D The last variant seems best? (I'm sure there are some other variations i haven't thought of..) Let's handle the second variant first, since it is much simpler. https://rise4fun.com/Alive/LYjY https://bugs.llvm.org/show_bug.cgi?id=38708 Reviewers: spatel, craig.topper, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51985 llvm-svn: 342067
* [WebAssembly] SIMD comparisonsThomas Lively2018-09-122-1/+55
| | | | | | | | | | | | | | | | Summary: Match the ordering semantics of non-vector comparisons. For floating point comparisons that do not correspond to instructions, the tests check that some vector comparison instruction was emitted but do not care about the full implementation. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51765 llvm-svn: 342064
* [ARM] Tighten f64<->f16 conversion requirementsDiogo N. Sampaio2018-09-121-4/+8
| | | | | | | | | | | | | | Fix missing Requires fields. Patch by Bernard Ogden (bogden) Reviewers: SjoerdMeijer, javed.absar, t.p.northover Reviewed By: t.p.northover Differential Revision: https://reviews.llvm.org/D51631 llvm-svn: 342061
* [X86] Remove isel patterns for ADCX instructionCraig Topper2018-09-121-30/+7
| | | | | | | | | | | | There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
* Reverting r342048, which caused UBSan failures in dsymutil.Wolfgang Pieb2018-09-127-201/+221
| | | | llvm-svn: 342056
* [GVNHoist] computeInsertionPoints() miscalculates IDFAlexandros Lamprineas2018-09-121-4/+2
| | | | | | | | | | | | | | Fix for https://bugs.llvm.org/show_bug.cgi?id=38912. In GVNHoist::computeInsertionPoints() we iterate over the Value Numbers and calculate the Iterated Dominance Frontiers without clearing the IDFBlocks vector first. IDFBlocks ends up accumulating an insane number of basic blocks, which bloats the compilation time of SemaChecking.cpp with ubsan enabled. Differential Revision: https://reviews.llvm.org/D51980 llvm-svn: 342055
* [AArch64] Implement aarch64_vector_pcs codegen support.Sander de Smalen2018-09-123-41/+92
| | | | | | | | | | | | | | This patch adds codegen support for the saving/restoring V8-V23 for functions specified with the aarch64_vector_pcs calling convention attribute, as added in patch D51477. Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar, MatzeB Reviewed By: thegameg Differential Revision: https://reviews.llvm.org/D51479 llvm-svn: 342049
* [DWARF] Refactoring range list dumping to fold DWARF v4 functionality into ↵Wolfgang Pieb2018-09-127-221/+201
| | | | | | | | | | | | | v5 handling Eliminating some duplication of rangelist dumping code at the expense of some version-dependent code in dump and extract routines. Reviewer: dblaikie, JDevlieghere, vleschuk Differential revision: https://reviews.llvm.org/D51081 llvm-svn: 342048
* [CGP] Ensure splitgep gives deterministic outputDavid Green2018-09-121-1/+1
| | | | | | | | | | | | | | The output of splitLargeGEPOffsets does not appear to be deterministic because of the way that we iterate over a DenseMap. I've changed it to a MapVector for consistent output. The test here isn't particularly great, only showing a consmetic difference in output. The original reproducer is much larger but show a diffierence in instruction ordering, leading to different codegen. Differential Revision: https://reviews.llvm.org/D51851 llvm-svn: 342043
OpenPOWER on IntegriCloud