summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [ARM] Follow-up to rL342033Sam Parker2018-09-121-1/+1
| | | | | | Fixed typo which can cause segfault. llvm-svn: 342040
* [SimplifyCFG] Put an alignment on generated switch tablesDavid Green2018-09-121-0/+3
| | | | | | | | | | Previously the alignment on the newly created switch table data was not set, meaning that DataLayout::getPreferredAlignment was free to overalign it to 16 bytes. This causes unnecessary code bloat. Differential Revision: https://reviews.llvm.org/D51800 llvm-svn: 342039
* [AArch64] NFC: Refactoring to prepare for vector PCS.Sander de Smalen2018-09-121-39/+74
| | | | | | | | | | | | | | This patch refactors several parts of AArch64FrameLowering so that it can be easily extended to support saving/restoring of FPR128 (Q) registers. Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar Reviewed By: thegameg Differential Revision: https://reviews.llvm.org/D51478 llvm-svn: 342038
* [ARM] Exchange MAC operands in ARMParallelDSPSam Parker2018-09-121-115/+154
| | | | | | | | | | | | | | | | SMLAD and SMLALD instructions also come in the form of SMLADX and SMLALDX which perform an exchange on their second operand. To support this, more of the loads in the MAC candidates are compared for sequential access and a boolean value has been added to BinOpChain. AddMACCandiate has been refactored into a small pattern matching state machine to reduce the amount of duplicated code, but also to enable the matching to be more flexible. CreateParallelMACPairs now iterates through all the candidates to find parallel ones. Differential Revision: https://reviews.llvm.org/D51424 llvm-svn: 342033
* [ARM] Allow bitcasts in ARMCodeGenPrepareSam Parker2018-09-121-5/+4
| | | | | | | | Allow bitcasts in the use-def chains, treating them as sources. Differential Revision: https://reviews.llvm.org/D50758 llvm-svn: 342032
* [AArch64] Add parsing of aarch64_vector_pcs attribute.Sander de Smalen2018-09-126-0/+13
| | | | | | | | | | | | | | | | | | | This patch adds parsing support for the 'aarch64_vector_pcs' calling convention attribute to calls and function declarations. More information describing the vector ABI and procedure call standard can be found here: https://developer.arm.com/products/software-development-tools/\ hpc/arm-compiler-for-hpc/vector-function-abi Reviewers: t.p.northover, rnk, rengolin, javed.absar, thegameg, SjoerdMeijer Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D51477 llvm-svn: 342030
* [LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC)Florian Hahn2018-09-122-694/+338
| | | | | | | | | | | | | Move the 2 classes out of LoopVectorize.cpp to make it easier to re-use them for VPlan outside LoopVectorize.cpp Reviewers: Ayal, mssimpso, rengolin, dcaballe, mkuper, hsaito, hfinkel, xbolva00 Reviewed By: rengolin, xbolva00 Differential Revision: https://reviews.llvm.org/D49488 llvm-svn: 342027
* Remove unused include from IVDescriptors.cpp.Ilya Biryukov2018-09-121-1/+0
| | | | | | | | | This fixes a layering violation: Analysis/IVDescrtors.cpp can't include Transforms/Utils/BasicBlockUtils.h, since TransformUtils depends on Analysis. llvm-svn: 342024
* Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into ↵Ilya Biryukov2018-09-1212-402/+401
| | | | | | | | | | | TargetParser." This reverts commit r341982. The change introduced a layering violation. Reverting to unbreak our integrate. llvm-svn: 342023
* [SelectionDAG] Remove some code from PromoteIntOp_MGATHER that handles ↵Craig Topper2018-09-121-8/+1
| | | | | | | | UpdateNodeOperands returning an existing node instead of updating. I suspect this became unecessary when the CSE of mgather was fixed in r338080. It may still be possible to hit this if we widen the element type of a gather outside of type legalization and the promote the mask of a separate gather node so they become the same. But that seems pretty unlikely. llvm-svn: 342022
* Break LoopUtils into an Analysis file.Vikram TV2018-09-123-988/+1032
| | | | | | | | | | | | | | | | | | | Summary: The InductionDescriptor and RecurrenceDescriptor classes basically analyze the IR to identify the respective IVs. So, it is better to have them in the "Analysis" directory instead of the "Transforms" directory. The rationale for this is to make the Induction and Recurrence descriptor classes available for analysis passes. Currently including them in an analysis pass produces link error (http://lists.llvm.org/pipermail/llvm-dev/2018-July/124456.html). Induction and Recurrence descriptors are moved from Transforms/Utils/LoopUtils.h|cpp to Analysis/IVDescriptors.h|cpp. Reviewers: dmgreen, llvm-commits, hfinkel Reviewed By: dmgreen Subscribers: mgorny Differential Revision: https://reviews.llvm.org/D51153 llvm-svn: 342016
* [X86] Teach X86SelectionDAGInfo::EmitTargetCodeForMemcpy about GNUX32Craig Topper2018-09-122-24/+36
| | | | | | | | | | | | | | | | | Summary: In GNUX23, is64BitMode returns true, but pointers are 32-bits. So we shouldn't copy pointer values into RSI/RDI since the widths don't match. Fixes PR38865 despite what the title says. I think the llvm_unreachable in the copyPhysReg code tricked the optimizer and made the fatal error trigger. Reviewers: rnk, efriedma, MatzeB, echristo Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51893 llvm-svn: 342015
* [MachineOutliner] Add codegen size remarks to the MachineOutlinerJessica Paquette2018-09-111-1/+103
| | | | | | | | | | | | | | | | Since the outliner is a module pass, it doesn't get codegen size remarks like the other codegen passes do. This adds size remarks *to* the outliner. This is kind of a workaround, so it's peppered with FIXMEs; size remarks really ought to not ever be handled by the pass itself. However, since the outliner is the only "MachineModulePass", this works for now. Since the entire purpose of the MachineOutliner is to produce code size savings, it really ought to be included in codgen size remarks. If we ever go ahead and make a MachineModulePass (say, something similar to MachineFunctionPass), then all of this ought to be moved there. llvm-svn: 342009
* [InstCombine] add folds for unsigned-overflow comparesSanjay Patel2018-09-111-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Name: op_ugt_sum %a = add i8 %x, %y %r = icmp ugt i8 %x, %a => %notx = xor i8 %x, -1 %r = icmp ugt i8 %y, %notx Name: sum_ult_op %a = add i8 %x, %y %r = icmp ult i8 %a, %x => %notx = xor i8 %x, -1 %r = icmp ugt i8 %y, %notx https://rise4fun.com/Alive/ZRxI AFAICT, this doesn't interfere with any add-saturation patterns because those have >1 use for the 'add'. But this should be better for IR analysis and codegen in the basic cases. This is another fold inspired by PR14613: https://bugs.llvm.org/show_bug.cgi?id=14613 llvm-svn: 342004
* [PDB] Write FPO Data to the PDB.Zachary Turner2018-09-113-11/+54
| | | | llvm-svn: 342003
* [cmake] Speed up check-llvm 5x by delay loading shell32 and ole32Reid Kleckner2018-09-111-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, check-llvm on my Windows 10 workstation took about 300s to run, and it would lock up my mouse. Now, it takes just under 60s. Previously running the tests only used about 15% of the available CPU time, now it uses up to 60%. Shell32.dll and ole32.dll have direct dependencies on user32.dll and gdi32.dll. These DLLs are mostly used to for Windows GUI functionality, which most LLVM tools don't need. It seems that these DLLs acquire and release some system resources on startup and exit, and that requires acquiring the same highly contended lock discussed in this post: https://randomascii.wordpress.com/2017/07/09/24-core-cpu-and-i-cant-move-my-mouse/ Most LLVM tools still have a transitive dependency on SHGetKnownFolderPathW, which is used to look up the user home directory and local AppData directory. We also use SHFileOperationW to recursively delete a directory, but only LLDB and clang-doc use this today. At some point, we might consider removing these last shell32.dll deps, but for now, I would like to take this free performance. Many thanks to Bruce Dawson for suggesting this fix. He looked at an ETW trace of an LLVM test run, noticed these DLLs, and suggested avoiding them. Reviewers: zturner, pcc, thakis Subscribers: mgorny, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D51952 llvm-svn: 342002
* Revert "[GVNHoist] Re-enable GVNHoist by default"Alexandros Lamprineas2018-09-112-4/+4
| | | | | | | | | | | | | | This reverts rL341954. The builder `sanitizer-x86_64-linux-bootstrap-ubsan` has been failing with timeouts at stage2 clang/ubsan: [3065/3073] Linking CXX executable bin/lld command timed out: 1200 seconds without output running python ../sanitizer_buildbot/sanitizers/buildbot_selector.py, attempting to kill llvm-svn: 342001
* [codeview] Decode and dump FP regs from S_FRAMEPROC recordsReid Kleckner2018-09-112-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There are two registers encoded in the S_FRAMEPROC flags: one for locals and one for parameters. The encoding is described by the ExpandEncodedBasePointerReg function in cvinfo.h. Two bits are used to indicate one of four possible values: 0: no register - Used when there are no variables. 1: SP / standard - Variables are stored relative to the standard SP for the ISA. 2: FP - Variables are addressed relative to the ISA frame pointer, i.e. EBP on x86. If realignment is required, parameters use this. If a dynamic alloca is used, locals will be EBP relative. 3: Alternative - Variables are stored relative to some alternative third callee-saved register. This is required to address highly aligned locals when there are dynamic stack adjustments. In this case, both the incoming SP saved in the standard FP and the current SP are at some dynamic offset from the locals. LLVM uses ESI in this case, MSVC uses EBX. Most of the changes in this patch are to pass around the CPU so that we can decode these into real, named architectural registers. Subscribers: hiraditya Differential Revision: https://reviews.llvm.org/D51894 llvm-svn: 341999
* [object] Improve the performance of getSymbols used by ArchiveWriterAlexander Shaposhnikov2018-09-111-11/+23
| | | | | | | | | | | | In this diff we adjust the code of getSymbols to avoid creating LLVMContext when it's not necessary. Without this patch when the function getSymbols was called on a MachO object with a __bitcode section it was parsing the embedded bitcode and then ignoring the result. Test plan: make check-all Differential revision: https://reviews.llvm.org/D51759 llvm-svn: 341998
* [InstCombine] add folds for icmp with xor mask constantSanjay Patel2018-09-111-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are the folds in Alive; Name: xor_ult Pre: isPowerOf2(-C1) %xor = xor i8 %x, C1 %r = icmp ult i8 %xor, C1 => %r = icmp ugt i8 %x, ~C1 Name: xor_ugt Pre: isPowerOf2(C1+1) %xor = xor i8 %x, C1 %r = icmp ugt i8 %xor, C1 => %r = icmp ugt i8 %x, C1 https://rise4fun.com/Alive/Vty The ugt case in its simplest form was already handled by DemandedBits, but that's not ideal as shown in the multi-use test. I'm not sure if these are all of the symmetrical folds, but I adjusted the existing code for one of the folds to try to show the similarities. There's no obvious connection, but this is another preliminary step for PR14613... https://bugs.llvm.org/show_bug.cgi?id=14613 llvm-svn: 341997
* add IR flags to MIMichael Berg2018-09-115-1/+28
| | | | | | | | | | | | | | Summary: Initial support for nsw, nuw and exact flags in MI Reviewers: spatel, hfinkel, wristow Reviewed By: spatel Subscribers: nlopes Differential Revision: https://reviews.llvm.org/D51738 llvm-svn: 341996
* Revert "[SanitizerCoverage] Create comdat for global arrays."Matt Morehouse2018-09-111-26/+14
| | | | | | | This reverts r341987 since it will cause trouble when there's a module ID collision. llvm-svn: 341995
* [Support] Quote arguments containing \n on WindowsReid Kleckner2018-09-111-1/+1
| | | | | | | | | Fixes at_file.c test failure caused by r341988. We may want to change how we treat \n in our tokenizer, but this is probably a good fix regardless, since we can invoke all kinds of programs with different interpretations of the command line quoting rules. llvm-svn: 341992
* [Support] Avoid calling CommandLineToArgvW from shell32.dllReid Kleckner2018-09-111-55/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Shell32.dll depends on gdi32.dll and user32.dll, which are mostly DLLs for Windows GUI functionality. LLVM's utilities don't typically need GUI functionality, and loading these DLLs seems to be slowing down startup. Also, we already have an implementation of Windows command line tokenization in cl::TokenizeWindowsCommandLine, so we can just use it. The goal is to get the original argv in UTF-8, so that it can pass through most LLVM string APIs. A Windows process starts life with a UTF-16 string for its command line, and it can be retreived with GetCommandLineW from kernel32.dll. Previously, we would: 1. Get the wide command line 2. Call CommandLineToArgvW to handle quoting rules and separate it into arguments. 3. For each wide argument, expand wildcards (* and ?) using FindFirstFileW. 4. Convert each argument to UTF-8 Now we: 1. Get the wide command line, convert the whole thing to UTF-8 2. Tokenize the UTF-8 command line with cl::TokenizeWindowsCommandLine 3. For each argument, expand wildcards if present - This requires converting back to UTF-16 to call FindFirstFileW - Results of FindFirstFileW must be converted back to UTF-8 Reviewers: zturner Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51941 llvm-svn: 341988
* [SanitizerCoverage] Create comdat for global arrays.Matt Morehouse2018-09-111-14/+26
| | | | | | | | | | | | | | | | | Summary: Place global arrays in comdat sections with their associated functions. This makes sure they are stripped along with the functions they reference, even on the BFD linker. Reviewers: eugenis Reviewed By: eugenis Subscribers: eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51902 llvm-svn: 341987
* Update MemorySSA in LoopUnswitch.Alina Sbirlea2018-09-111-10/+60
| | | | | | | | | | | | Summary: Update MemorySSA in old LoopUnswitch pass. Actual dependency and update is disabled by default. Subscribers: sanjoy, jlebar, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D45301 llvm-svn: 341984
* AMDGPU: Move isa version and EF_AMDGPU_MACH_* determinationKonstantin Zhuravlyov2018-09-1112-401/+402
| | | | | | | | | | | | | | into TargetParser. Also switch away from target features to CPU string when determining isa version. This fixes an issue when we output wrong isa version in the object code when features of a particular CPU are altered (i.e. gfx902 w/o xnack used to result in gfx900). Differential Revision: https://reviews.llvm.org/D51890 llvm-svn: 341982
* [InstCombine] enhance vector demanded elements to look at a vector select ↵Sanjay Patel2018-09-111-2/+21
| | | | | | | | | | | | | | | condition operand I noticed that we were not back-propagating undef lanes to shuffle masks when we have a shuffle that reduces the vector width. This is part of investigating/solving PR38691: https://bugs.llvm.org/show_bug.cgi?id=38691 The DAG equivalent was proposed with: D51696 Differential Revision: https://reviews.llvm.org/D51433 llvm-svn: 341981
* [gcov] Fix branch counters with switch statements (fix PR38821)Vedant Kumar2018-09-111-196/+40
| | | | | | | | | | | | | | | | | | | | | | | | Right now, the counters are added in regards of the number of successors for a given BasicBlock: it's good when we've only 1 or 2 successors (at least with BranchInstr). But in the case of a switch statement, the BasicBlock after switch has several predecessors and we need know from which BB we're coming from. So the idea is to revert what we're doing: add a PHINode in each block which will select the counter according to the incoming BB. They're several pros for doing that: - we fix the "switch" bug - we remove the function call to "__llvm_gcov_indirect_counter_increment" and the lookup table stuff - we replace by PHINodes, so the optimizer will probably makes a better job. Patch by calixte! Differential Revision: https://reviews.llvm.org/D51619 llvm-svn: 341977
* Add some context to fatal verifier errorsXin Tong2018-09-111-2/+3
| | | | | | | | | | | | | | | | Summary: Add function name when verification fails as an initial breadcrumb for debugging. Patch by David Callahan. Reviewers: mehdi_amini, modocache Reviewed By: modocache Subscribers: llvm-commits, modocache Differential Revision: https://reviews.llvm.org/D51386 llvm-svn: 341974
* [X86] Prefer unpckhpd over movhlps in isel for fake unary casesCraig Topper2018-09-111-13/+0
| | | | | | | | | | | | In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order. This patch removes the hack. This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage. Differential Revision: https://reviews.llvm.org/D49499 llvm-svn: 341973
* [X86] Teach X86FastISel::X86SelectRet to use EAX for the sret pointer in GNUX32Craig Topper2018-09-111-1/+1
| | | | | | | | | | GNUX32 uses 32-bit pointers despite is64BitMode being true. So we should use EAX to return the value. Fixes ones of the failures from PR38865. Differential Revision: https://reviews.llvm.org/D51940 llvm-svn: 341972
* [InstCombine] Fix incorrect usage of getPrimitiveSizeInBits when we should ↵Craig Topper2018-09-111-2/+1
| | | | | | | | | | be using the element size for vectors For vectors, getPrimitiveSizeInBits returns the full vector width. This code should using the element size for vectors. This could be fixed by calling getScalarSizeInBits, but its even easier to just get it from the APInt we're checking. Differential Revision: https://reviews.llvm.org/D51938 llvm-svn: 341971
* [CallSiteSplitting] Add debug location to created PHI nodes.Florian Hahn2018-09-111-1/+4
| | | | | | | | | | | | | | | | | | | | | | There are 2 cases when we create PHI nodes: * For the result of the call that was duplicated in the split blocks. Those PHI nodes should have the debug location of the call. * For values produced before the call. Those instructions need to be duplicated in the split blocks and the PHI nodes should have the debug locations of those instructions. Fixes PR37962. Reviewers: junbuml, gbedwell, vsk Reviewed By: junbuml Tags: #debug-info Differential Revision: https://reviews.llvm.org/D51919 llvm-svn: 341970
* [GlobalISel] Lower dbg.declare into indirect DBG_VALUEJosh Stone2018-09-111-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: D31439 changed the semantics of dbg.declare to take the address of a variable as the first argument, making it indirect. It specifically updated FastISel for this change here: https://reviews.llvm.org/D31439#change-WVArzi177jPl GlobalISel needs to follow suit, or else it will be missing a level of indirection in the generated debuginfo. This problem was seen in a Rust debuginfo test on aarch64, since GlobalISel is used at -O0 for aarch64. https://github.com/rust-lang/rust/issues/49807 https://bugzilla.redhat.com/show_bug.cgi?id=1611597 https://bugzilla.redhat.com/show_bug.cgi?id=1625768 Reviewers: dblaikie, aprantl, t.p.northover, javed.absar, rnk Reviewed By: rnk Subscribers: #debug-info, rovka, kristof.beyls, JDevlieghere, llvm-commits, tstellar Differential Revision: https://reviews.llvm.org/D51749 llvm-svn: 341969
* Test commit: remove trailing whitespaceJosh Stone2018-09-111-1/+1
| | | | llvm-svn: 341966
* Revert "[SanitizerCoverage] Create comdat for global arrays."Matt Morehouse2018-09-111-31/+14
| | | | | | This reverts r341951 due to bot breakage. llvm-svn: 341965
* [InstCombine] Use dyn_cast instead of match(m_Constant). NFCCraig Topper2018-09-111-4/+2
| | | | llvm-svn: 341962
* [InstCombine] Support (mul (sext x), cst) --> (sext (mul x, cst')) and (mul ↵Craig Topper2018-09-111-2/+2
| | | | | | | | | | (zext x), cst) --> (zext (mul x, cst')) for vectors constants. Similar to D51236, but for mul instead of add. Differential Revision: https://reviews.llvm.org/D51900 llvm-svn: 341961
* [MachineOutliner][NFC] Factor out instruction mapping into its own functionJessica Paquette2018-09-111-28/+38
| | | | | | | Just some tidy-up. Pull the mapper stuff into `populateMapper`. This makes it a bit easier to read what's going on in `runOnModule`. llvm-svn: 341959
* [X86] Correct the one use check from r341915.Craig Topper2018-09-111-1/+1
| | | | | | The one use check should be on the bitcast, not the input to the bitcast. llvm-svn: 341956
* [GVNHoist] Re-enable GVNHoist by defaultAlexandros Lamprineas2018-09-112-4/+4
| | | | | | | Rebase rL340922 since https://bugs.llvm.org/show_bug.cgi?id=38807 has been fixed by rL341947. llvm-svn: 341954
* [MIPS] Fix illegal type assert in single-float modeSimon Atanasyan2018-09-111-3/+8
| | | | | | | | | | | | An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in single-float mode. This would trigger an "Unexpected illegal type!" assert. Patch by Dan Ravensloft. Differential revision: https://reviews.llvm.org/D51810 llvm-svn: 341952
* [SanitizerCoverage] Create comdat for global arrays.Matt Morehouse2018-09-111-14/+31
| | | | | | | | | | | | | | | | | Summary: Place global arrays in comdat sections with their associated functions. This makes sure they are stripped along with the functions they reference, even on the BFD linker. Reviewers: eugenis Reviewed By: eugenis Subscribers: eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51902 llvm-svn: 341951
* [MemorySSAUpdater] Avoid creating self-referencing MemoryDefsAlexandros Lamprineas2018-09-111-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for https://bugs.llvm.org/show_bug.cgi?id=38807, which occurred while compiling SemaTemplateInstantiate.cpp with clang and GVNHoist enabled. In the following example: 1=def(entry) / \ 2=def(1) 4=def(1) 3=def(2) 5=def(4) When removing the MemoryDef 2=def(1) from its basic block, and just before adding it to the end of the parent basic block, we first replace all its uses with the defining memory access: 3=def(2) -> 3=def(1) Then we call insertDef for adding 2=def(1) to the parent basic block, where we replace the uses of 1=def(entry) with 2=def(1). Doing so we create a self reference: 2=def(1) -> 2=def(2) (bad) 3=def(1) -> 3=def(2) (ok) 4=def(1) -> 4=def(2) (ok) Differential Revision: https://reviews.llvm.org/D51801 llvm-svn: 341947
* pdb output: Initialize padding in PublicsStreamHeader.Nico Weber2018-09-111-2/+3
| | | | | | | | | Makes the produced pdbs more deterministic; before they'd contain 2 arbitary bytes where this padding was. Also reorder initialization to match the order of the fields in the struct (nfc) llvm-svn: 341945
* [ARM] Add smlald support in ARMParallelDSPSam Parker2018-09-111-13/+41
| | | | | | | | | Search from i64 reducing phis, as well as i32, to allow the generation of smlald instructions. Differential Revision: https://reviews.llvm.org/D51101 llvm-svn: 341941
* [MIPS] ORC JIT supportPetar Jovanovic2018-09-113-2/+491
| | | | | | | | | | | | This patch adds support for ORC JIT for mips/mips64 architecture. In common code $static is changed to __ORCstatic because on MIPS architecture "$" is a reserved character. Patch by Luka Ercegovcevic Differential Revision: https://reviews.llvm.org/D49665 llvm-svn: 341934
* [ARM] Enable ARMCodeGenPrepare by defaultSam Parker2018-09-111-1/+1
| | | | | | | | | We've had the pass enabled downstream for a couple of weeks and it seems to be okay, so enable it by default. Differential Revision: https://reviews.llvm.org/D51920 llvm-svn: 341932
* [AMDGPU] Preliminary patch for divergence driven instruction selection. ↵Alexander Timofeev2018-09-114-21/+62
| | | | | | | | | Immediate selection predicate changed Differential revision: https://reviews.llvm.org/D51734 Reviewers: rampitec llvm-svn: 341928
OpenPOWER on IntegriCloud