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* Change some StringRef::data() reinterpret_cast to bytes_begin() or ↵Fangrui Song2019-04-076-14/+9
| | | | | | arrayRefFromStringRef() llvm-svn: 357852
* [X86] When converting (x << C1) AND C2 to (x AND (C2>>C1)) << C1 during ↵Craig Topper2019-04-061-6/+13
| | | | | | isel, try using andl over andq by favoring 32-bit unsigned immediates. llvm-svn: 357848
* [X86] combineBitcastvxi1 - provide dst VT and src SDValue directly. NFCI.Simon Pilgrim2019-04-061-19/+17
| | | | | | Prep work to make it easier to reuse the BITCAST->MOVSMK combine in other cases. llvm-svn: 357847
* [X86] Use a signed mask in foldMaskedShiftToScaledMask to enable a shorter ↵Craig Topper2019-04-061-2/+6
| | | | | | | | | | | immediate encoding. This function reorders AND and SHL to enable the SHL to fold into an LEA. The upper bits of the AND will be shifted out by the SHL so it doesn't matter what mask value we use for these bits. By using sign bits from the original mask in these upper bits we might enable a shorter immediate encoding to be used. llvm-svn: 357846
* Fix spelling mistake. NFCI.Simon Pilgrim2019-04-061-1/+1
| | | | llvm-svn: 357843
* [AMDGPU] Sort out and rename multiple CI/VI predicatesStanislav Mekhanoshin2019-04-0614-85/+82
| | | | | | Differential Revision: https://reviews.llvm.org/D60346 llvm-svn: 357835
* [DWARF] Simplify DWARFDebugAranges::findAddressFangrui Song2019-04-061-15/+6
| | | | | | | | The current lower_bound approach has to check two iterators pos and pos-1. Changing it to upper_bound allows us to check one iterator (similar to DWARFUnitVector::getUnitFor*). llvm-svn: 357834
* [Symbolize] Uniquify sorted vector<pair<SymbolDesc, StringRef>>Fangrui Song2019-04-062-10/+16
| | | | llvm-svn: 357833
* [LLVM-C] Begin to Expose A More General Binary InterfaceRobert Widmann2019-04-051-0/+28
| | | | | | | | | | | | | | | | | | | | | Summary: Provides a new type, `LLVMBinaryRef`, and a binding to `llvm::object::createBinary` for more general interoperation with binary files than `LLVMObjectFileRef`. It also provides the proper non-consuming API for input buffers and populates an out parameter for error handling if necessary - two things the previous API did not do. In a follow-up, I'll define section and symbol iterators and begin to build upon the existing test infrastructure. This patch is a first step towards deprecating that API and replacing it with something more robust. Reviewers: deadalnix, whitequark Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60322 llvm-svn: 357822
* [LLVM-C] Add bindings to insert basic blocksRobert Widmann2019-04-051-0/+14
| | | | | | | | | | | | | | | | | | | | Summary: Now that we can create standalone basic blocks, it's useful to be able to append them. Add bindings to - Insert a basic block after the current insertion block - Append a basic block to the end of a function's list of basic blocks Reviewers: whitequark, deadalnix, harlanhaskins Reviewed By: whitequark, harlanhaskins Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59658 llvm-svn: 357812
* [X86] Enable tail calls for CallingConv::SwiftFrancis Visoiu Mistrih2019-04-051-0/+2
| | | | | | It's currently only enabled on AArch64 (enabled in r281376). llvm-svn: 357809
* [X86] Preserve operand flag when expanding TCRETURNriFrancis Visoiu Mistrih2019-04-053-2/+11
| | | | | | | | | The expansion of TCRETURNri(64) would not keep operand flags like undef/renamable/etc. which can result in machine verifier issues. Also add plumbing to be able to use `-run-pass=x86-pseudo`. llvm-svn: 357808
* [AMDGPU] Add MachineDCE pass after RenameIndependentSubregsStanislav Mekhanoshin2019-04-052-2/+37
| | | | | | | | | | | | | | Detect dead lanes can create some dead defs. Then RenameIndependentSubregs will break a REG_SEQUENCE which may use these dead defs. At this point a dead instruction can be removed but we do not run a DCE anymore. MachineDCE was only running before live variable analysis. The patch adds a mean to preserve LiveIntervals and SlotIndexes in case it works past this. Differential Revision: https://reviews.llvm.org/D59626 llvm-svn: 357805
* [X86] Merge the different Jcc instructions for each condition code into ↵Craig Topper2019-04-0521-232/+177
| | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
* [X86] Merge the different SETcc instructions for each condition code into ↵Craig Topper2019-04-0520-256/+290
| | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
* [X86] Merge the different CMOV instructions for each condition code into ↵Craig Topper2019-04-0531-422/+460
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an immediate. Summary: Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models. This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between CMOV instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. This does complicate the scheduler models a little since we can't assign the A and BE instructions to a separate class now. I plan to make similar changes for SETcc and Jcc. Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet Reviewed By: RKSimon Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60041 llvm-svn: 357800
* [LCG] Add aliased functions as LCG rootsGuozhi Wei2019-04-051-0/+13
| | | | | | | | | Current LCG doesn't check aliased functions. So if an internal function has a public alias it will not be added to CG SCC, but it is still reachable from outside through the alias. So this patch adds aliased functions to SCC. Differential Revision: https://reviews.llvm.org/D59898 llvm-svn: 357795
* [AMDGPU] predicate and feature refactoringStanislav Mekhanoshin2019-04-0518-196/+245
| | | | | | | | | We have done some predicate and feature refactoring lately but did not upstream it. This is to sync. Differential revision: https://reviews.llvm.org/D60292 llvm-svn: 357791
* Change some dyn_cast to more apropriate isa. NFCFangrui Song2019-04-0510-13/+13
| | | | llvm-svn: 357773
* [SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCCSimon Pilgrim2019-04-051-3/+8
| | | | | | | | | | Second half of PR40800, this patch adds DAG undef handling to fcmp instructions to match the behavior in llvm::ConstantFoldCompareInstruction, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.). This involves a lot of tweaking to reduced tests as bugpoint loves to reduce fcmp arguments to undef........ Differential Revision: https://reviews.llvm.org/D60006 llvm-svn: 357765
* GlobalISel: Add another overload of buildUnmergeMatt Arsenault2019-04-051-0/+9
| | | | | | | It's annoying to have to create an array of the result type, particularly when you don't care about the size of the value. llvm-svn: 357763
* AMDGPU/GlobalISel: Fix non-power-of-2 selectMatt Arsenault2019-04-051-0/+1
| | | | llvm-svn: 357762
* [DAGCombiner][x86] scalarize splatted vector FP opsSanjay Patel2019-04-052-2/+25
| | | | | | | | | | | | | | | There are a variety of vector patterns that may be profitably reduced to a scalar op when scalar ops are performed using a subset (typically, the first lane) of the vector register file. For x86, this is true for float/double ops and element 0 because insert/extract is just a sub-register rename. Other targets should likely enable the hook in a similar way. Differential Revision: https://reviews.llvm.org/D60150 llvm-svn: 357760
* [Symbolize] Replace map<SymbolDesc, StringRef> with sorted vectorFangrui Song2019-04-052-10/+19
| | | | llvm-svn: 357758
* Fix r357749 for big-endian architecturesPavel Labath2019-04-051-2/+6
| | | | | | | | | | | | | We need to read the strings from the minidump files as little-endian, regardless of the host byte order. I definitely remember thinking about this case while writing the patch (and in fact, I have implemented that for the "write" case), but somehow I have ended up not implementing the byte swapping when reading the data. This adds the necessary byte-swapping and should hopefully fix test failures on big-endian bots. llvm-svn: 357754
* Fix MSVC build for r357749Pavel Labath2019-04-051-5/+5
| | | | | | | | MSVC found the bare "make_unique" invocation ambiguous (between std:: and llvm:: versions). Explicitly qualifying the call with llvm:: should hopefully fix it. llvm-svn: 357750
* Minidump: Add support for reading/writing stringsPavel Labath2019-04-052-5/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Strings in minidump files are stored as a 32-bit length field, giving the length of the string in *bytes*, which is followed by the appropriate number of UTF16 code units. The string is also supposed to be null-terminated, and the null-terminator is not a part of the length field. This patch: - adds support for reading these strings out of the minidump file (this implementation does not depend on proper null-termination) - adds support for writing them to a minidump file - using the previous two pieces implements proper (de)serialization of the CSDVersion field of the SystemInfo stream. Previously, this was only read/written as hex, and no attempt was made to access the referenced string -- now this string is read and written correctly. The changes are tested via yaml2obj|obj2yaml round-trip as well as a unit test which checks the corner cases of the string deserialization logic. Reviewers: jhenderson, zturner, clayborg Subscribers: llvm-commits, aprantl, markmentovai, amccarth, lldb-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59775 llvm-svn: 357749
* [SelectionDAG] Compute known bits of CopyFromRegPiotr Sobczak2019-04-052-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Teach SelectionDAG how to compute known bits of ISD::CopyFromReg if the virtual reg used has one def only. This can be particularly useful when calling isBaseWithConstantOffset() with the ISD::CopyFromReg argument, as more optimizations may get enabled in the result. Also add a missing truncation on X86, found by testing of this patch. Change-Id: Id1c9fceec862d118c54a5b53adf72ada5d6daefa Reviewers: bogner, craig.topper, RKSimon Reviewed By: RKSimon Subscribers: lebedev.ri, nemanjai, jvesely, nhaehnle, javed.absar, jsji, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59535 llvm-svn: 357745
* [X86] Promote i16 SRA instructions to i32Craig Topper2019-04-051-0/+2
| | | | | | | | | | | | We already promote SRL and SHL to i32. This will introduce sign extends sometimes which might be harder to deal with than the zero we use for promoting SRL. I ran this through some of our internal benchmark lists and didn't see any major regressions. I think there might be some DAG combine improvement opportunities in the test changes here. Differential Revision: https://reviews.llvm.org/D60278 llvm-svn: 357743
* [FastISel] Fix crash for gc.relocate lowringSerguei Katkov2019-04-051-1/+6
| | | | | | | | | | | | | | Lowering safepoint checks that all gc.relocaes observed in safepoint must be lowered. However Fast-Isel is able to skip dead gc.relocate. To resolve this issue we just ignore dead gc.relocate in the check. Reviewers: reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D60184 llvm-svn: 357742
* NFC: Move API uses of MD5::MD5Result to Optional rather than a pointer.Eric Christopher2019-04-048-30/+32
| | | | | | Differential Revision: https://reviews.llvm.org/D60290 llvm-svn: 357736
* An unreachable block may have a route to a reachable block, don't fast-path ↵Nick Lewycky2019-04-041-2/+2
| | | | | | | | | | return that it can't. A block reachable from the entry block can't have any route to a block that's not reachable from the entry block (if it did, that route would make it reachable from the entry block). That is the intended performance optimization for isPotentiallyReachable. For the case where we ask whether an unreachable from entry block has a route to a reachable from entry block, we can't conclude one way or the other. Fix a bug where we claimed there could be no such route. The fix in rL357425 ironically reintroduced the very bug it was fixing but only when a DominatorTree is provided. This fixes the remaining bug. llvm-svn: 357734
* [TextAPI] Prefix all architecture enums to fix the build on i386.Juergen Ributzka2019-04-043-11/+11
| | | | | | | | | | | | | | | | | Summary: This changes the Architecture enum to use a prefix (AK_) to prevent the preprocessor from replacing i386 with 1 when building llvm/clang for i386. Reviewers: steven_wu, lhames, mstorsjo Reviewed By: mstorsjo Subscribers: hiraditya, jkorous, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60241 llvm-svn: 357733
* [IR] Refactor attribute methods in Function class (NFC)Evandro Menezes2019-04-0467-123/+123
| | | | | | | | Rename the functions that query the optimization kind attributes. Differential revision: https://reviews.llvm.org/D60287 llvm-svn: 357731
* Revert [X86] When using Win64 ABI, exit with error if SSE is disabled for ↵James Y Knight2019-04-041-3/+0
| | | | | | | | | | | | | | | varargs It unnecessarily breaks previously-working code which used varargs, but didn't pass any float/double arguments (such as EDK2). Also revert the fixup on top of that: Revert [X86] Fix a test from r357317 This reverts r357317 (git commit d413f41de6baf500e5d20c638375447e18777db2) This reverts r357380 (git commit 7af32444b9b17719ebabb6bee6eb52465acc8507) llvm-svn: 357718
* Appease STLs where std::atomic<void*> lacks a constexpr default ctorReid Kleckner2019-04-041-4/+2
| | | | | | | | MSVC 2019 casts the pointer to a pointer-sized integer, which is a reinterpret_cast, which is invalid in a constexpr context, so I have to remove the LLVM_REQUIRES_CONSTANT_INITIALIZATION annotation for now. llvm-svn: 357716
* Ensure that ManagedStatic is constant initialized in MSVC 2017 & 2019Reid Kleckner2019-04-041-3/+8
| | | | | | | | | | | | | | | | | | | Fixes PR41367. This effectively relands r357655 with a workaround for MSVC 2017. I tried various approaches with unions, but I ended up going with this ifdef approach because it lets us write the proper C++11 code that we want to write, with a separate workaround that we can delete when we drop MSVC 2017 support. This also adds LLVM_REQUIRE_CONSTANT_INITIALIZATION, which wraps [[clang::require_constant_initialization]]. This actually detected a minor issue when using clang-cl where clang wasn't able to use the constexpr constructor in MSVC's STL, so I switched back to using the default ctor of std::atomic<void*>. llvm-svn: 357714
* [WebAssembly] Add new explicit relocation types for PIC relocationsSam Clegg2019-04-047-28/+76
| | | | | | | | See https://github.com/WebAssembly/tool-conventions/pull/106 Differential Revision: https://reviews.llvm.org/D59907 llvm-svn: 357710
* [x86] eliminate unnecessary broadcast of horizontal opSanjay Patel2019-04-041-4/+14
| | | | | | | This is another pattern that comes up if we more aggressively scalarize FP ops. llvm-svn: 357703
* [RISCV] Support assembling TLS add and associated modifiersLewis Revill2019-04-049-11/+202
| | | | | | | | | | This patch adds support in the MC layer for parsing and assembling the 4-operand add instruction needed for TLS addressing. This also involves parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers. Differential Revision: https://reviews.llvm.org/D55341 llvm-svn: 357698
* [COFF] Fix delay import directory iteratorJoseph Tremoulet2019-04-041-1/+1
| | | | | | | | | | | | | | | | | | Summary: Take the Index into account in `getDelayImportTable`, otherwise we always return the entry for the first delay DLL reference. Reviewers: ruiu Reviewed By: ruiu Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60081 llvm-svn: 357697
* [SystemZ] Bugfix in isFusableLoadOpStorePattern()Jonas Paulsson2019-04-041-15/+16
| | | | | | | | | | | | | | | | | | | | | This function is responsible for checking the legality of fusing an instance of load -> op -> store into a single operation. In the SystemZ backend the check was incomplete and a test case emerged with a cycle in the instruction selection DAG as a result. Instead of using the NodeIds to determine node relationships, hasPredecessorHelper() now is used just like in the X86 backend. This handled the failing tests and as well gave a few additional transformations on benchmarks. The SystemZ isFusableLoadOpStorePattern() is now a very near copy of the X86 function, and it seems this could be made a utility function in common code instead. Review: Ulrich Weigand https://reviews.llvm.org/D60255 llvm-svn: 357688
* [Symbolize] Keep SymbolDescs with the same address and improve ↵Fangrui Song2019-04-042-3/+6
| | | | | | | | getNameFromSymbolTable heuristic I'll follow up with better heuristics or tests. llvm-svn: 357683
* [ARM GlobalISel] Support DBG_VALUEDiana Picus2019-04-041-0/+7
| | | | | | Make sure we can map and select DBG_VALUE. llvm-svn: 357681
* [AArch64][AsmParser] Fix .arch_extension directive parsingSander de Smalen2019-04-041-8/+2
| | | | | | | | | | | | | | | | | | This patch fixes .arch_extension directive parsing to handle a wider range of architecture extension options. The existing parser was parsing extensions as an identifier which breaks for extensions containing a "-", such as the "tlb-rmi" extension. The extension is now parsed as a string. This is consistent with the extension parsing in the .arch and .cpu directive parsing. Patch by Cullen Rhodes (c-rhodes) Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D60118 llvm-svn: 357677
* [llvm-symbolizer] Add `--output-style` switch.Igor Kudrin2019-04-041-1/+4
| | | | | | | | | | | | | In general, llvm-symbolizer follows the output style of GNU's addr2line. However, there are still some differences; in particular, for a requested address, llvm-symbolizer prints line and column, while addr2line prints only the line number. This patch adds a new switch to select the preferred style. Differential Revision: https://reviews.llvm.org/D60190 llvm-svn: 357675
* [InstCombine] Combine no-wrap sub and icmp w/ constant.Luqman Aden2019-04-041-1/+10
| | | | | | | | | | | | | | | | Teach InstCombine the transformation `(icmp P (sub nuw|nsw C2, Y), C) -> (icmp swap(P) Y, C2-C)` Reviewers: majnemer, apilipenko, sanjoy, spatel, lebedev.ri Reviewed By: lebedev.ri Subscribers: dmgreen, lebedev.ri, nikic, hiraditya, JDevlieghere, jfb, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59916 llvm-svn: 357674
* [X86] Use INSERT_SUBREG rather than SUBREG_TO_REG when creating LEA64_32 ↵Craig Topper2019-04-041-13/+8
| | | | | | | | | during isel. SUBREG_TO_REG is supposed to be used to assert that we know the upper bits are zero. But that isn't the case here. We've done no analysis of the inputs. llvm-svn: 357673
* [FastISel] Fix the crash in gc.result loweringSerguei Katkov2019-04-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The Fast ISel has a fallback to SelectionDAGISel in case it cannot handle the instruction. This works as follows: Using reverse order, try to select instruction using Fast ISel, if it cannot handle instruction it fallbacks to SelectionDAGISel for these instructions if it is a call and continue fast instruction selections. However if unhandled instruction is not a call or statepoint related instruction it fallbacks to SelectionDAGISel for all remaining instructions in basic block. However gc.result instruction is missed and as a result it is possible that gc.result is processed earlier than statepoint causing breakage invariant the gc.results should be handled after statepoint. Test is updated because in the current form fast-isel cannot handle ret instruction (due to i1 ret type without explicit ext) and as a result test does not check fast-isel at all. Reviewers: reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D60182 llvm-svn: 357672
* Revert r357452 - 'SimplifyCFG SinkCommonCodeFromPredecessors: Also sink ↵David L. Jones2019-04-041-15/+14
| | | | | | | | | | function calls without used results (PR41259)' This revision causes tests to fail under ASAN. Since the cause of the failures is not clear (could be ASAN, could be a Clang bug, could be a bug in this revision), the safest course of action seems to be to revert while investigating. llvm-svn: 357667
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