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* remove calls to calloc if the allocated memory is not used (it was already ↵Nuno Lopes2012-05-032-3/+3
| | | | | | | | being done for malloc) fix a few typos found by Chad in my previous commit llvm-svn: 156110
* Support for target dependent Hexagon VLIW packetizer.Sirish Pande2012-05-0314-93/+4967
| | | | | | This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
* add support for calloc to objectsize loweringNuno Lopes2012-05-032-5/+57
| | | | llvm-svn: 156102
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-4/+6
| | | | llvm-svn: 156077
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-039-1339/+4107
| | | | | | This adds new instructions for Hexagon V4 architecture. llvm-svn: 156071
* replace 'break's with 'return 0' in visitCallInst code for objectsize, since ↵Nuno Lopes2012-05-031-5/+5
| | | | | | | | there is no need to fallback to visitCallSite. This gives a 0.9% in a test case llvm-svn: 156069
* Use 'unsigned' instead of 'int' in a few places dealing with counts of ↵Craig Topper2012-05-031-3/+3
| | | | | | vector elements. llvm-svn: 156060
* Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the ↵Craig Topper2012-05-032-21/+36
| | | | | | lower half correctly. Missed in r155982. llvm-svn: 156059
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-031-15/+16
| | | | | | | | | | | | | | | | | | | | | | to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 llvm-svn: 156048
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-033-8/+40
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
* Whitespace cleanup.Bill Wendling2012-05-021-87/+80
| | | | llvm-svn: 156034
* Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, ↵Owen Anderson2012-05-021-0/+18
| | | | | | just like it now knows for FMULs. llvm-svn: 156029
* For Intel Atom, use ILP scheduling always, instead of ILP for 64 bitPreston Gurd2012-05-021-4/+4
| | | | | | | and Hybrid for 32 bit, since benchmarks show ILP scheduling is better most of the time. llvm-svn: 156028
* Change the Intel Atom detection code to recognizePreston Gurd2012-05-022-3/+5
| | | | | | Lincroft and Medfield. llvm-svn: 156025
* Teach DAG combine that multiplication by 1.0 can always be constant folded.Owen Anderson2012-05-021-0/+3
| | | | llvm-svn: 156023
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+2
| | | | llvm-svn: 156019
* Move llvm-tblgen's StringMatcher into the TableGen library so it canDouglas Gregor2012-05-022-0/+150
| | | | | | be used by clang-tblgen. llvm-svn: 156000
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-024-68/+171
| | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. llvm-svn: 155996
* Revert r155853Manman Ren2012-05-021-16/+0
| | | | | | | | The commit is intended to fix rdar://10961709. But it is the root cause of PR12720. Revert it for now. llvm-svn: 155992
* [tsan] typo and style (thanks to Nick Lewycky)Kostya Serebryany2012-05-021-9/+9
| | | | llvm-svn: 155986
* The value held in the vector may be RAUW'ed by some of the canonicalizationBill Wendling2012-05-021-2/+3
| | | | | | | methods. Use a weak value handle to keep up with this. PR12245 llvm-svn: 155984
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-021-4/+8
| | | | llvm-svn: 155983
* Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support ↵Craig Topper2012-05-024-36/+90
| | | | | | for AsmPrinter. llvm-svn: 155982
* Fix the implementation of MachOObjectFile::isSectionZeroInit so it follows ↵Eli Friedman2012-05-021-4/+6
| | | | | | the MachO spec. llvm-svn: 155976
* Tidy up. Naming conventions.Jim Grosbach2012-05-011-16/+16
| | | | llvm-svn: 155960
* Remove unneeded break.Jakub Staszak2012-05-011-1/+0
| | | | llvm-svn: 155959
* Use dyn_cast instead of checking opcode and cast.Jakub Staszak2012-05-011-2/+1
| | | | llvm-svn: 155957
* Remove trailing spaces.Jakub Staszak2012-05-011-43/+43
| | | | llvm-svn: 155956
* Strip the pointer casts off of allocas so that the selection DAG can find them.Bill Wendling2012-05-011-1/+1
| | | | | | PR10799 llvm-svn: 155954
* Target independent Hexagon Packetizer fix.Sirish Pande2012-05-011-55/+36
| | | | llvm-svn: 155947
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+11
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 llvm-svn: 155946
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-4/+16
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 llvm-svn: 155941
* This patch marks the X86 floating point stack registers ST0-ST7 as reservedPreston Gurd2012-05-011-0/+10
| | | | | | | | | in order to avoid assertion failures in the register scavenger. The assertion failures were “Bad machine code: Using an undefined physical register” and “Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor!”. llvm-svn: 155930
* MC: Unknown assembler directives are now hard errors.Jim Grosbach2012-05-011-1/+1
| | | | | | | | | | | | | | | | Previously, an unsupported/unknown assembler directive issued a warning. That's generally unsafe, and inconsistent with the behaviour of pretty much every system assembler. Now that the MC assemblers are mature enough to be the default on multiple targets, it's reasonable to issue errors for these. For target or platform directives that need to stay warnings, we should add explicit handlers for them in, e.g., ELFAsmParser.cpp, DarwinAsmParser.cpp, et. al., and issue the warning there. rdar://9246275 llvm-svn: 155926
* MC: Remove errant EatToEndOfStatement() in asm parser.Jim Grosbach2012-05-011-3/+1
| | | | | | | | | | | | The caller is already responsible for eating any additional input on the line. Putting an additional EatToEndOfStatement() in ParseStatement() causes an entire extra statement to be consumed when treating warnings as errors. For example, test/MC/macros.s will assert() because the .endmacro directive is missed as a result. rdar://11355843 llvm-svn: 155925
* X86: optimization for max-like structManman Ren2012-05-011-0/+40
| | | | | | | | | | | | | | | | | | | | | | | This patch will optimize the following cases on X86 (a > b) ? (a-b) : 0 (a >= b) ? (a-b) : 0 (b < a) ? (a-b) : 0 (b <= a) ? (a-b) : 0 FROM movl %edi, %ecx subl %esi, %ecx cmpl %edi, %esi movl $0, %eax cmovll %ecx, %eax TO xorl %eax, %eax subl %esi, %edi cmovll %eax, %edi movl %edi, %eax rdar: 10734411 llvm-svn: 155919
* X86: Use StackRegister instead of FrameRegister in getFrameIndexReference ↵Alexey Samsonov2012-05-012-0/+14
| | | | | | (to generate debug info for local variables) if stack needs realignment llvm-svn: 155917
* Move MipsDisassembler classes into an anonymous namespace.Benjamin Kramer2012-05-011-0/+4
| | | | llvm-svn: 155915
* Value-initialize global to avoid global construction.Benjamin Kramer2012-05-011-2/+2
| | | | llvm-svn: 155909
* RuntimeDyld cleanup:Eli Bendersky2012-05-014-65/+77
| | | | | | | | | | | - Improved parameter names for clarity - Added comments - emitCommonSymbols should return void because its return value is not being used anywhere - Attempt to reduce the usage of the RelocationValueRef type. Restricts it for a single goal and may serve as a step for eventual removal. llvm-svn: 155908
* YAMLParser: get rid of global ctors & dtors.Benjamin Kramer2012-05-011-2/+0
| | | | llvm-svn: 155907
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-0112-70/+68
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* Allow BMI, AES, F16C, POPCNT, FMA3, and CLMUL to be detected on AMD processors.Craig Topper2012-05-011-9/+9
| | | | llvm-svn: 155899
* RuntimeDyld code cleanup:Eli Bendersky2012-05-016-30/+38
| | | | | | | | | - There's no point having a different type for the local and global symbol tables. - Renamed SymbolTable to GlobalSymbolTable to clarify the intention - Improved const correctness where relevant llvm-svn: 155898
* Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify ↵Craig Topper2012-05-011-9/+8
| | | | | | Bulldozer feature list. llvm-svn: 155897
* Attempt to handle MRMInitReg in emitVEXOpcodePrefix. Hopefully fixes PR12711.Craig Topper2012-05-011-1/+12
| | | | llvm-svn: 155896
* Make XOP imply AVX as its needed to legalize the registers types.Craig Topper2012-05-011-1/+2
| | | | llvm-svn: 155891
* Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES ↵Craig Topper2012-05-011-3/+3
| | | | | | and HasCLMUL predicates. llvm-svn: 155890
* Make CLMUL and AES imply SSE2 since its needed to legalize the type.Craig Topper2012-05-011-2/+4
| | | | llvm-svn: 155888
* Enable AVX and FMA4 for AMD Bulldozer processors.Craig Topper2012-05-011-5/+5
| | | | llvm-svn: 155885
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