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* Revert "Add 'thinlto_src_module' md with asserts or -enable-import-metadata"Piotr Padlewski2016-07-081-19/+6
| | | | | | | | | Reverting because of 17463 http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules/builds/17463 This reverts commit d20cb431bba2ba43b4c65a8556cff445bfefbb7c. llvm-svn: 274946
* Revert "InstCombine rule to fold truncs whose value is available"Anna Thomas2016-07-082-50/+17
| | | | | | | This reverts commit r274853. Caused failure in ppcBE build llvm-svn: 274943
* Lanai: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-081-6/+6
| | | | | | | Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr* in the Lanai backend. llvm-svn: 274942
* [MC, COFF] Permit a variable to be redefinedDavid Majnemer2016-07-081-19/+11
| | | | | | | | | Our assertions in WinCOFFStreamer had unexpected side effects resulting in symbols getting unexpectedly marked as used. This fixes PR28462. llvm-svn: 274941
* [TTI] Expose TTI::getGEPCost and use it in SLSR and NaryReassociate.Jingyue Wu2016-07-083-76/+19
| | | | | | NFC. llvm-svn: 274940
* AMDGPU: Remove unused control flow intrinsicMatt Arsenault2016-07-087-32/+0
| | | | llvm-svn: 274939
* Add 'thinlto_src_module' md with asserts or -enable-import-metadataPiotr Padlewski2016-07-081-6/+19
| | | | | | | | | | | | | | Summary: This way the metadata will be only generated when asserts enabled, or when -enable-import-metadata specified Reviewers: tejohnson, eraman, mehdi_amini Subscribers: mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D22167 llvm-svn: 274938
* Reapply r274829 with fix for FP vectorsMatt Arsenault2016-07-081-2/+4
| | | | llvm-svn: 274937
* [PM] name the new PM LAA class LoopAccessAnalysis (LAA) /NFCXinliang David Li2016-07-082-4/+4
| | | | llvm-svn: 274934
* MSP430: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-084-32/+31
| | | | | | | | Avoid implicit conversions from MachineInstrBundleIIterator to MachineInstr* in the MSP430 backend by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable. llvm-svn: 274933
* [InstCombine] don't form select from bitcasted logic ops if bitcasts have >1 useSanjay Patel2016-07-081-2/+2
| | | | | | | | | | | | | | | This isn't a sure thing (are 2 extra bitcasts less expensive than a logic op?), but we'll try to err on the conservative side by going with the case that has less IR instructions. Note: This question came up in http://reviews.llvm.org/D22114 , but this part is independent of that patch proposal, so I'm making this small change ahead of that one. See also: http://reviews.llvm.org/rL274926 llvm-svn: 274932
* NVPTX: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-083-22/+21
| | | | | | | | | | | | | | | | | Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr* in the NVPTX backend, mainly by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable and using range-based for loops. There was one piece of questionable code in NVPTXInstrInfo::AnalyzeBranch, where a condition checked a pointer converted from an iterator for nullptr. Since this case is impossible (moreover, the code above guarantees that the iterator is valid), I removed the check when I changed the pointer to a reference. Despite that case, there should be no functionality change here. llvm-svn: 274931
* Allow dead insts to be kept in DeadRemat only when they are rematerializable.Wei Mi2016-07-085-18/+27
| | | | | | | | | | | | | | | Because isReallyTriviallyReMaterializableGeneric puts many limits on rematerializable instructions, this fix can prevent instructions with tied virtual operands and instructions with virtual register uses from being kept in DeadRemat, so as to workaround the live interval consistency problem for the dummy instructions kept in DeadRemat. But we still need to fix the live interval consistency problem. This patch is just a short time relieve. PR28464 has been filed as a reminder. Differential Revision: http://reviews.llvm.org/D19486 llvm-svn: 274928
* Rename LoopAccessAnalysis to LoopAccessLegacyAnalysis /NFCXinliang David Li2016-07-087-30/+30
| | | | llvm-svn: 274927
* [InstCombine] don't form select from logic ops if it's unlikely that we'll ↵Sanjay Patel2016-07-081-17/+22
| | | | | | eliminate any ops llvm-svn: 274926
* AArch64: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-088-222/+217
| | | | | | | | Avoid implicit conversions from MachineInstrBundleInstr to MachineInstr* in the AArch64 backend, mainly by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable. llvm-svn: 274924
* Remove duplicate inclusion /NFCXinliang David Li2016-07-081-1/+0
| | | | llvm-svn: 274921
* ARM: Remove implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-088-135/+124
| | | | | | | | | | | Remove remaining implicit conversions from MachineInstrBundleIterator to MachineInstr* from the ARM backend. In most cases, I made them less attractive by preferring MachineInstr& or using a ranged-based for loop. Once all the backends are fixed I'll make the operator explicit so that this doesn't bitrot back. llvm-svn: 274920
* Remove inline hints computation from SampleProfile.cppDehao Chen2016-07-081-70/+0
| | | | | | | | | | | | Summary: As we will move to use uniformed hotness check in inliner, we do not need inline hints in SampleProfile pass any more. Reviewers: dnovillo, davidxl Subscribers: eraman, llvm-commits Differential Revision: http://reviews.llvm.org/D19287 llvm-svn: 274918
* Revert r274829, it caused PR28472.Nico Weber2016-07-081-1/+1
| | | | llvm-svn: 274916
* Sparc: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-081-3/+3
| | | | | | | Remove the only implicit conversions from MachineInstrBundleIterator to MachineInstr* in the Sparc backend. llvm-svn: 274913
* WebAssembly: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-083-33/+30
| | | | | | | | Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr* in the WebAssembly backend by preferring MachineInstr& over MachineInstr*. llvm-svn: 274912
* AsmPrinter: Avoid implicit iterator conversions in ↵Duncan P. N. Exon Smith2016-07-081-2/+2
| | | | | | DbgValueHistoryCalculator, NFC llvm-svn: 274911
* [CrossDSOCFI] Change the pass so that it doesn't require doInitialization()Davide Italiano2016-07-081-19/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D21357 llvm-svn: 274910
* [X86][AVX2] Add support for target shuffle combining to VPERMPD/VPERMQSimon Pilgrim2016-07-081-2/+19
| | | | llvm-svn: 274908
* SelectionDAG: Avoid implicit iterator conversions in SelectionDAGBuilder, NFCDuncan P. N. Exon Smith2016-07-081-1/+2
| | | | llvm-svn: 274907
* AMDGPU: Remove implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-089-172/+176
| | | | | | | | | | | Remove remaining implicit conversions from MachineInstrBundleIterator to MachineInstr* from the AMDGPU backend. In most cases, I made them less attractive by preferring MachineInstr& or using a ranged-based for loop. Once all the backends are fixed I'll make the operator explicit so that this doesn't bitrot back. llvm-svn: 274906
* [SCCP] Fold constants as we build them whne visiting cast instructions.Davide Italiano2016-07-081-2/+4
| | | | | | | | | This should be slightly more efficient and could avoid spurious overdefined markings, as Eli pointed out. Differential Revision: http://reviews.llvm.org/D22122 llvm-svn: 274905
* SelectionDAG: Avoid implicit iterator conversions in SelectionDAGISel, NFCDuncan P. N. Exon Smith2016-07-081-8/+8
| | | | llvm-svn: 274904
* SelectionDAG: Avoid implicit iterator conversions in ScheduleDAGSDNodes, NFCDuncan P. N. Exon Smith2016-07-081-1/+1
| | | | llvm-svn: 274903
* AMDGPU: Make infinite loop clear, NFCDuncan P. N. Exon Smith2016-07-081-1/+2
| | | | | | | | | | | | | | | Change a while loop that was checking for nullptr on an iterator-to-pointer conversion to an infinite for loop. Now it's clear that the condition doesn't terminate. The only change in behaviour is if an invalid iterator (holding nullptr) was passed into AMDGPUCFGStructurizer::reversePredicateSetter. There are only two callers, and they both dereference the iterator before sending it in, so rather than adding an early return to avoid the loop I've just asserted (using a static_cast, to avoid an implicit conversion to pointer). llvm-svn: 274902
* SelectionDAG: Avoid implicit iterator conversions in FastISel, NFCDuncan P. N. Exon Smith2016-07-081-3/+4
| | | | llvm-svn: 274899
* Target: Avoid getFirstTerminator() => pointer, NFCDuncan P. N. Exon Smith2016-07-083-10/+10
| | | | | | | | | | | | | | Stop using an implicit conversion from the return of MachineBasicBlock::getFirstTerminator to MachineInstr*. In two cases, directly dereference to a MachineInstr& since later code assumes it's valid. In a third case, change to an iterator since later code checks against MachineBasicBlock::end. Although the fix for the third case avoids undefined behaviour, I expect this doesn't cause a functionality change in practice (since the basic block already has a terminator). llvm-svn: 274898
* CodeGen: Avoid iterator conversions in TwoAddressInstructionPass, NFCDuncan P. N. Exon Smith2016-07-081-55/+51
| | | | | | | | | | | | Mostly through preferring MachineInstr&, avoid implicit conversions from iterator to pointer. Although this may bitrot (since there are other uses blocking me from removing the implicit operator), this removes the last of the implicit conversions from MachineInstrBundleIterator to MachineInstr* in the LLVMCodeGen build target. llvm-svn: 274893
* CodeGen: Use MachineInstr& in StackSlotColoring, NFCDuncan P. N. Exon Smith2016-07-081-14/+11
| | | | | | Avoid implicit iterator to pointer conversions. llvm-svn: 274892
* [InstCombine] check for one-use before turning simple logic op into a selectSanjay Patel2016-07-081-2/+2
| | | | llvm-svn: 274891
* IR: Set a TargetPrefix for nvvm intrinsicsJustin Bogner2016-07-081-2/+3
| | | | | | | | | Since these are named nvvm_* rather than nvptx_*, we also need to update getArchTypePrefix. It's a bit unusual for getArchTypePrefix not to match the backend name, but I think this fits the intent of the function in this case. llvm-svn: 274890
* CodeGen: Use MachineInstr& in RegisterScavenging, NFCDuncan P. N. Exon Smith2016-07-081-16/+15
| | | | | | | Prefer MachineInstr& in order to avoid implicit conversions from MachineInstrBundleIterator to MachineInstr*. llvm-svn: 274888
* AMDGPU: Minor adjustment to r274817Matt Arsenault2016-07-081-1/+1
| | | | | | | | | | The commit message is inaccurate, modifiesRegister will check for partial defs of exec. We currently don't ever emit partial defs of exec, so it doesn't really matter. llvm-svn: 274886
* [InstCombine] allow or(sext(A), B) --> A ? -1 : B transform for vectorsSanjay Patel2016-07-081-4/+5
| | | | llvm-svn: 274883
* [SystemZ] Add support for the .word directive.Zhan Jun Liau2016-07-081-0/+3
| | | | | | | | | | | | | Summary: Branch off the work to add support for the .word directive, using addAliasForDirective. Reviewers: koriakin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22142 llvm-svn: 274878
* [DSE] Minor refactor based on D21007. NFC.Chad Rosier2016-07-081-39/+50
| | | | llvm-svn: 274877
* [CodeGen, TargetPassConfig] Remove a race from createRegAllocPassDavid Majnemer2016-07-081-6/+14
| | | | | | | | The createRegAllocPass reads and writes to a global variable 'Registry' via calls to getDefault and setDefault. Run this under a call_once to avoid races. llvm-svn: 274875
* PeepholeOptimizer: Make pass name match DEBUG_TYPEMatt Arsenault2016-07-081-2/+2
| | | | llvm-svn: 274874
* [SystemZ] Add support for missing instructionsZhan Jun Liau2016-07-082-4/+93
| | | | | | | | | | | | | | | | | Summary: Add support to allow clang integrated assembler to recognize some missing instructions, for openssl. Instructions are: LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL. Reviewers: uweigand Subscribers: koriakin, llvm-commits Differential Revision: http://reviews.llvm.org/D22050 llvm-svn: 274869
* Move setName after accessing NameEric Liu2016-07-081-5/+2
| | | | llvm-svn: 274862
* Make a std::string copy of StringRef Name so that it remains valid when the ↵Eric Liu2016-07-081-1/+4
| | | | | | | | | | | | | | original Name is overridden. Summary: lib/IR/AutoUpgrade.cpp:348 and lib/IR/AutoUpgrade.cpp:350 upset sanitizer. Reviewers: bkramer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22140 llvm-svn: 274861
* [Sparc] Leon errata fix passes.Chris Dewhurst2016-07-088-173/+869
| | | | | | | | | | | | Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
* Do not expand SDIV when compiling for minimum code sizeSjoerd Meijer2016-07-081-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D22139 llvm-svn: 274855
* InstCombine rule to fold truncs whose value is availableAnna Thomas2016-07-082-17/+50
| | | | | | | | | | | | | We can fold truncs whose operand feeds from a load, if the trunc value is available through a prior load/store. This change is from: http://reviews.llvm.org/D21246, which folded the trunc but missed the bitcast or ptrtoint/inttoptr required in the RAUW call, when the load type didnt match the prior load/store type. Differential Revision: http://reviews.llvm.org/D21791 llvm-svn: 274853
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