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* Fix some compilation errors on msvc:Ted Kremenek2008-03-092-3/+4
| | | | | | | | | - "Redefinition of I" (iterator masks previous definition) - include missing header file Patch by Argiris Kirtzidis! llvm-svn: 48115
* And again.Nick Lewycky2008-03-091-1/+2
| | | | llvm-svn: 48112
* Braces belong here. No functionality change.Nick Lewycky2008-03-091-1/+2
| | | | llvm-svn: 48111
* SCCP also needs to be taught to follow unwind_toNick Lewycky2008-03-091-0/+4
| | | | llvm-svn: 48109
* fp_round's produced by getCopyFromParts should always be exact, becauseChris Lattner2008-03-091-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | they are produced by calls (which are known exact) and by cross block copies which are known to be produced by extends. This improves: define double @test2() { %tmp85 = call double asm sideeffect "fld0", "={st(0)}"() ret double %tmp85 } from: _test2: subl $20, %esp # InlineAsm Start fld0 # InlineAsm End fstpl 8(%esp) movsd 8(%esp), %xmm0 movsd %xmm0, (%esp) fldl (%esp) addl $20, %esp #FP_REG_KILL ret to: _test2: # InlineAsm Start fld0 # InlineAsm End #FP_REG_KILL ret by avoiding a f64 <-> f80 trip llvm-svn: 48108
* teach X86InstrInfo::copyRegToReg how to copy into ST(0) from Chris Lattner2008-03-092-16/+41
| | | | | | | | | | | | an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
* Don't eliminate blocks that are only reachable by unwind_to.Nick Lewycky2008-03-091-2/+8
| | | | llvm-svn: 48106
* Add ScheduleDAG support for copytoreg where the src/dst register areChris Lattner2008-03-091-16/+19
| | | | | | | | in different register classes, e.g. copy of ST(0) to RFP*. This gets some really trivial inline asm working that plops things on the top of stack (PR879) llvm-svn: 48105
* add some code to support cross-register class copying from Chris Lattner2008-03-091-4/+22
| | | | | | RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
* rearrange some code, no functionality change.Chris Lattner2008-03-091-58/+59
| | | | llvm-svn: 48101
* fix 80 col violationChris Lattner2008-03-091-1/+2
| | | | llvm-svn: 48100
* Firstly, having a BranchInst isn't exclusive with having an unwind_to.Nick Lewycky2008-03-091-5/+8
| | | | | | | Secondly, we have to check whether the branch is actually pointing to the block with the unwind in it. We could have gotten here because of the unwind_to alone. llvm-svn: 48099
* claim ST(x) registers are 80 bits, which is true. This doesn't affect Chris Lattner2008-03-091-1/+1
| | | | | | codegen yet because these can't be spilled (they don't exist until after RA). llvm-svn: 48098
* extend fp values with FP_EXTEND not FP_ROUND.Chris Lattner2008-03-091-3/+6
| | | | llvm-svn: 48097
* A BB that unwind_to an "unwind" inst is that same as one that doesn't unwind_toNick Lewycky2008-03-091-1/+4
| | | | | | at all. llvm-svn: 48096
* rename FP_SETRESULT -> FP_SET_ST0Chris Lattner2008-03-094-15/+15
| | | | llvm-svn: 48094
* rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support forChris Lattner2008-03-095-46/+62
| | | | | | | isel'ing value preserving FP roundings from one fp stack reg to another into a noop, instead of stack traffic. llvm-svn: 48093
* Finish implementing a readme entry: when inserting an i64 variableChris Lattner2008-03-092-43/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | into a vector of zeros or undef, and when the top part is obviously zero, we can just use movd + shuffle. This allows us to compile vec_set-B.ll into: _test3: movl $1234567, %eax andl 4(%esp), %eax movd %eax, %xmm0 ret instead of: _test3: subl $28, %esp movl $1234567, %eax andl 32(%esp), %eax movl %eax, (%esp) movl $0, 4(%esp) movq (%esp), %xmm0 addl $28, %esp ret llvm-svn: 48090
* Update the block cloner which fixes bugpoint on code using unwind_to (phew!)Nick Lewycky2008-03-096-14/+43
| | | | | | and also update the cloning interface's major user, the loop optimizations. llvm-svn: 48088
* Update the inliner and simplifycfg to handle unwind_to.Nick Lewycky2008-03-092-1/+22
| | | | llvm-svn: 48086
* Two things. Preserve the unwind_to when splitting a BB.Nick Lewycky2008-03-092-6/+14
| | | | | | | Add the ability to remove just one instance of a BB from a phi node. This fixes the compile error in the tree now. llvm-svn: 48085
* Prune the unwind_to labels on BBs that don't need them. Another step in theNick Lewycky2008-03-091-3/+16
| | | | | | removal of invoke, PR1269. llvm-svn: 48084
* add a noteChris Lattner2008-03-091-0/+37
| | | | llvm-svn: 48064
* Implement a readme entry, compilingChris Lattner2008-03-092-26/+51
| | | | | | | | | | | | | | #include <xmmintrin.h> __m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);} into: movl $1, %eax movd %eax, %xmm0 ret instead of a constant pool load. llvm-svn: 48063
* Fix two problems in SelectionDAGLegalize::ExpandBUILD_VECTOR's handlingChris Lattner2008-03-091-21/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | of BUILD_VECTORS that only have two unique elements: 1. The previous code was nondeterminstic, because it walked a map in SDOperand order, which isn't determinstic. 2. The previous code didn't handle the case when one element was undef very well. Now we ensure that the generated shuffle mask has the undef vector on the RHS (instead of potentially being on the LHS) and that any elements that refer to it are themselves undef. This allows us to compile CodeGen/X86/vec_set-9.ll into: _test3: movd %rdi, %xmm0 punpcklqdq %xmm0, %xmm0 ret instead of: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret ... saving a register. llvm-svn: 48060
* Teach SD some vector identities, allowing us to compile vec_set-9 into:Chris Lattner2008-03-081-1/+13
| | | | | | | | | | | | | | | | | | | | | _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. llvm-svn: 48058
* 1) Improve comments.Chris Lattner2008-03-081-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | 2) Don't try to insert an i64 value into the low part of a vector with movq on an x86-32 target. This allows us to compile: __m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);} into: _doload64: movaps LCPI1_0, %xmm0 ret instead of: _doload64: subl $28, %esp movl $0, 4(%esp) movl $1, (%esp) movq (%esp), %xmm0 addl $28, %esp ret llvm-svn: 48057
* minor simplifications to this code, don't create a deadChris Lattner2008-03-081-6/+10
| | | | | | SCALAR_TO_VECTOR on paths that end up not using it. llvm-svn: 48056
* This one looks easy, add a note.Chris Lattner2008-03-081-1/+2
| | | | llvm-svn: 48055
* move these to the appropriate fileChris Lattner2008-03-082-53/+57
| | | | llvm-svn: 48054
* Not all users of a BB are Instructions any more.Nick Lewycky2008-03-081-1/+6
| | | | llvm-svn: 48047
* Load the symbols first so that the interpreter constructor can find them whenNick Lewycky2008-03-081-9/+5
| | | | | | it tries to initialize them. llvm-svn: 48046
* Remove unused runPass methods.Dan Gohman2008-03-081-14/+0
| | | | llvm-svn: 48044
* More ppc32 byval handling (bug fixes). ThingsDale Johannesen2008-03-081-3/+23
| | | | | | are looking pretty good now. llvm-svn: 48043
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-0813-17/+64
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Add support for calls with i128 return values on ppc64.Dan Gohman2008-03-081-3/+13
| | | | llvm-svn: 48041
* Something that kills a super-register alsoBill Wendling2008-03-071-2/+1
| | | | | | kills the sub-register. llvm-svn: 48038
* Fix a typo. It's causing consumer-typeset to miscompile. Perhaps more.Evan Cheng2008-03-071-1/+1
| | | | llvm-svn: 48035
* PPC64 passes arguments of integral type in i64 registers, not i32. Reflect thisBill Wendling2008-03-071-26/+43
| | | | | | | by promoting smaller integral values (i32 at this point) to i64, then truncating to get the wanted size. llvm-svn: 48030
* Add support for lowering 128-bit shifts on ppc64.Dan Gohman2008-03-071-44/+60
| | | | llvm-svn: 48029
* Next bits of PPC byval handling. Basically functionalDale Johannesen2008-03-071-7/+73
| | | | | | but there are bugs. llvm-svn: 48028
* Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).Chris Lattner2008-03-072-6/+16
| | | | llvm-svn: 48027
* Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to workChris Lattner2008-03-071-6/+3
| | | | | | with 32 or 64-bit operands/results. llvm-svn: 48026
* Fixed a register scavenger bug. If a def is re-defining part of a super ↵Evan Cheng2008-03-071-3/+8
| | | | | | register, there must be an implicit def of the super-register on the MI. llvm-svn: 48024
* Update inliner to handle functions that return multiple values.Devang Patel2008-03-071-43/+52
| | | | llvm-svn: 48020
* fix 80 col violationsChris Lattner2008-03-072-2/+4
| | | | llvm-svn: 48019
* add a pass that can extract all kinds of global values, not just functions. ↵Andrew Lenharth2008-03-071-0/+174
| | | | | | Update llvm-extract to use it and optionally extract a global variable if you want it too llvm-svn: 48015
* Clarify some important bitsAnton Korobeynikov2008-03-071-1/+2
| | | | llvm-svn: 48010
* Small cleanup: propagate thread-localness via generic routine.Anton Korobeynikov2008-03-071-7/+10
| | | | | | No functionality change. llvm-svn: 48009
* mark frem as expand for all legal fp types on x86, regardless of whetherChris Lattner2008-03-071-3/+2
| | | | | | we're using SSE or not. This fixes PR2122. llvm-svn: 48006
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