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* [InstCombine] break up visitICmpInstWithInstAndIntCst(); NFCISanjay Patel2016-07-212-155/+166
| | | | | | | Making smaller pieces out of some of these ~1000 line functions should make it easier to incrementally upgrade them to handle vector types. llvm-svn: 276304
* [AMDGPU] Emit read-only data to .rodata for hsaKonstantin Zhuravlyov2016-07-211-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D22538 llvm-svn: 276298
* [IRTranslator] Add G_AND opcode.Quentin Colombet2016-07-211-0/+2
| | | | | | This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
* AMDGPU/SI: Add support for R_AMDGPU_ABS32Konstantin Zhuravlyov2016-07-211-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D21646 llvm-svn: 276294
* [AArch64] Load/store opt: Don't count transient instructions towards search ↵Geoff Berry2016-07-211-15/+14
| | | | | | | | | | | | | | | | | | limits. Summary: This change also changes findMatchingInsn and findMatchingUpdateInsnForward to take DBG_VALUE opcodes into account when tracking register defs and uses, which could potentially inhibit these optimizations in the presence of debug information. Reviewers: mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22582 llvm-svn: 276293
* [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th elementSimon Pilgrim2016-07-211-6/+15
| | | | | | | | | | | | | | Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
* [X86][SSE] Pull out duplicate EXTRW lowering code. NFCI.Simon Pilgrim2016-07-211-26/+16
| | | | | | As requested on D22509, I've pulled out the v8i16 extraction lowering as the SSE41 and pre-SSE41 implementations are effectively the same. llvm-svn: 276285
* [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128Simon Pilgrim2016-07-214-12/+72
| | | | | | | | | | | | As reported on PR26235, we don't currently make use of the VBROADCASTF128/VBROADCASTI128 instructions (or the AVX512 equivalents) to load+splat a 128-bit vector to both lanes of a 256-bit vector. This patch enables lowering from subvector insertion/concatenation patterns and auto-upgrades the llvm.x86.avx.vbroadcastf128.pd.256 / llvm.x86.avx.vbroadcastf128.ps.256 intrinsics to match. We could possibly investigate using VBROADCASTF128/VBROADCASTI128 to load repeated constants as well (similar to how we already do for scalar broadcasts). Differential Revision: https://reviews.llvm.org/D22460 llvm-svn: 276281
* [DemandedBits] Reduce number of duplicated DenseMap lookups.Benjamin Kramer2016-07-211-5/+4
| | | | | | No functionality change intended. llvm-svn: 276278
* Rename StringMap::emplace_second to try_emplace.Benjamin Kramer2016-07-212-2/+2
| | | | | | | Coincidentally this function maps to the C++17 try_emplace. Rename it for consistentcy with C++17 std::map. NFC. llvm-svn: 276276
* [AMDGPU] Some code cleaning in SIRegisterInfo.tdSam Kolton2016-07-211-33/+23
| | | | | | | | | | Reviewers: tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: https://reviews.llvm.org/D22620 llvm-svn: 276274
* ExecutionDepsFix - Fix bug in clearance calculationMarina Yatsina2016-07-211-2/+0
| | | | | | | | The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit. Differential Revision: http://reviews.llvm.org/D22580 llvm-svn: 276266
* [GCOV] Remove a layer of indirection.Benjamin Kramer2016-07-211-18/+10
| | | | | | | StringMap is designed to hold large values. No functionality change intended. llvm-svn: 276265
* AMDGPU: Fix phis from blocks split due to register indexingMatt Arsenault2016-07-211-15/+22
| | | | llvm-svn: 276257
* [GVNHoist] Preserve optimization hints which agreeDavid Majnemer2016-07-211-3/+17
| | | | | | | If we have optimization hints with agree with each other along different paths, preserve them. llvm-svn: 276248
* [GVNHoist] Don't wrongly preserve TBAADavid Majnemer2016-07-211-0/+12
| | | | | | | We hoisted loads/stores without taking into account which can cause miscompiles. llvm-svn: 276240
* [MergedLoadStoreMotion] Remove out of date commentDavid Majnemer2016-07-211-1/+0
| | | | llvm-svn: 276239
* Add missing import to fix the buildAmaury Sechet2016-07-211-0/+1
| | | | llvm-svn: 276237
* Expose AttributeSetNode, use it to provide aggregate getter for attribute in ↵Amaury Sechet2016-07-213-68/+126
| | | | | | | | | | | | | | the C API. Summary: See D19181 for context. Reviewers: whitequark, Wallbraker, jyknight, echristo, bkramer, void Subscribers: mehdi_amini Differential Revision: http://reviews.llvm.org/D21265 llvm-svn: 276236
* IPRA: Fix RegMask calculation for alias registersMatthias Braun2016-07-211-12/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes a very subtle bug in regmask calculation. Thanks to zan jyu Wong <zyfwong@gmail.com> for bringing this to notice. For example if CL is only clobbered than CH should not be marked clobbered but CX, RCX and ECX should be mark clobbered. Previously for each modified register all of its aliases are marked clobbered by markRegClobbred() in RegUsageInfoCollector.cpp but that is wrong because when CL is clobbered then MRI::isPhysRegModified() will return true for CL, CX, ECX, RCX which is correct behavior but then for CX, EXC, RCX we mark CH also clobbered as CH is aliased to CX,ECX,RCX so markRegClobbred() is not required because isPhysRegModified already take cares of proper aliasing register. A very simple test case has been added to verify this change. Please find relevant bug report here : http://llvm.org/PR28567 Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: https://reviews.llvm.org/D22400 llvm-svn: 276235
* [OptDiag] Missed these when making the IR Value a const pointerAdam Nemet2016-07-211-2/+4
| | | | llvm-svn: 276224
* [OptDiag,LV] Add hotness attribute to applied-optimization remarksAdam Nemet2016-07-212-7/+22
| | | | | | | Test coverage is provided by modifying the function in the FP-math testcase that we are allowed to vectorize. llvm-svn: 276223
* X86InstrInfo: No need for liveness analysis in classifyLEAReg()Matthias Braun2016-07-211-18/+2
| | | | | | | | | | | | | | | | | | | | classifyLEAReg() deals with switching operands from 32bit to 64bit in order to use a LEA64_32 instruction (for three address code goodness). It currently performs a liveness analysis to determine the kill/undef flag for the newly added operand. This should not be necessary: - If the previous operand had a kill flag, then the 32bit part of the register gets killed, this will kill the super register as well. - If the previous operand had an undef flag then we didn't care what value we read, just use the same flag on the new operand. (No matter what an operand with an undef flag won't affect liveness) This makes the code independent of the presence of kill flags because it avoids a call to MachineBasicBlock::computeRegisterLiveness(). Differential Revision: http://reviews.llvm.org/D22283 llvm-svn: 276222
* [InstCombine] LogicOpc (zext X), C --> zext (LogicOpc X, C) (PR28476)Sanjay Patel2016-07-212-28/+16
| | | | | | | | | | | | | | | | The benefits of this change include: 1. Remove DeMorgan-matching code that was added specifically to work-around the missing transform in http://reviews.llvm.org/rL248634. 2. Makes the DeMorgan transform work for vectors too. 3. Fix PR28476: https://llvm.org/bugs/show_bug.cgi?id=28476 Extending this transform to other casts and other associative operators may be useful too. See https://reviews.llvm.org/D22421 for a prerequisite for doing that though. Differential Revision: https://reviews.llvm.org/D22271 llvm-svn: 276221
* [OptDiag,LV] Add hotness attribute to the derived analysis remarksAdam Nemet2016-07-202-7/+31
| | | | | | | | This includes FPCompute and Aliasing. Testcase is based on no_fpmath.ll. llvm-svn: 276211
* [InstSimplify][InstCombine] don't crash when folding vector selects of icmpSanjay Patel2016-07-202-2/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D22602 llvm-svn: 276209
* Make help text more consistent. NFC.George Burgess IV2016-07-201-1/+1
| | | | llvm-svn: 276205
* [CFLAA] Add offset tracking in CFLGraph.George Burgess IV2016-07-201-13/+122
| | | | | | | | | | | | | | | | (Also, refactor our constexpr handling to be less insane). This patch lets us track field offsets in the CFL Graph, which is the first step to making CFLAA field/offset sensitive. Woohoo! Note that this patch shouldn't visibly change our behavior (since we make no use of the offsets we're now tracking), so we can't quite add tests for this yet. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22598 llvm-svn: 276201
* [NVPTX] Enable the load-store vectorizer on nvptx.Justin Lebar2016-07-202-1/+11
| | | | | | | | | | Reviewers: tra Subscribers: jholewinski, arsenm, asbirlea Differential Revision: https://reviews.llvm.org/D22592 llvm-svn: 276196
* [AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc ↵Geoff Berry2016-07-204-8/+2
| | | | | | -run-pass. NFCI. llvm-svn: 276193
* [OptDiag,LV] Add hotness attribute to analysis remarksAdam Nemet2016-07-203-54/+75
| | | | | | | | The earlier change added hotness attribute to missed-optimization remarks. This follows up with the analysis remarks (the ones explaining the reason for the missed optimization). llvm-svn: 276192
* [OptDiag] Take the IR Value as a const pointerAdam Nemet2016-07-201-2/+3
| | | | | | | | This helps because LoopAccessReport is passed around as a const reference and we derive the basic block passed as the Value parameter from the instruction in LoopAccessReport. llvm-svn: 276191
* [OptDiag] Wrap a long lineAdam Nemet2016-07-201-1/+2
| | | | llvm-svn: 276190
* [NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.Artem Belevich2016-07-204-21/+21
| | | | | | | | After r276153 the pass applies to both kernels and regular functions. Differential Revision: https://reviews.llvm.org/D22583 llvm-svn: 276189
* GlobalISel: implement Legalization querying framework.Tim Northover2016-07-202-0/+129
| | | | | | | This adds an (incomplete, inefficient) framework for deciding what to do with some operation on a given type. llvm-svn: 276184
* [AArch64][FastISel] Select -O0 legal cmpxchg.Ahmed Bougacha2016-07-201-0/+55
| | | | | | | | | | | At -O0, cmpxchg survives AtomicExpand: it's mostly straightforward to select it in fast-isel, and let the pseudo be expanded later. extractvalues on the result are the tricky part: the generic logic only works for legal types (and it would be painful to make it support illegal types), so we can only support i32/i64 cmpxchg. llvm-svn: 276183
* [AArch64][FastISel] Select atomic stores into STLR.Ahmed Bougacha2016-07-201-3/+40
| | | | llvm-svn: 276182
* [GVNHoist] Don't hoist PHI nodesDavid Majnemer2016-07-201-4/+8
| | | | | | | | | We hoisted PHIs without respecting their special insertion point in the block, leading to verfier errors. This fixes PR28626. llvm-svn: 276181
* [SCCP] Zap multiple return values.Davide Italiano2016-07-201-9/+41
| | | | | | | | | We can replace the return values with undef if we replaced all the call uses with a constant/undef. Differential Revision: https://reviews.llvm.org/D22336 llvm-svn: 276174
* [LSV] Don't move stores across may-load instrs, and loosen restrictions on ↵Justin Lebar2016-07-201-2/+18
| | | | | | | | | | | | | | | | | | | | | moving loads. Summary: Previously we wouldn't move loads/stores across instructions that had side-effects, where that was defined as may-write or may-throw. But this is not sufficiently restrictive: Stores can't safely be moved across instructions that may load. This patch also adds a DEBUG check that all instructions in our chain are either loads or stores. Reviewers: asbirlea Subscribers: llvm-commits, jholewinski, arsenm, mzolotukhin Differential Revision: https://reviews.llvm.org/D22547 llvm-svn: 276171
* [LSV] Vectorize up to side-effecting instructions.Justin Lebar2016-07-201-7/+3
| | | | | | | | | | | | | | | Summary: Previously if we had a chain that contained a side-effecting instruction, we wouldn't vectorize it at all. Now we'll vectorize everything that comes before the side-effecting instruction. Reviewers: asbirlea Subscribers: arsenm, jholewinski, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D22536 llvm-svn: 276170
* [MSSA] Add an overload for getClobberingMemoryAccess.George Burgess IV2016-07-201-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A seemingly common use for the walker's getClobberingMemoryAccess function is: ``` MemoryAccess *getClobber(MemorySSAWalker *W, MemoryUseOrDef *MUD) { const Instruction *I = MUD->getMemoryInst(); return W->getClobberingMemoryAccess(I); } ``` Which is kind of redundant, since walkers will ultimately query MSSA to find out which MemoryAccess `I` maps to (...which is always `MUD`). So, this patch adds an overload of getClobberingMemoryAccess that accepts MemoryAccesses directly. As a result, the Instruction overload of getClobberingMemoryAccess becomes a lightweight wrapper around our new overload. Additionally, this patch un`virtual`izes the Instruction overload of getClobberingMemoryAccess, since there doesn't seem to be a walker that benefits from that being virtual, and I can't think of how else one would implement it. Happy to make it virtual again if we would benefit from doing so. llvm-svn: 276169
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-2012-92/+156
| | | | | | | | This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158
* Properly ifdef the use of cpuid.Alina Sbirlea2016-07-201-1/+6
| | | | llvm-svn: 276156
* [NVPTX] deal with all aggregate return types.Artem Belevich2016-07-201-6/+6
| | | | | | | | Fixes a crash in llvm_unreachable when a function has array return type. Differential Revision: https://reviews.llvm.org/D22524 llvm-svn: 276154
* [NVPTX] Improve lowering of byval args of device functions.Artem Belevich2016-07-203-32/+45
| | | | | | | | | | | | Avoid unnecessary spills of byval arguments of device functions to local space on SASS level and subsequent pointer conversion to generic address space that follows. Instead, make a local copy in IR, provide a way to access arguments directly, and let LLVM optimize the copy away when possible. Differential Review: https://reviews.llvm.org/D21421 llvm-svn: 276153
* [cpu-detection] Cleanup of Host.cpp.Alina Sbirlea2016-07-201-46/+48
| | | | | | | | | | | | | | Summary: Mirroring most cleanup changed from compiler-rt/lib/builtins/cpu_model. x86 methods are still returning a bool. Reviewers: llvm-commits, echristo, craig.topper, sanjoy Subscribers: mehdi_amini Differential Revision: https://reviews.llvm.org/D22480 llvm-svn: 276149
* move decomposeBitTestICmp() to Transforms/Utils; NFCSanjay Patel2016-07-202-47/+44
| | | | | | | | As noted in https://reviews.llvm.org/D22537 , we can use this functionality in visitSelectInstWithICmp() and InstSimplify, but currently we have duplicated code. llvm-svn: 276140
* Use ValueOffsetPair to enhance value reuse during SCEV expansion.Wei Mi2016-07-202-33/+80
| | | | | | | | | | | | | | | | | | | | | | | In D12090, the ExprValueMap was added to reuse existing value during SCEV expansion. However, const folding and sext/zext distribution can make the reuse still difficult. A simplified case is: suppose we know S1 expands to V1 in ExprValueMap, and S1 = S2 + C_a S3 = S2 + C_b where C_a and C_b are different SCEVConstants. Then we'd like to expand S3 as V1 - C_a + C_b instead of expanding S2 literally. It is helpful when S2 is a complex SCEV expr and S2 has no entry in ExprValueMap, which is usually caused by the fact that S3 is generated from S1 after const folding. In order to do that, we represent ExprValueMap as a mapping from SCEV to ValueOffsetPair. We will save both S1->{V1, 0} and S2->{V1, C_a} into the ExprValueMap when we create SCEV for V1. When S3 is expanded, it will first expand S2 to V1 - C_a because of S2->{V1, C_a} in the map, then expand S3 to V1 - C_a + C_b. Differential Revision: https://reviews.llvm.org/D21313 llvm-svn: 276136
* fix documentation comments; NFCSanjay Patel2016-07-201-32/+0
| | | | llvm-svn: 276135
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