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* AMDGPU: Fix bug causing crash due to invalid opencl version metadata.Yaxun Liu2016-07-201-9/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D22526 llvm-svn: 276119
* Revert "[InstCombine] Enable cast-folding in logic(cast(icmp), cast(icmp))"Benjamin Kramer2016-07-201-8/+2
| | | | | | | | Makes InstCombine infloop when compiling v8. This reverts commit r275989 and r276105. llvm-svn: 276106
* [X86][SSE] Add cost model values for CTPOP of vectorsSimon Pilgrim2016-07-202-4/+29
| | | | | | | | This patch adds costs for the vectorized implementations of CTPOP, the default values were seriously underestimating the cost of these and was encouraging vectorization on targets where serialized use of POPCNT would be much better. Differential Revision: https://reviews.llvm.org/D22456 llvm-svn: 276104
* [ARM] Skip inline asm memory operands in DAGToDAGISelDiana Picus2016-07-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | Retry r275776 (no changes, we suspect the issue was with another commit). The current logic for handling inline asm operands in DAGToDAGISel interprets the operands by looking for constants, which should represent the flags describing the kind of operand we're dealing with (immediate, memory, register def etc). The operands representing actual data are skipped only if they are non-const, with the exception of immediate operands which are skipped explicitly when a flag describing an immediate is found. The oversight is that memory operands may be const too (e.g. for device drivers reading a fixed address), so we should explicitly skip the operand following a flag describing a memory operand. If we don't, we risk interpreting that constant as a flag, which is definitely not intended. Fixes PR26038 Differential Revision: https://reviews.llvm.org/D22103 llvm-svn: 276101
* [AVX512] Add a missing NoVLX to give priority to the AVX512 version of the ↵Craig Topper2016-07-201-1/+1
| | | | | | pattern. llvm-svn: 276088
* [X86] Use 'HasAVX1Only' to properly give priority to the AVX2 version ↵Craig Topper2016-07-201-1/+1
| | | | | | without relying on file ordering. llvm-svn: 276087
* [X86] Create some multiclasses to reduce the repeated patterns for ↵Craig Topper2016-07-201-171/+43
| | | | | | VEXTRACT(F/I)128/VINSERT(I/F)128. NFC llvm-svn: 276086
* [X86] Create some wrapper multiclasses to create AVX and SSE shift ↵Craig Topper2016-07-201-172/+90
| | | | | | instructions with less repeated code. NFC llvm-svn: 276085
* Revert "Disable this-return argument forwarding on ARM/AArch64"David Majnemer2016-07-202-16/+2
| | | | | | | | | Inference of the 'returned' attribute was fixed in r276008, lets try turning the backend support back on. This reverts commit r275677. llvm-svn: 276081
* [LV] Add hotness attribute to missed-optimization remarksAdam Nemet2016-07-201-11/+17
| | | | | | | The new OptimizationRemarkEmitter analysis pass is hooked up to both new and old PM passes. llvm-svn: 276080
* Revert "Revert r275883 and r275891. They seem to cause PR28608."Michael Zolotukhin2016-07-202-15/+69
| | | | | | | This reverts commit r276064, and thus reapplies r275891 and r275883 with a fix for PR28608. llvm-svn: 276077
* [LSV] Don't assume that loads/stores appear in address order in the BB.Justin Lebar2016-07-201-20/+40
| | | | | | | | | | | | | | | | Summary: getVectorizablePrefix previously didn't work properly in the face of aliasing loads/stores. It unwittingly assumed that the loads/stores appeared in the BB in address order. If they didn't, it would do the wrong thing. Reviewers: asbirlea, tstellarAMD Subscribers: arsenm, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D22535 llvm-svn: 276072
* Revert "RegScavenging: Add scavengeRegisterBackwards()"Matthias Braun2016-07-202-240/+108
| | | | | | | | | Reverting this commit for now as it seems to be causing failures on test-suite tests on the clang-ppc64le-linux-lnt bot. This reverts commit r276044. llvm-svn: 276068
* Codegen: Tail Duplication: Only duplicate into layout pred if it is a CFG Pred.Kyle Butt2016-07-201-0/+2
| | | | | | | | | Add a check that the layout predecessor of a block is an actual CFG predecssor of the block as well. No current code fails this check, but upcoming patches can trigger this, and it makes sense to separate it out. llvm-svn: 276066
* Revert r275883 and r275891. They seem to cause PR28608.Sean Silva2016-07-192-60/+13
| | | | | | | | | | | | Revert "[LoopSimplify] Update LCSSA after separating nested loops." This reverts commit r275891. Revert "[LCSSA] Post-process PHI-nodes created by SSAUpdate when constructing LCSSA form." This reverts commit r275883. llvm-svn: 276064
* [PM] Port LoopUnroll.Sean Silva2016-07-194-0/+43
| | | | | | | | | We just set PreserveLCSSA to always true since we don't have an analogous method `mustPreserveAnalysisID(LCSSA)`. Also port LoopInfo verifier pass to test LoopUnrollPass. llvm-svn: 276063
* Codegen: Factor out canTailDuplicateKyle Butt2016-07-191-9/+19
| | | | | | | | canTailDuplicate accepts two blocks and returns true if the first can be duplicated into the second successfully. Use this function to encapsulate the heuristic. llvm-svn: 276062
* Get rid of call to StringRef::substr that's never used.Justin Lebar2016-07-191-1/+0
| | | | | | | | | | | | Summary: substr doesn't modify the string, so this line has no effect. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22540 llvm-svn: 276057
* [LSV] Insert stores at the right point.Justin Lebar2016-07-191-30/+28
| | | | | | | | | | | | | | | | | | | | | Summary: Previously, the insertion point for stores was the last instruction in Chain *before calling getVectorizablePrefixEndIdx*. Thus if getVectorizablePrefixEndIdx didn't return Chain.size(), we still would insert at the last instruction in Chain. This patch changes our internal API a bit in an attempt to make it less prone to this sort of error. As a result, we end up recalculating the Chain's boundary instructions, but I think worrying about the speed hit of this is a premature optimization right now. Reviewers: asbirlea, tstellarAMD Subscribers: mzolotukhin, arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D22534 llvm-svn: 276056
* [LSV] Use make_range, and reformat a DEBUG message. NFCJustin Lebar2016-07-191-12/+15
| | | | | | | | | | | | | | | Summary: The DEBUG message was hard to read because two Values were being printed on the same line with only the delimiter "aliases". This change makes us print each Value on its own line. Reviewers: asbirlea Subscribers: llvm-commits, arsenm, mzolotukhin Differential Revision: https://reviews.llvm.org/D22533 llvm-svn: 276055
* [LSV] Nix two global (ish) variables in the LoadStoreVectorizer. NFCJustin Lebar2016-07-191-10/+12
| | | | | | | | | | Reviewers: asbirlea Subscribers: mzolotukhin, llvm-commits, arsenm Differential Revision: https://reviews.llvm.org/D22532 llvm-svn: 276054
* [libFuzzer] extend the messages printed by afl_driverKostya Serebryany2016-07-191-4/+12
| | | | llvm-svn: 276052
* AMDGPU: Change fdiv lowering based on !fpmath metadataMatt Arsenault2016-07-198-49/+227
| | | | | | | | | | | If 2.5 ulp is acceptable, denormals are not required, and isn't a reciprocal which will already be handled, replace with a faster fdiv. Simplify the lowering tests by using per function subtarget features. llvm-svn: 276051
* Fix unused variableDaniel Berlin2016-07-191-2/+1
| | | | llvm-svn: 276050
* Make GVN Hoisting obey optnone/bisect.Paul Robinson2016-07-191-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D22545 llvm-svn: 276048
* Make MemorySSA::dominates/locallydominates constant timeDaniel Berlin2016-07-191-16/+36
| | | | | | | | | | | | Summary: Make MemorySSA::dominates/locallydominates constant time Reviewers: george.burgess.iv, gberry Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22527 llvm-svn: 276046
* Add AIX support to Path.inc, Host.h, and CMake.Chandler Carruth2016-07-191-2/+3
| | | | | | | | Patch by Andrew Paprocki! Differential Revision: https://reviews.llvm.org/D18359 llvm-svn: 276045
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2016-07-192-108/+240
| | | | | | | | | | | | | | This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 276044
* RegisterScavenger: Introduce backward() mode.Matthias Braun2016-07-191-23/+84
| | | | | | | | | | | | | | | | This adds two pieces: - RegisterScavenger:::enterBasicBlockEnd() which behaves similar to enterBasicBlock() but starts tracking at the end of the basic block. - A RegisterScavenger::backward() method. It is subtly different from the existing unprocess() method which only considers uses with the kill flag set: If a value is dead at the end of a basic block with a last use inside the basic block, unprocess() will fail to mark it as live. However we cannot change/fix this behaviour because unprocess() needs to perform the exact reverse operation of forward(). Differential Revision: http://reviews.llvm.org/D21873 llvm-svn: 276043
* [AArch64] Properly validate the reciprocal estimation.Evandro Menezes2016-07-191-0/+6
| | | | | | | | Add check for legal data types when expanding into a Newton series. Differential Revision: https://reviews.llvm.org/D22267 llvm-svn: 276041
* [InstCombine] fold add(zext(xor X, C), C) --> sext X when C is INT_MIN in ↵Sanjay Patel2016-07-191-0/+10
| | | | | | | | | | | | | | | | | | | the source type The pattern may look more obviously like a sext if written as: define i32 @g(i16 %x) { %zext = zext i16 %x to i32 %xor = xor i32 %zext, 32768 %add = add i32 %xor, -32768 ret i32 %add } We already have that fold in visitAdd(). Differential Revision: https://reviews.llvm.org/D22477 llvm-svn: 276035
* Attempt to appease MSVC buildbots.George Burgess IV2016-07-191-8/+10
| | | | | | Broken by r276026. llvm-svn: 276032
* [AMDGPU] Remove spurious line (should've been removed in r276029).Davide Italiano2016-07-191-3/+0
| | | | llvm-svn: 276030
* [AMDGPU] Remove dead code.Davide Italiano2016-07-191-25/+0
| | | | | | LGTM'd by Matt Arsenault. llvm-svn: 276029
* [CFLAA] Add some interproc. analysis to CFLAnders.George Burgess IV2016-07-192-8/+188
| | | | | | | | | | | This patch adds function summary support to CFLAnders. It also comes with a lot of tests! Woohoo! Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22450 llvm-svn: 276026
* Next step along the way to getting good error messages for bad archives.Kevin Enderby2016-07-191-35/+46
| | | | | | | | | This step builds on Lang Hames work to change Archive::child_iterator for better interoperation with Error/Expected. Building on that it is now possible to return an error message when the size field of an archive contains non-decimal characters. llvm-svn: 276025
* [CFLAA] Teach CFLAnders to distinguish reads from writes.George Burgess IV2016-07-191-50/+95
| | | | | | | | | | | | | | | | | | | | | | | This patch adds more specific edges to CFLAndersAliasAnalysis. The goal of these edges is to give us more information about *how* two values that MayAlias alias. With this, we can now tell cases like a = b; // ergo, a may alias b apart from a = c; b = c; // so, a may alias b, but only because they were both assigned to c. ...And others. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22429 llvm-svn: 276023
* Use posix_fallocate instead of ftruncate.Rafael Espindola2016-07-191-0/+9
| | | | | | | | | | | This makes sure that space is actually available. With this change running lld on a full file system causes it to exit with failed to open foo: No space left on device instead of crashing with a sigbus. llvm-svn: 276017
* [tsan] Don't instrument __llvm_gcov_global_state_pred or __llvm_gcda*Vedant Kumar2016-07-191-2/+3
| | | | | | | | | | r274801 did not go far enough to allow gcov+tsan to cooperate. With this commit it's possible to run the following code without false positives: std::thread T1(fib), T2(fib); T1.join(); T2.join(); llvm-svn: 276015
* ARM: move feature for Thumb2 pkhbt/pkhtb onto architectures.Tim Northover2016-07-191-32/+14
| | | | | | | | | | | There's not much functional change, but it really is an architectural feature (on v6T2, v7A, v7R and v7EM) rather than something each CPU implements individually. The main functional change is the default behaviour you get when specifying only "-triple". llvm-svn: 276013
* [GlobalISel] Mark newly-created gvregs as having a bank.Ahmed Bougacha2016-07-192-3/+10
| | | | | | | | | | Also verify that we never try to set the size of a vreg associated to a register class. Report an error when we encounter that in MIR. Fix a testcase that hit that error and had a size for no reason. llvm-svn: 276012
* [GlobalISel] Simplify more RegClassOrRegBank is+get. NFC.Ahmed Bougacha2016-07-191-5/+3
| | | | llvm-svn: 276011
* [FunctionAttrs] Correct the safety analysis for inference of 'returned'David Majnemer2016-07-191-0/+51
| | | | | | | | | | | | We skipped over ReturnInsts which didn't return an argument which would lead us to incorrectly conclude that an argument returned by another ReturnInst was 'returned'. This reverts commit r275756. This fixes PR28610. llvm-svn: 276008
* [SCCP] Improve assert messages. NFCI.Davide Italiano2016-07-191-4/+6
| | | | | | | I've been hitting those already while working on SCCP and I think it's be useful to provide a more explanatory diagnostic. llvm-svn: 276007
* [libFuzzer] properly intercept memmemKostya Serebryany2016-07-192-2/+15
| | | | llvm-svn: 276006
* [DSE] Add additional debug output. NFC.Chad Rosier2016-07-191-0/+2
| | | | llvm-svn: 276005
* [RegionPass] Some minor cleanupsDavid Majnemer2016-07-191-4/+2
| | | | | | No functional change is intended. llvm-svn: 276000
* [LoopPass] Some minor cleanupsDavid Majnemer2016-07-191-7/+5
| | | | | | No functional change is intended. llvm-svn: 275999
* [DSE] Add additional debug output. NFC.Chad Rosier2016-07-191-0/+3
| | | | llvm-svn: 275991
* [InstCombine] Enable cast-folding in logic(cast(icmp), cast(icmp))Tobias Grosser2016-07-191-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently, InstCombine is already able to fold expressions of the form `logic(cast(A), cast(B))` to the simpler form `cast(logic(A, B))`, where logic designates one of `and`/`or`/`xor`. This transformation is implemented in `foldCastedBitwiseLogic()` in InstCombineAndOrXor.cpp. However, this optimization will not be performed if both `A` and `B` are `icmp` instructions. The decision to preclude casts of `icmp` instructions originates in r48715 in combination with r261707, and can be best understood by the title of the former one: > Transform (zext (or (icmp), (icmp))) to (or (zext (cimp), (zext icmp))) if at least one of the (zext icmp) can be transformed to eliminate an icmp. Apparently, it introduced a transformation that is a reverse of the transformation that is done in `foldCastedBitwiseLogic()`. Its purpose is to expose pairs of `zext icmp` that would subsequently be optimized by `transformZExtICmp()` in InstCombineCasts.cpp. Therefore, in order to avoid an endless loop of switching back and forth between these two transformations, the one in `foldCastedBitwiseLogic()` has been restricted to exclude `icmp` instructions which is mirrored in the responsible check: `if ((!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src)) && ...` This check seems to sort out more cases than necessary because: - the reverse transformation is obviously done for `or` instructions only - and also not every `zext icmp` pair is necessarily the result of this reverse transformation Therefore we now remove this check and replace it by a more finegrained one in `shouldOptimizeCast()` that now rejects only those `logic(zext(icmp), zext(icmp))` that would be able to be optimized by `transformZExtICmp()`, which also avoids the mentioned endless loop. That means we are now able to also simplify expressions of the form `logic(cast(icmp), cast(icmp))` to `cast(logic(icmp, icmp))` (`cast` being an arbitrary `CastInst`). As an example, consider the following IR snippet ``` %1 = icmp sgt i64 %a, %b %2 = zext i1 %1 to i8 %3 = icmp slt i64 %a, %c %4 = zext i1 %3 to i8 %5 = and i8 %2, %4 ``` which would now be transformed to ``` %1 = icmp sgt i64 %a, %b %2 = icmp slt i64 %a, %c %3 = and i1 %1, %2 %4 = zext i1 %3 to i8 ``` This issue became apparent when experimenting with the programming language Julia, which makes use of LLVM. Currently, Julia lowers its `Bool` datatype to LLVM's `i8` (also see https://github.com/JuliaLang/julia/pull/17225). In fact, the above IR example is the lowered form of the Julia snippet `(a > b) & (a < c)`. Like shown above, this may introduce `zext` operations, casting between `i1` and `i8`, which could for example hinder ScalarEvolution and Polly on certain code. Reviewers: grosser, vtjnash, majnemer Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D22511 Contributed-by: Matthias Reisinger llvm-svn: 275989
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