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* [ORC] Rename IRMaterializationUnit's Discardable member to SymbolToDefinition,Lang Hames2018-05-311-4/+6
| | | | | | | | | | and make it protected rather than private. The new name reflects the actual information in the map, and this information can be useful to derived classes (for example, to quickly look up the IR definition of a requested symbol). llvm-svn: 333683
* IRGen: Write .dwo files when -split-dwarf-file is used together with ↵Peter Collingbourne2018-05-311-1/+6
| | | | | | | | -fthinlto-index. Differential Revision: https://reviews.llvm.org/D47597 llvm-svn: 333677
* Relax GOTPCREL relocations for tail jmp instructions.Sriraman Tallam2018-05-311-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D47563 llvm-svn: 333676
* [JumpThreading] Fix some strange formatting of code inside LLVM_DEBUG. NFCCraig Topper2018-05-311-5/+5
| | | | | | I don't know if clang-format got confused here or what. llvm-svn: 333675
* [ADT] Make escaping fn conform to coding guidelinesJonas Devlieghere2018-05-314-16/+16
| | | | | | | | As noted by Adrian on llvm-commits, PrintHTMLEscaped and PrintEscaped in StringExtras did not conform to the LLVM coding guidelines. This commit rectifies that. llvm-svn: 333669
* [SimplifyLibcalls] [NFC] Cleanup, improvementsDavid Bolvansky2018-05-311-11/+9
| | | | | | | | | | | | | | | | Summary: * Use "find('%')" instead of loop to find '%' char (we already uses find('%') in optimizePrintFString..) * Convert getParent() chains to getModule()/getFunction() Reviewers: lebedev.ri, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47397 llvm-svn: 333668
* [MC] Fallback on DWARF when generating compact unwind on AArch64Francis Visoiu Mistrih2018-05-311-3/+11
| | | | | | | | | | | | | | | Instead of asserting when using the def_cfa directive with a register different from fp, fallback on DWARF. Easily triggered with: .cfi_def_cfa x1, 32; rdar://40249694 Differential Revision: https://reviews.llvm.org/D47593 llvm-svn: 333667
* [GlobalISel][Mips] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) ↵Roman Tereshin2018-05-311-0/+2
| | | | | | | | | | | | call for Mips Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333665
* [GlobalISel][AMDGPU] LegalizerInfo verifier: Adding ↵Roman Tereshin2018-05-311-0/+1
| | | | | | | | | | | | LegalizerInfo::verify(...) call for AMDGPU Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333664
* [GlobalISel][ARM] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) ↵Roman Tereshin2018-05-311-3/+5
| | | | | | | | | | | | call and fixing bugs exposed Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333663
* [GlobalISel][X86] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) ↵Roman Tereshin2018-05-311-2/+3
| | | | | | | | | | | | call and fixing bugs exposed Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333662
* [X86][SSE] Recognise splat rotations and expand back to shift ops.Simon Pilgrim2018-05-311-0/+12
| | | | | | Noticed while fixing PR37426, for splat rotations (rotation by an uniform value) its better to just expand back to shift ops than performing as a general non-uniform rotation. llvm-svn: 333661
* [X86][AVX] Add peekThroughEXTRACT_SUBVECTORs helper (NFCI)Simon Pilgrim2018-05-311-10/+10
| | | | | | We often need this for AVX1 128-bit integer ops as they may have been split from a 256-bit source. llvm-svn: 333660
* [DA] Fix direction vectors for weakZeroSrcSIVDavid Green2018-05-311-4/+4
| | | | | | | | | | Both weakZeroSrcSIV and weakZeroDstSIV are currently giving the same direction vectors. Fix weakZeroSrcSIVtest by flipping the directions it gives. Differential Revision: https://reviews.llvm.org/D46678 llvm-svn: 333658
* [X86] Introduce WriteFLDC for x87 constant loads.Clement Courbet2018-05-3111-10/+18
| | | | | | | | | | | | | | | | | Summary: {FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI} were using WriteMicrocoded. - I've measured the values for Broadwell, Haswell, SandyBridge, Skylake. - For ZnVer1 and Atom, values were transferred form InstRWs. - For SLM and BtVer2, I've guessed some values :( Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47585 llvm-svn: 333656
* [MCSchedule] Add the ability to compute the latency and throughput ↵Andrea Di Biagio2018-05-313-3/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information for MCInst. This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 llvm-svn: 333650
* Extend the GlobalObject metadata interfaceBenjamin Kramer2018-05-315-58/+53
| | | | | | | | | | | | - Make eraseMetadata return whether it changed something - Wire getMetadata for a single MDNode efficiently into the attachment map - Add hasMetadata, which is less weird than checking getMetadata == nullptr on a multimap. Use it to simplify code. llvm-svn: 333649
* [mips] Guard all short instructions correctly.Simon Dardis2018-05-312-22/+40
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47533 llvm-svn: 333645
* [InstCombine, ARM] Convert vld1 to llvm loadAlexandros Lamprineas2018-05-311-1/+30
| | | | | | | | | | Convert a vector load intrinsic into an llvm load instruction. This is beneficial when the underlying object being addressed comes from a constant, since we get constant-folding for free. Differential Revision: https://reviews.llvm.org/D46273 llvm-svn: 333643
* [X86] Extract latency of fldz/fld1 in separate classes.Clement Courbet2018-05-3111-10/+26
| | | | | | | | | | | | | | | | | Summary: - I've measured the values for Broadwell, Haswell, SandyBridge, Skylake. - For ZnVer1 and Atom, values were transferred form `InstRW`s. - For SLM and BtVer2, values are from Agner. This is split off from https://reviews.llvm.org/D47377 Reviewers: RKSimon, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47523 llvm-svn: 333642
* [X86][SSE] Add support for detecting SUB(SPLAT_BV, SPLAT) cases for ↵Simon Pilgrim2018-05-311-10/+36
| | | | | | | | shift-rotate patterns. This improves splat rotations (rotation by an uniform value), to avoid having to use the generic non-uniform shift code (extension to PR37426). llvm-svn: 333641
* DWARFAcceleratorTable: fix equal_range iteratorsPavel Labath2018-05-311-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Both (Apple and DWARF5) implementations of the iterators had bugs which resulted in crashes if one attempted to iterate through the accelerator tables all the way. For the Apple tables, the issue was that we did not clear the DataOffset field when we reached the end, which made our iterator compare unequal to the "end" iterator. For the Dwarf5 tables, the problem was that we incremented the CurrentIndex pointer and then used the incremented (possibly invalid) pointer to check whether we have reached the end of the index list. The reason these bugs went undetected is because their only user (dwarfdump) only ever searched for the first match. Besides allowing us to test this fix, changing llvm-dwarfdump --find to display all matches seems like a good improvement (it makes the behavior consistent with the --name option), so I change llvm-dwarfdump to do that. The existing tests would be sufficient to test this fix with the new llvm-dwarfdump behavior, but I add a special test that demonstrates that the tool indeed displays multiple results. The find.test test needed to be tweaked a bit as the tool now does not print the ".debug_info contents" header (also consistent with how --name works). Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D47543 llvm-svn: 333635
* [AArch64] Reverted rL333427 fixing Clang UnitTest FailureLuke Geeson2018-05-312-5/+39
| | | | llvm-svn: 333634
* [NFC] Factor out a method for further extensionMax Kazantsev2018-05-311-20/+32
| | | | llvm-svn: 333633
* Revert rL333106 / D46814: [InstCombine] Fold unfolded masked merge pattern ↵Roman Lebedev2018-05-311-36/+0
| | | | | | | | | | | | | with variable mask! In post-commit review, Eric Christopher notes that many new MSan warnings are being observed with this patch. The probable reason is: if 'y' is undef here and we could evaluate it twice and get different results. We can't increase the number of uses of a value. llvm-svn: 333631
* [AMDGPU] Track occupancy in MFIStanislav Mekhanoshin2018-05-316-13/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep track of achieved occupancy in SIMachineFunctionInfo. At the moment we have a lot of duplicated or even missed code to query and maintain occupancy info. Record it in the MFI and query in a single call. Interfaces: - getOccupancy() - returns current recorded achieved occupancy. - getMinAllowedOccupancy() - returns lesser of the achieved occupancy and the lowest occupancy we are ready to tolerate. For example if a kernel is memory bound we are ready to tolerate 4 waves. - limitOccupancy() - record occupancy level if we have to lower it. - increaseOccupancy() - record occupancy if scheduler managed to increase the occupancy. MFI takes care of integrating different checks affecting occupancy, including LDS use and waves-per-eu attribute. Note that scheduler starts with not yet known register pressure, so has to record either limit or increase in occupancy after it is done. Later passes can just query a resulting value. New interface is used in the active scheduler and NFC wrt its work. Changes are also made to experimental schedulers to use it and record an occupancy after they are done. Before the change waves-per-eu was ignored by experimental schedulers and tolerance window for memory bound kernels was not used. Differential Revision: https://reviews.llvm.org/D47509 llvm-svn: 333629
* AMDGPU/R600: Make sure functions are cacheline alignedJan Vesely2018-05-311-0/+4
| | | | | | | | | | | v2: use "ensureAlignment" make functions cache line aligned Fixes GPU hangs since r333219: "AMDGPU: Split R600 AsmPrinter code into its own class" Differential Revision: https://reviews.llvm.org/D47516 llvm-svn: 333622
* [GlobalISel][Legalizer] LegalizerInfo verifier: Making ↵Roman Tereshin2018-05-311-0/+3
| | | | | | | | | | | | LegalizerInfo::verify(...) errors fatal Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333619
* [GlobalISel][AArch64] LegalizerInfo verifier: Fixing bugs exposed by ↵Roman Tereshin2018-05-311-11/+4
| | | | | | | | | | | | LegalizerInfo::verify(...) Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333618
* [InstCombine] don't change the size of a select if it would mismatch its ↵Sanjay Patel2018-05-311-4/+10
| | | | | | | | | | | | | | | | | | | | | condition operands' sizes Don't always: cast (select (cmp x, y), z, C) --> select (cmp x, y), (cast z), C' This is something that came up as far back as D26556, and I lost track of it. I suspect that this transform is part of the underlying problem that is inspiring some of the recent proposals that seek to match larger patterns that include a cast op. Even if that's not true, this transform causes problems for codegen (particularly with vector types). A transform to actively match the size of cmp and select operand sizes should follow. This patch just removes the harmful canonicalization in the other direction. Differential Revision: https://reviews.llvm.org/D47163 llvm-svn: 333611
* [InstCombine] don't negate constant expression with fsub (PR37605)Sanjay Patel2018-05-301-1/+3
| | | | | | | X + (-C) would be transformed back into X - C, so infinite loop: https://bugs.llvm.org/show_bug.cgi?id=37605 llvm-svn: 333610
* AMDGPU: Split AMDGPUTTI into GCNTTI and R600TTITom Stellard2018-05-304-42/+212
| | | | | | | | | | | | Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D47359 llvm-svn: 333605
* [LowerTypeTests] Discard extern_weak linkage for definitionsVlad Tsyrklevich2018-05-301-0/+5
| | | | | | | | | | | | | | | | | | Summary: Fix PR37625. It's possible for an extern_weak declaration to be emitted to the merged module when a definition exists in the ThinLTO portion of the build; discard the linkage on the declaration in that case. (otherwise we copy the linkage to the alias to the jumptable and fail) Reviewers: pcc Reviewed By: pcc Subscribers: mehdi_amini, llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D47494 llvm-svn: 333604
* [NewGVN] Fix set comparison; reflow commentGeorge Burgess IV2018-05-301-7/+8
| | | | | | | | | | | | | | | | Looks like we intended to compare this->Members with Other->Members here, but ended up comparing this->Members with this->Members. Oops. :) Since CongruenceClass::Members is a SmallPtrSet anyway, we can probably skip building std::sets if we're willing to write a bit more code. This appears to be no functional change (for sufficiently lax values of "no"): this equality check was only being called inside of an assert. So, worst case, we'll catch more bugs in the form of assertion failures. Thanks to d0k for noting this! llvm-svn: 333601
* [GlobalISel][AArch64] LegalizerInfo verifier: Adding ↵Roman Tereshin2018-05-301-0/+1
| | | | | | | | | | | | | | | LegalizerInfo::verify(...) call w/o fixing bugs This is to make it clear what kind of bugs the LegalizerInfo::verifier is able to catch and test its output Reviewers: aemerson, qcolombet Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D46338 llvm-svn: 333597
* [IRBuilder] Add APIs for creating calls to atomic memmove and memset ↵Daniel Neilson2018-05-301-0/+70
| | | | | | | | | | | | | | intrinsics. (NFC) Summary: Creating the IRBuilder methods: CreateElementUnorderedAtomicMemSet CreateElementUnorderedAtomicMemMove These mirror the methods that create calls to the regular (non-atomic) memmove and memset intrinsics. llvm-svn: 333588
* [CalledValuePropagation] Just use a sorted vector instead of a set.Benjamin Kramer2018-05-301-9/+11
| | | | | | | | | The set properties are never used, so a vector is enough. No functionality change intended. While there add some std::moves to SparseSolver. llvm-svn: 333582
* [X86][SSE] Pulled out splat detection helper from LowerScalarVariableShift ↵Simon Pilgrim2018-05-301-37/+40
| | | | | | | | (NFCI) Created the IsSplatValue helper from the splat detection code in LowerScalarVariableShift as a first NFC step towards improving support for splat rotations, which is an extension of PR37426. llvm-svn: 333580
* [GlobalISel][Legalizer] LegalizerInfo verifier: check rules cover type indicesRoman Tereshin2018-05-301-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a simple verifier that tracks type indices being touched by legalization rules' builders. Every target will now have an opportunity to call LegalizerInfo::verify(...) at the end of its derived LegalizerInfo's constructor and check there are no obvious mistakes like checking only first type for an opcode that has more than one type index and therefore implicitly declaring any type for the second (and higher) type index legal. The check is only ran in assert builds and should have very minor performance impact in assert builds and none in release builds. This commit does not add LegalizerInfo::verify(...) calls to target-specific legalizers, look for separate commits for that. This commit also doesn't make the verification errors fatal, only produces an error message, look for a later commit that does. Reviewers: aemerson, qcolombet Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D46338 llvm-svn: 333576
* [dsymutil] Escape HTML special characters in plist.Jonas Devlieghere2018-05-301-0/+17
| | | | | | | | | | When printing string in the Plist, we weren't escaping the characters which lead to invalid XML. This patch adds the escape logic to StringExtras. rdar://39785334 llvm-svn: 333565
* [AMDGPU][Waitcnt] Fix build error: unused variable 'SWaitInst'Mark Searles2018-05-301-6/+2
| | | | | | | | | | | | | | https://reviews.llvm.org/rL333556 caused a buildbot failure. See http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/21876/steps/build_Lld/logs/stdio /Users/buildslave/as-bldslv9/lld-x86_64-darwin13/llvm.src/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:2007:10: error: unused variable 'SWaitInst' [-Werror,-Wunused-variable] auto SWaitInst = BuildMI(EntryBB, EntryBB.getFirstNonPHI(), The unused variable was for debugging purposes; removing that piece of code to fix the build. llvm-svn: 333559
* AMDGPU: Use better alignment for kernarg loweringMatt Arsenault2018-05-302-17/+22
| | | | | | | | | | This was just emitting loads with the ABI alignment for the raw type. The true alignment is often better, especially when an illegal vector type was scalarized. The better alignment allows using a scalar load more often. llvm-svn: 333558
* [ValueTracking] Fix endless recursion in isKnownNonZero()Karl-Johan Karlsson2018-05-301-4/+5
| | | | | | | | | | | | | | | | | | | | | Summary: The isKnownNonZero() function have checks that abort the recursion when it reaches the specified max depth. However one of the recursive calls was placed before the max depth check was done, resulting in a endless recursion that eventually triggered a segmentation fault. Fixed the problem by moving the max depth check above the first recursive call. Reviewers: Prazek, nlopes, spatel, craig.topper, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, bjope, llvm-commits Differential Revision: https://reviews.llvm.org/D47531 llvm-svn: 333557
* [AMDGPU][Waitcnt] Fix handling of loops with many bottom blocksMark Searles2018-05-301-19/+23
| | | | | | | | | | | | | In terms of waitcnt insertion/if necessary, the waitcnt pass forces convergence for a loop. Previously, that kicked if greater than 2 passes over a loop, which doesn't account for loop with many bottom blocks. So, increase the threshold to (n+1), where n is the number of bottom blocks. This gives the pass an opportunity to consider the contribution of each bottom block, to the overall loop, before the forced convergence potentially kicks in. Differential Revision: https://reviews.llvm.org/D47488 llvm-svn: 333556
* [X86] Lowering FMA intrinsics to native IR (LLVM part)Gabor Buella2018-05-302-20/+101
| | | | | | | | | | | | | | | | | | | | | | | | Support for Clang lowering of fused intrinsics. This patch: 1. Removes bindings to clang fma intrinsics. 2. Introduces new LLVM unmasked intrinsics with rounding mode: int_x86_avx512_vfmadd_pd_512 int_x86_avx512_vfmadd_ps_512 int_x86_avx512_vfmaddsub_pd_512 int_x86_avx512_vfmaddsub_ps_512 supported with a new intrinsic type (INTR_TYPE_3OP_RM). 3. Introduces new x86 fmaddsub/fmsubadd folding. 4. Introduces new tests for code emitted by sequentions introduced in Clang part. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper, RKSimon Differential Revision: https://reviews.llvm.org/D47443 llvm-svn: 333554
* [AliasSet] Teach the alias set how to handle atomic memcpy/memmove/memsetDaniel Neilson2018-05-301-8/+11
| | | | | | | | | Summary: The atomic variants of the memcpy/memmove/memset intrinsics can be treated the same was as the regular forms, with respect to aliasing. Update the AliasSetTracker to treat the atomic forms the same was as the regular forms. llvm-svn: 333551
* [InstCombine, ARM, AArch64] Convert table lookup to shuffle vectorAlexandros Lamprineas2018-05-301-0/+46
| | | | | | | | | | | Turning a table lookup intrinsic into a shuffle vector instruction can be beneficial. If the mask used for the lookup is the constant vector {7,6,5,4,3,2,1,0}, then the back-end generates byte reverse instructions instead. Differential Revision: https://reviews.llvm.org/D46133 llvm-svn: 333550
* [ARM] Remove code handling ADDC/ADDE/SUBC/SUBEAmaury Sechet2018-05-301-30/+0
| | | | | | | | | | | | Summary: This code is now dead as the ARM backend uses ADDCARRY/SUBCARRY/SETCCCARRY . Reviewers: rogfer01, efriedma, rengolin, javed.absar Subscribers: kristof.beyls, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D47413 llvm-svn: 333544
* [Hexagon] Use vector align-left when shift amount fits in 3 bitsKrzysztof Parzyszek2018-05-301-6/+11
| | | | | | | This saves an instruction because for align-right the shift amount would need to be put in a register first. llvm-svn: 333543
* [mips] Correct the definition of CTC2/CFC2Simon Dardis2018-05-301-8/+6
| | | | llvm-svn: 333542
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