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* [InstCombine] allow icmp-xor folds for vectors (PR33138)Sanjay Patel2017-05-231-5/+9
| | | | | | | | | This fixes the first part of: https://bugs.llvm.org/show_bug.cgi?id=33138 More work is needed for the bitcasted variant. llvm-svn: 303660
* AMDGPU: Fold CI-specific complex SMRD patterns into existing complex patternsMarek Olsak2017-05-234-51/+18
| | | | | | | | | | | | This is just a cleanup. Also, it adds checking that ByteCount is aligned to 4. Reviewers: arsenm, nhaehnle, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28994 llvm-svn: 303658
* Commit AttributeList change that was supposed to be part of r303654Reid Kleckner2017-05-231-2/+2
| | | | llvm-svn: 303656
* [RuntimeDyld, PowerPC] Fix regression from r303637Ulrich Weigand2017-05-231-7/+9
| | | | | | | | | | | | | | Actually, to identify external symbols, we need to check for *either* non-null Value.SymbolName *or* a SymType of Symbol::ST_Unknown. The former may happen for symbols not known to the JIT at all (e.g. defined in a native library), while the latter happens for symbols known to the JIT, but defined in a different module. Fixed several regressions on big-endian ppc64. llvm-svn: 303655
* [IR] Switch AttributeList to use an array for O(1) accessReid Kleckner2017-05-237-288/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change, AttributeLists stored a pair of index and AttributeSet. This is memory efficient if most arguments do not have attributes. However, it requires doing a search over the pairs to test an argument or function attribute. Profiling shows that this loop was 0.76% of the time in 'opt -O2' of sqlite3.c, because LLVM constantly tests values for nullability. This was worth about 2.5% of mid-level optimization cycles on the sqlite3 amalgamation. Here are the full perf results: https://reviews.llvm.org/P7995 Here are just the before and after cycle counts: ``` $ perf stat -r 5 ./opt_before -O2 sqlite3.bc -o /dev/null 13,274,181,184 cycles # 3.047 GHz ( +- 0.28% ) $ perf stat -r 5 ./opt_after -O2 sqlite3.bc -o /dev/null 12,906,927,263 cycles # 3.043 GHz ( +- 0.51% ) ``` This patch *does not* change the indices used to query attributes, as requested by reviewers. Tracking whether an index is usable for array indexing is a huge pain that affects many of the internal APIs, so it would be good to come back later and do a cleanup to remove this internal adjustment. Reviewers: pete, chandlerc Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D32819 llvm-svn: 303654
* [AMDGPU] Convert shl (add) into add (shl)Stanislav Mekhanoshin2017-05-232-2/+43
| | | | | | | | | | | shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1) This allows to fold a constant into an address in some cases as well as to eliminate second shift if the expression is used as an address and second shift is a result of a GEP. Differential Revision: https://reviews.llvm.org/D33432 llvm-svn: 303641
* Revert "Make TypeSerializer's StringMap use the same allocator."Zachary Turner2017-05-232-13/+32
| | | | | | | | This reverts commit e34ccb7b57da25cc89ded913d8638a2906d1110a. This is causing failures on the ASAN bots. llvm-svn: 303640
* [mips] Remove unused class field. NFCSimon Atanasyan2017-05-232-5/+0
| | | | llvm-svn: 303639
* [mips] Change type of MipsSubtarget ctor arguments s/std::string/StringRef/. NFCSimon Atanasyan2017-05-232-5/+4
| | | | llvm-svn: 303638
* [RuntimeDyld, PowerPC] Fix check for external symbols when detecting ↵Ulrich Weigand2017-05-231-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | reloction overflow The PowerPC part of processRelocationRef currently assumes that external symbols can be identified by checking for SymType == SymbolRef::ST_Unknown. This is actually incorrect in some cases, causing relocation overflows to be mis-detected. The correct check is to test whether Value.SymbolName is null. Includes test case. Note that it is a bit tricky to replicate the exact condition that triggers the bug in a test case. The one included here seems to fail reliably (before the fix) across different operating system versions on Power, but it still makes a few assumptions (called out in the test case comments). Also add ppc64le platform name to the supported list in the lit.local.cfg files for the MCJIT and OrcMCJIT directories, since those tests were currently not run at all. Fixes PR32650. Reviewer: hfinkel Differential Revision: https://reviews.llvm.org/D33402 llvm-svn: 303637
* [JumpThreading] Safely replace uses of conditionAnna Thomas2017-05-232-2/+57
| | | | | | | | | | | | | | | | | | | | | | This patch builds over https://reviews.llvm.org/rL303349 and replaces the use of the condition only if it is safe to do so. We should not blindly RAUW the condition if experimental.guard or assume is a use of that condition. This is because LVI may have used the guard/assume to identify the value of the condition, and RUAWing will fold the guard/assume and uses before the guards/assumes. Reviewers: sanjoy, reames, trentxintong, mkazantsev Reviewed by: sanjoy, reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33257 llvm-svn: 303633
* [RuntimeDyld, PowerPC] Fix relocation detection overflowUlrich Weigand2017-05-231-8/+8
| | | | | | | | | | | | | | | | Code in RuntimeDyldELF currently uses 32-bit temporaries to detect whether a PPC64 relocation target is out of range. This is incorrect, and can mis-detect overflow where the distance between relocation site and target is close to a multiple of 4GB. Fixed by using 64-bit temporaries. Noticed while debugging PR32650. Reviewer: hfinkel Differential Revision: https://reviews.llvm.org/D33403 llvm-svn: 303632
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-2313-64/+552
| | | | | | | | | | | | | | | Summary: Added separate pseudo and real instruction for GFX9 SDWA instructions. Currently supports only in assembler. Depends D32493 Reviewers: vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D33132 llvm-svn: 303620
* [AArch64] Make instruction fusion more aggressive. Florian Hahn2017-05-233-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch makes instruction fusion more aggressive by * adding artificial edges between the successors of FirstSU and SecondSU, similar to BaseMemOpClusterMutation::clusterNeighboringMemOps. * updating PostGenericScheduler::tryCandidate to keep clusters together, similar to GenericScheduler::tryCandidate. This change increases the number of AES instruction pairs generated on Cortex-A57 and Cortex-A72. This doesn't change code at all in most benchmarks or general code, but we've seen improvement on kernels using AESE/AESMC and AESD/AESIMC. Reviewers: evandro, kristof.beyls, t.p.northover, silviu.baranga, atrick, rengolin, MatzeB Reviewed By: evandro Subscribers: aemerson, rengolin, MatzeB, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33230 llvm-svn: 303618
* [GlobalISel][X86] G_LOAD/G_STORE vec256/512 supportIgor Breger2017-05-233-0/+38
| | | | | | | | | | | | | | Summary: mark G_LOAD/G_STORE vec256/512 legal for AVX/AVX512. Implement instruction selection. Reviewers: zvi, guyblank Reviewed By: zvi Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33268 llvm-svn: 303617
* [KnownBits] Use !hasConflict() in asserts in place of Zero & One == 0 or ↵Craig Topper2017-05-232-33/+33
| | | | | | similar. NFC llvm-svn: 303614
* [LV] Report multiple reasons for not vectorizing under allowExtraAnalysisAyal Zaks2017-05-231-20/+42
| | | | | | | | | | | | | | | | | | | | The default behavior of -Rpass-analysis=loop-vectorizer is to report only the first reason encountered for not vectorizing, if one is found, at which time the vectorizer aborts its handling of the loop. This patch allows multiple reasons for not vectorizing to be identified and reported, at the potential expense of additional compile-time, under allowExtraAnalysis which can currently be turned on by Clang's -fsave-optimization-record and opt's -pass-remarks-missed. Removed from LoopVectorizationLegality::canVectorize() the redundant checking and reporting if we CantComputeNumberOfIterations, as LAI::canAnalyzeLoop() also does that. This redundancy is caught by a lit test once multiple reasons are reported. Patch initially developed by Dror Barak. Differential Revision: https://reviews.llvm.org/D33396 llvm-svn: 303613
* libDebugInfo: Support symbolizing using DWP filesDavid Blaikie2017-05-232-13/+44
| | | | llvm-svn: 303609
* [AArch64] Fix PRR33100.Akira Hatanaka2017-05-231-7/+10
| | | | | | | | | | | | | This commit fixes a bug introduced in r301019 where optimizeLogicalImm would replace a logical node's immediate operand that was CSE'd and was also an operand of another node. This commit fixes the bug by replacing the logical node instead of its immediate operand. rdar://problem/32295276 llvm-svn: 303607
* Added LLVM_FALLTHROUGH to address gcc warning: this statement may fall through.Galina Kistanova2017-05-231-0/+4
| | | | llvm-svn: 303597
* Added LLVM_FALLTHROUGH to address gcc warning: this statement may fall through.Galina Kistanova2017-05-231-0/+1
| | | | llvm-svn: 303595
* FIX: Remove debugging assert left in previous commitDavid Blaikie2017-05-231-1/+0
| | | | | | Sorry for the bot noise. llvm-svn: 303592
* libDebugInfo: Avoid independently parsing the same .dwo file for two ↵David Blaikie2017-05-232-27/+38
| | | | | | | | | separate CUs residing there NFC, just an optimization. Will be building on this for DWP support shortly. llvm-svn: 303591
* Support for taking the max of module flags when linking, use for PIE/PICTeresa Johnson2017-05-233-4/+24
| | | | | | | | | | | | | | | | | | | | | | Summary: Add Max ModFlagBehavior, which can be used to take the max of two module flag values when merging modules. Use it for the PIE and PIC levels. This avoids an error when we try to import from a module built -fpic into a module built -fPIC, for example. For both PIE and PIC levels, this will be legal, since the code generation gets more conservative as the level is increased. Therefore we can take the max instead of somehow trying to block importing between modules compiled with different levels. Reviewers: tmsriram, pcc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33418 llvm-svn: 303590
* [NewPM] Fix an innocent but silly typo. Reported by Craig Topper.Davide Italiano2017-05-221-1/+1
| | | | llvm-svn: 303587
* [NewPM] Add a temporary cl::opt() to test NewGVN.Davide Italiano2017-05-221-2/+13
| | | | llvm-svn: 303586
* Added LLVM_FALLTHROUGH to address gcc warning: this statement may fall through.Galina Kistanova2017-05-221-0/+1
| | | | llvm-svn: 303585
* [CodeGen] Fix uninitialized variables exposed by r303084Vitaly Buka2017-05-221-2/+2
| | | | | | | All other calls of analyzeBranch reset PredTBB and PredFBB, so I assume it's expected behavior. llvm-svn: 303581
* InstructionSimplify: don't speculate about Constants changing.Tim Northover2017-05-221-0/+4
| | | | | | | | | | When presented with an icmp/select pair, we can end up asking what would happen if we replaced one constant with another in an instruction. This is a mistake, while non-constant Values could become a constant, constants cannot change and trying to do so can lead to completely invalid IR (a GEP referencing a non-existant field in the original case). llvm-svn: 303580
* Infer relocation model from module flags in relocatable LTO link.Evgeniy Stepanov2017-05-222-9/+17
| | | | | | Fix for PR33096. llvm-svn: 303578
* Implement various flavors of type merging.Zachary Turner2017-05-222-76/+175
| | | | | | | | | | | | | | Previous algotirhm assumed that types and ids are in a single unified stream. For inputs that come from object files, this is the case. But if the input is already a PDB, or is the result of a previous merge, then the types and ids will already have been split up, in which case we need an algorithm that can accept operate on independent streams of types and ids that refer across stream boundaries to each other. Differential Revision: https://reviews.llvm.org/D33417 llvm-svn: 303577
* Make TypeSerializer's StringMap use the same allocator.Zachary Turner2017-05-222-32/+13
| | | | llvm-svn: 303576
* Don't generate line&scope debug info for meta-instructions.Adrian Prantl2017-05-224-9/+10
| | | | | | | | | | | | | | | MachineInstructions that don't generate any code (such as IMPLICIT_DEFs) should not generate any debug info either. Fixes PR33107. https://bugs.llvm.org/show_bug.cgi?id=33107 This reapplies r303566 without any modifications. The stage2 build failures persisted even after reverting this patch, and looking back through history, it looks like these tests are flaky. llvm-svn: 303575
* Fix update VP metadata after inlining for instrumentation PGOTeresa Johnson2017-05-221-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: With instrumentation profiling, when updating the VP metadata after an inline, VP metadata on the inlined copy was inadvertantly having all counts zeroed out. This was causing indirect calls from code inlined during the call step to be marked as cold in the ThinLTO summaries and not imported. The CallerBFI needs to be passed down so that the CallSiteCount can be computed from the profile summary info. With Sample PGO this was working since the count is extracted from the branch weight metadata on the call being inlined (even before we stopped looking at metadata for non-sample PGO in r302844 this largely wasn't working for instrumentation PGO since only promoted indirect calls would be getting inlined and have the metadata). Added an instrumentation PGO test and renamed the sample PGO test. Reviewers: danielcdh, eraman Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D33389 llvm-svn: 303574
* [Hexagon] Fix definitions of vector predicate loads and storesKrzysztof Parzyszek2017-05-221-22/+17
| | | | | | This fixes http://llvm.org/PR33048. llvm-svn: 303572
* [DataLayout] Add llvm_unreachable to the default of a nested switch ↵Craig Topper2017-05-221-1/+1
| | | | | | statement that covers all values given to it by the outer switch. NFC llvm-svn: 303571
* Revert "Don't generate line&scope debug info for meta-instructions."Adrian Prantl2017-05-224-10/+9
| | | | | | This reverts commit r303566 while investigating a stage2 buildbot failure. llvm-svn: 303570
* [AMDGPU] Narrow lshl from 64 to 32 bit if possibleStanislav Mekhanoshin2017-05-221-11/+33
| | | | | | | | | Turn expensive 64 bit shift into 32 bit if shift does not overflow int: shl (ext x) => zext (shl x) Differential Revision: https://reviews.llvm.org/D33367 llvm-svn: 303569
* [PartialInlining] Add internal options to enable partial inlining in pass ↵Xinliang David Li2017-05-222-2/+17
| | | | | | | | | | | pipeline (off by default) 1. Legacy: -mllvm -enable-partial-inlining 2. New: -mllvm -enable-npm-partial-inlining -fexperimental-new-pass-manager Differential Revision: http://reviews.llvm.org/D33382 llvm-svn: 303567
* Don't generate line&scope debug info for meta-instructions.Adrian Prantl2017-05-224-9/+10
| | | | | | | | | | | MachineInstructions that don't generate any code (such as IMPLICIT_DEFs) should not generate any debug info either. Fixes PR33107. https://bugs.llvm.org/show_bug.cgi?id=33107 llvm-svn: 303566
* [DAG] Rework store merge to loop on load candidates. NFCI.Nirav Dave2017-05-221-202/+225
| | | | | | | Continue to consider remaining candidate merges until all possible merges have been considered. llvm-svn: 303560
* [AMDGPU] Fix incorrect register usage tracking in GCNUpwardTrackerValery Pykhtin2017-05-222-62/+86
| | | | | | Differential revision: https://reviews.llvm.org/D33289 llvm-svn: 303548
* [mips] Support micromips attribute passed by front-endSimon Atanasyan2017-05-221-0/+9
| | | | | | | | | This patch adds handling of the `micromips` and `nomicromips` attributes passed by front-end. The patch depends on D33363. Differential revision: https://reviews.llvm.org/D33364 llvm-svn: 303545
* [LoopPredication] NFC. Add extra debug output in case we fail to parse the ↵Artur Pilipenko2017-05-221-1/+3
| | | | | | range check llvm-svn: 303544
* [LoopPredication] NFC. Move a nested struct declaration before the fields, ↵Artur Pilipenko2017-05-221-7/+9
| | | | | | | | clang-format a bit This will simplify the diff for an upcoming review. llvm-svn: 303543
* Re-apply r302416: [ARM] Clear the constant pool cache on explicit .ltorg ↵James Molloy2017-05-222-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | directives Re-applying now that PR32825 which was raised on the commit this fixed up is now known to have also been fixed by this commit. Original commit message: Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 303540
* Re-apply r286006: Fix 24560: assembler does not share constant pool for ↵James Molloy2017-05-221-1/+11
| | | | | | | | | | | | | | | | | same constants Re-applying now that the open bug on this commit, PR32825, is known to be fixed. Original commit message: Summary: This patch returns the same label if the CP entry with the same value has been created. Reviewers: eli.friedman, rengolin, jmolloy Subscribers: majnemer, jmolloy, llvm-commits Differential Revision: https://reviews.llvm.org/D25804 llvm-svn: 303539
* [MIPS] Add support to match more patterns for DINS instructionStrahinja Petrovic2017-05-221-25/+62
| | | | | | | | | This patch adds support for recognizing patterns to match DINS instruction. Differential Revision: https://reviews.llvm.org/D31465 llvm-svn: 303537
* Revert "[ARM] Clear the constant pool cache on explicit .ltorg directives"James Molloy2017-05-222-12/+0
| | | | | | | | This reverts commit r302416. This was a fixup for r286006, which has now been reverted so this doesn't apply (either in concept or in code). This commit itself has no problems, but the underlying issue it was fixing has now disappeared from the codebase. llvm-svn: 303536
* Revert "Fix 24560: assembler does not share constant pool for same constants"James Molloy2017-05-221-11/+1
| | | | | | This reverts commit r286006. It caused PR32825 and wasn't fixed. llvm-svn: 303535
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