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* Remove code to enable execution dependency fix pass on VR256. VR128 is ↵Craig Topper2011-11-161-9/+3
| | | | | | sufficient after r144636. llvm-svn: 144777
* Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.Evan Cheng2011-11-161-2/+1
| | | | llvm-svn: 144776
* Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it whenNick Lewycky2011-11-161-30/+20
| | | | | | looking at the size of the pointee. Fixes PR11390! llvm-svn: 144773
* If the 2addr instruction has other kills, don't move it below any other uses ↵Evan Cheng2011-11-161-2/+7
| | | | | | since we don't want to extend other live ranges. llvm-svn: 144772
* RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE ↵Evan Cheng2011-11-161-1/+1
| | | | | | instructions. rdar://10451185 llvm-svn: 144771
* Process all uses first before defs to accurately capture register liveness. ↵Evan Cheng2011-11-161-7/+13
| | | | | | rdar://10449480 llvm-svn: 144770
* CONCAT_VECTORS can have more than two operands. PR11389.Eli Friedman2011-11-161-22/+12
| | | | llvm-svn: 144768
* Add a couple asserts so it will be easier to debug if we accidentally pass ↵Eli Friedman2011-11-161-0/+4
| | | | | | indexed loads/stores to the legalizer. llvm-svn: 144767
* AddressSanitizer, first commit (compiler module only)Kostya Serebryany2011-11-163-0/+967
| | | | llvm-svn: 144758
* test commit to verify that commit access works (added blank line)Kostya Serebryany2011-11-161-0/+1
| | | | llvm-svn: 144748
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-163-4/+4
| | | | llvm-svn: 144747
* Fix SCEV overly optimistic back edge taken count for multi-exit loops.Andrew Trick2011-11-161-9/+22
| | | | | | Fixes PR11375: Different results for 'clang++ huh.cpp'... llvm-svn: 144746
* Add FIXME comment.Chad Rosier2011-11-161-0/+2
| | | | llvm-svn: 144743
* Enable -widen-vmovs by default.Jakob Stoklund Olesen2011-11-151-1/+1
| | | | | | | | | | | This will widen 32-bit register vmov instructions to 64-bit when possible. The 64-bit vmovd instructions can then be translated to NEON vorr instructions by the execution dependency fix pass. The copies are only widened if they are marked as clobbering the whole D-register. llvm-svn: 144734
* Stabilize the output of the dwarf accelerator tables. Fixes a comparisonEric Christopher2011-11-151-2/+11
| | | | | | failure during bootstrap with it turned on. llvm-svn: 144731
* GEPs with all zero indices are trivially coalesced by fast-isel. For example,Chad Rosier2011-11-151-0/+5
| | | | | | | | | | | | | %arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0 %arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134 Prior to this commit, the GEP instruction that defines %arrayidx136 thought that %arrayidx135 was a trivial kill. The GEP that defines %arrayidx135 doesn't generate any code and thus %M0 gets folded into the second GEP. Thus, we need to look through GEPs with all zero indices. rdar://10443319 llvm-svn: 144730
* ARM assembly parsing for register range syntax for VLD/VST register lists.Jim Grosbach2011-11-151-2/+34
| | | | | | | | | | | | | | | | For example, vld1.f64 {d2-d5}, [r2,:128]! Should be equivalent to: vld1.f64 {d2,d3,d4,d5}, [r2,:128]! It's not documented syntax in the ARM ARM, but it is consistent with what's accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to support. rdar://10451128 llvm-svn: 144727
* ARM assembly parsing for data type suffices on NEON VMOV aliases.Jim Grosbach2011-11-152-0/+21
| | | | llvm-svn: 144722
* Fix MSVC warnings by adding a cast. Nadav Rotem2011-11-151-4/+4
| | | | llvm-svn: 144721
* AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the ↵Nadav Rotem2011-11-151-48/+85
| | | | | | | | vbroadcast code. llvm-svn: 144720
* ARM assembly parsing two operand forms for shift instructions.Jim Grosbach2011-11-151-0/+10
| | | | llvm-svn: 144713
* ARM VFP assembly parsing for VADD and VSUB two-operand forms.Jim Grosbach2011-11-151-0/+10
| | | | llvm-svn: 144710
* ARM accept an immediate offset in memory operands w/o the '#'.Jim Grosbach2011-11-151-3/+6
| | | | llvm-svn: 144709
* Added custom lowering for load->dec->store sequence in x86 when the EFLAGS ↵Pete Cooper2011-11-153-2/+66
| | | | | | | | | | | | registers is used by later instructions. Only done for DEC64m right now. Fixes <rdar://problem/6172640> llvm-svn: 144705
* ARM enclosing curly braces optional on one-register VLD/VST instruction lists.Jim Grosbach2011-11-151-2/+23
| | | | | | | | 'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]' rdar://10450488. llvm-svn: 144701
* ARM size suffix on VFP single-precision 'vmov' is optional.Jim Grosbach2011-11-151-0/+5
| | | | | | rdar://10435114 llvm-svn: 144698
* Insert modified DBG_VALUE into LiveDbgValueMap. Devang Patel2011-11-151-1/+1
| | | | llvm-svn: 144696
* Fix typo.Jim Grosbach2011-11-151-1/+1
| | | | llvm-svn: 144695
* ARM alternate size suffices for VTRN instructions.Jim Grosbach2011-11-151-0/+16
| | | | | | rdar://10435076 llvm-svn: 144694
* Fix a misplaced paren bug.Owen Anderson2011-11-151-1/+1
| | | | llvm-svn: 144692
* ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach2011-11-151-0/+11
| | | | | | Yet more of rdar://10435076. llvm-svn: 144691
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+6
| | | | | | rdar://10449856. llvm-svn: 144689
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+4
| | | | | | Ongoing rdar://10435114. llvm-svn: 144688
* Thumb2 two-operand 'mul' instruction wide encoding parsing.Jim Grosbach2011-11-152-0/+19
| | | | | | rdar://10449724 llvm-svn: 144684
* Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and ↵Owen Anderson2011-11-152-8/+66
| | | | | | VMOVv4f32. llvm-svn: 144683
* Thumb2 assembly parsing for mul.w in IT block fix.Jim Grosbach2011-11-151-0/+1
| | | | | | | | | | When the 3rd operand is not a low-register, and the first two operands are the same low register, the parser was incorrectly trying to use the 16-bit instruction encoding. rdar://10449281 llvm-svn: 144679
* StringRefize and simplify.Benjamin Kramer2011-11-152-13/+10
| | | | llvm-svn: 144675
* We currently use a callback to handle an IL pass deleting a BB that stillRafael Espindola2011-11-151-0/+12
| | | | | | | | | | | has a reference to it. Unfortunately, that doesn't work for codegen passes since we don't get notified of MBB's being deleted (the original BB stays). Use that fact to our advantage and after printing a function, check if any of the IL BBs corresponds to a symbol that was not printed. This fixes pr11202. llvm-svn: 144674
* Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bitAkira Hatanaka2011-11-152-18/+24
| | | | | | registers and instructions when ABI is N64. llvm-svn: 144666
* Set nomacro before emitting the sequence of instructions that set global pointerAkira Hatanaka2011-11-151-3/+2
| | | | | | register. llvm-svn: 144665
* Simplify function PassByValArg64.Akira Hatanaka2011-11-151-14/+18
| | | | llvm-svn: 144664
* Remove function printMipsSymbolRef.Akira Hatanaka2011-11-151-35/+0
| | | | llvm-svn: 144663
* Remove Value::getNameStr. It has been deprecated for a while and provides no ↵Benjamin Kramer2011-11-151-4/+0
| | | | | | additional value over getName(). llvm-svn: 144657
* Missed some users of Value::getNameStr.Benjamin Kramer2011-11-151-4/+2
| | | | llvm-svn: 144656
* Delete files.Akira Hatanaka2011-11-152-137/+0
| | | | llvm-svn: 144655
* Remove MipsMCSymbolRefExpr.Akira Hatanaka2011-11-152-2/+0
| | | | llvm-svn: 144654
* ARM parsing datatype suffix variants for register-writeback VLD1/VST1 ↵Jim Grosbach2011-11-151-0/+78
| | | | | | | | instructions. rdar://10435076 llvm-svn: 144650
* Tidy up. 80 columns.Jim Grosbach2011-11-155-28/+34
| | | | llvm-svn: 144649
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-1522-61/+63
| | | | llvm-svn: 144648
* Twinify GraphWriter a little bit.Benjamin Kramer2011-11-155-11/+11
| | | | llvm-svn: 144647
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