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* [LoopSimplifyCFG] Update MemorySSA after r353911.Alina Sbirlea2019-02-211-10/+17
| | | | | | | | | | | | | | | | | Summary: MemorySSA is not properly updated in LoopSimplifyCFG after recent changes. Use SplitBlock utility to resolve that and clear all updates once handleDeadExits is finished. All updates that follow are removal of edges which are safe to handle via the removeEdge() API. Also, deleting dead blocks is done correctly as is, i.e. delete from MemorySSA before updating the CFG and DT. Reviewers: mkazantsev, rtereshin Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58524 llvm-svn: 354613
* [EarlyCSE] Cleanup deadcode. [NFCI]Alina Sbirlea2019-02-211-5/+1
| | | | | | | | | | | | | | Summary: Cleanup nop assignments. Reviewers: george.burgess.iv, davide Subscribers: sanjoy, jlebar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58308 llvm-svn: 354612
* [Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trapKrzysztof Parzyszek2019-02-213-1/+38
| | | | | | | | | The trap instruction is intercepted by various runtime environments, and instead of a crash it creates confusion. This reapplies r354606 with a fix. llvm-svn: 354611
* Revert r354606, it breaks asan testsKrzysztof Parzyszek2019-02-213-38/+1
| | | | llvm-svn: 354609
* [Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trapKrzysztof Parzyszek2019-02-213-1/+38
| | | | | | | The trap instruction is intercepted by various runtime environments, and instead of a crash it creates confusion. llvm-svn: 354606
* [AMDGPU] remove unused AssemblerPredicatesMark Searles2019-02-211-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | An internal build is hitting asserts complaining about too many subtarget features: llvm/utils/TableGen/Types.cpp:42: const char* llvm::getMinimalTypeForEnumBitfield(uint64_t): Assertion `MaxIndex <= 64 && "Too many bits"' failed. llvm/utils/TableGen/AsmMatcherEmitter.cpp:1476: void {anonymous}::AsmMatcherInfo::buildInfo(): Assertion `SubtargetFeatures.size() <= 64 && "Too many subtarget features!"' failed. The short-term solution is to remove a few unused AssemblerPredicates to get under the limit. The long-term solution seems to be to revisit these asserts. E.g., rather than hardcoded '64', use the standard sized std::bitset like the other places that track subtarget features. Differential Revision: https://reviews.llvm.org/D58516 llvm-svn: 354604
* [WebAssembly] Don't create MSSymbolWasm object for non-symbolsSam Clegg2019-02-211-9/+4
| | | | | | | | | | | `__linear_memory` and `__indirect_function_table` are both generated as imports in wasm object files but are actually symbols and don't appear in any symbols table or relocation entry. Indeed we don't have any symbol type to meaningfully represent either of them. Differential Revision: https://reviews.llvm.org/D58487 llvm-svn: 354599
* [DAGCombiner] prevent infinite looping by truncating 'and' (PR40793)Sanjay Patel2019-02-211-2/+3
| | | | | | | | | | | | | | This fold can occur during legalization, so it can fight with promotion to the larger type. It apparently takes a special sequence and subtarget to avoid more basic simplifications that would hide the problem. But there's a bigger question raised here: why does distributeTruncateThroughAnd() even exist? It duplicates functionality from a more minimal pattern that we already have. But getting rid of this function requires some preliminary steps. https://bugs.llvm.org/show_bug.cgi?id=40793 llvm-svn: 354594
* AMDGPU/GlobalISel: Make phis legalMatt Arsenault2019-02-211-0/+13
| | | | llvm-svn: 354592
* RegBankSelect: Allow targets to introduce control flow for mappingMatt Arsenault2019-02-211-0/+13
| | | | | | | | | | | | | For AMDGPU, if an operand requires an SGPR but is only available as a VGPR, a loop needs to be introduced to execute the instruction with each unique combination of values across all lanes. The rest of the instructions in the block will be moved to a new block following the loop. Check if the next instruction's parent changed, and update the iterators and insertion block if this happened. Tests will be included in a future patch. llvm-svn: 354591
* [X86] Fix copy-paste error in @ccz flag.Nirav Dave2019-02-211-1/+1
| | | | | | @ccz operand should be equivalent to @cce. llvm-svn: 354588
* AMDGPU/GlobalISel: Fix bit count ops for non-power-of-2 typesMatt Arsenault2019-02-211-1/+3
| | | | llvm-svn: 354587
* [RISCV][NFC] IsEligibleForTailCallOptimization -> ↵Alex Bradbury2019-02-212-9/+8
| | | | | | | | isEligibleForTailCallOptimization Also clang-format the modified hunks. llvm-svn: 354584
* [RISCV] Add implied zero offset load/store alias patternsAlex Bradbury2019-02-214-0/+81
| | | | | | | | | | Allow load/store instructions with implied zero offset for compatibility with GNU assembler. Differential Revision: https://reviews.llvm.org/D57141 Patch by James Clarke. llvm-svn: 354581
* [InferAddressSpaces] Fix fallthrough errorJoey Gouly2019-02-211-0/+1
| | | | llvm-svn: 354580
* [ARM GlobalISel] Support G_FRAME_INDEX for Thumb2Diana Picus2019-02-212-2/+5
| | | | | | Same as arm mode. llvm-svn: 354579
* Re-land part of r354244 "[DAGCombiner] Eliminate dead stores to stack."Clement Courbet2019-02-213-10/+44
| | | | | | This part introduces the lifetime node. llvm-svn: 354578
* [InferAddressSpaces] Fix crash on select of non-ptr operandsJoey Gouly2019-02-211-2/+5
| | | | | | | | | Check the operands of a select are pointers, to determine if it is an address expression or not. https://reviews.llvm.org/D58226 llvm-svn: 354576
* [X86][SSE] combineX86ShufflesRecursively - moved to generic op input index ↵Simon Pilgrim2019-02-211-7/+3
| | | | | | | | lookup. NFCI. We currently bail if the target shuffle decodes to more than 2 input vectors, this change alters the input index to work for any number of inputs for when we drop that requirement. llvm-svn: 354575
* [yaml2obj][obj2yaml] - Support SHT_GNU_verdef (.gnu.version_d) section.George Rimar2019-02-211-0/+22
| | | | | | | | | | This patch adds support for parsing/dumping the .gnu.version section. Description of the section is: https://refspecs.linuxfoundation.org/LSB_1.3.0/gLSB/gLSB/symverdefs.html Differential revision: https://reviews.llvm.org/D58437 llvm-svn: 354574
* Revert 354564: [ARM] Add some missing thumb1 opcodes to enable peephole ↵David Green2019-02-211-54/+12
| | | | | | | | | optimisation of CMPs I believe it's causing bootstrap failures for A32 code. I'll take a look at what's wrong. llvm-svn: 354569
* [yaml2obj]Allow symbol Index field to take values lower than SHN_LORESERVEJames Henderson2019-02-211-3/+0
| | | | | | | | | | | | | | | | | | | | In order to test tool handling of invalid section indexes, I need to create an object containing such an invalid section index. I could create a hex-edited binary, but having the ability to use yaml2obj is preferable. Prior to this change, yaml2obj would reject any explicit section indexes less than SHN_LORESERVE. This patch changes it to allow any value. I had to change the test to use llvm-readelf instead of llvm-readobj, because llvm-readobj does not like invalid section indexes. I've also expanded the test to show that the most common SHN_* values are accepted (SHN_UNDEF, SHN_ABS, SHN_COMMON). Reviewed by: grimar, jakehehrlich Differential Revision: https://reviews.llvm.org/D58445 llvm-svn: 354566
* [AArch64] Print instruction before atomic semantic annotationsDavid Spickett2019-02-211-5/+6
| | | | | | | | | | | | | | | | | Commit r353303 added annotations when acquire semantics were dropped from an instruction. printAnnotation was called before printInstruction. So if you didn't set a separate comment output stream you got <comment><instr> instead of <instr><comment> as expected. To fix this move the new printAnnotation to after the instruction is printed. Differential Revision: https://reviews.llvm.org/D58059 llvm-svn: 354565
* [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPsDavid Green2019-02-211-12/+54
| | | | | | | | | This adds a number of missing Thumb1 opcodes so that the peephole optimiser can remove redundant CMP instructions. Differential Revision: https://reviews.llvm.org/D57833 llvm-svn: 354564
* [ObjectYAML] Support SHT_MIPS_DWARF section type flagFangrui Song2019-02-212-1/+2
| | | | | | | Also reorder SHT_MIPS_DWARF and SHT_MIPS_ABIFLAGS in Object/ELF.cpp. The test will be added by D58457. llvm-svn: 354563
* [ARM] Negative constants mishandled in ARM CGPSam Parker2019-02-211-5/+5
| | | | | | | | | | | | | During type promotion, sometimes we convert negative an add with a negative constant into a sub with a positive constant. The loop that performs this transformation has two issues: - it iterates over a set, causing non-determinism. - it breaks, instead of continuing, when it finds the first non-negative operand. Differential Revision: https://reviews.llvm.org/D58452 llvm-svn: 354557
* [DebugInfo] Prep llvm-dwarfdump for typed DW5 ops.Markus Lavin2019-02-215-13/+60
| | | | | | | | | | | Adds llvm-dwarfdump support for pretty printing Dwarf5 expressions ops that reference a base type (right now only DW_OP_convert is added). Includes verification to verify that the ops operand is actually a DW_TAG_base_type DIE. Differential Revision: https://reviews.llvm.org/D58442 llvm-svn: 354552
* [LoopSimplifyCFG] Add missing MSSA edge deletionMax Kazantsev2019-02-211-0/+2
| | | | | | | | When we create fictive switch in preheader, we should take care about MSSA and delete edge between old preheader and header. llvm-svn: 354547
* [WebAssembly] Default to something reasonable in WebAssemblyAddMissingPrototypesSam Clegg2019-02-211-7/+13
| | | | | | | | | | | | | | | | | | Previously if we couldn't derive a prototype for a "no-prototype" function from C we would leave it as is: void foo(...) With this change we instead give is an empty signature and remove the "no-prototype" attribute. This fixes the current wasm waterfall test failure. Tags: #llvm Differential Revision: https://reviews.llvm.org/D58488 llvm-svn: 354544
* [AMDGPU] fix commuted case of sub combineStanislav Mekhanoshin2019-02-211-5/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D58481 llvm-svn: 354543
* [Inliner] Pass nullptr for the ORE param of getInlineCost if RemarkEnabledWei Mi2019-02-212-3/+10
| | | | | | | | | | | | | | | | | | | is false. Right now for inliner and partial inliner, we always pass the address of a valid ORE object to getInlineCost even if RemarkEnabled is false because of no -Rpass is specified. Since ComputeFullInlineCost will be set to true if ORE is non-null in getInlineCost, this introduces the problem that in getInlineCost we cannot return early even if we already know the cost is definitely higher than the threshold. It is a general problem for compile time. This patch fixes that by pass nullptr as the ORE argument if RemarkEnabled is false. Differential Revision: https://reviews.llvm.org/D58399 llvm-svn: 354542
* Add skipFunction to PostRA machine sinking pass.Xin Tong2019-02-211-0/+3
| | | | | | | | | | | | | | Summary: Add skipFunction to PostRA machine sinking pass. Reviewers: junbuml Subscribers: arsenm, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57847 llvm-svn: 354541
* Revert "[AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR"Amara Emerson2019-02-212-153/+0
| | | | | | This reverts r354521 because it broke the bots, but passes on Darwin somehow. llvm-svn: 354532
* [WebAssembly] Don't error on conflicting uses of prototype-less functionsSam Clegg2019-02-201-6/+8
| | | | | | | | | | | | | | | | When we can't determine with certainty the signature of a function import we pick the fist signature we find rather than error'ing out. The resulting program might not do what is expected since we might pick the wrong signature. However since undefined behavior in C to use the same function with different signatures this seems better than refusing to compile such programs. Fixes PR40472 Differential Revision: https://reviews.llvm.org/D58304 llvm-svn: 354523
* [AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTORAmara Emerson2019-02-202-0/+153
| | | | | | | | | | | | | | This change makes some basic type combinations for G_SHUFFLE_VECTOR legal, and implements them with a very pessimistic TBL2 instruction in the selector. For TBL2, support is also needed to generate constant pool entries and load from them in order to materialize the mask register. Currently supports <2 x s64> and <4 x s32> result types. Differential Revision: https://reviews.llvm.org/D58466 llvm-svn: 354521
* [CGP] match a special-case of unsigned subtract overflowSanjay Patel2019-02-201-0/+5
| | | | | | | This is the 'sub0' (negate) pattern from PR31754: https://bugs.llvm.org/show_bug.cgi?id=31754 llvm-svn: 354519
* [DAGCombine] Generalize Dead Store to overlapping stores.Nirav Dave2019-02-201-14/+17
| | | | | | | | | | | | | | | | | | Summary: Remove stores that are immediately overwritten by larger stores. Reviewers: courbet, rnk Reviewed By: rnk Subscribers: javed.absar, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58467 llvm-svn: 354518
* AMDGPU/GlobalISel: Move SMRD selection logic to TableGenTom Stellard2019-02-204-128/+136
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52922 llvm-svn: 354516
* [SelectionDAG] Teach GetDemandedBits to look at the known zeros of the LHS ↵Craig Topper2019-02-201-3/+7
| | | | | | | | | | | | when handling ISD::AND If the LHS has known zeros, then the RHS immediate mask might have been simplified to remove those bits. This patch adds a call to computeKnownBits to get the known zeroes to handle that possibility. I left an early out to skip the call if all of the demanded bits are set in the mask. Differential Revision: https://reviews.llvm.org/D58464 llvm-svn: 354514
* [SDAG] Support vector UMULO/SMULONikita Popov2019-02-205-19/+91
| | | | | | | | | | | | | | | Second part of https://bugs.llvm.org/show_bug.cgi?id=40442. This adds an extra UnrollVectorOverflowOp() method to SDAG, because the general UnrollOverflowOp() method can't deal with multiple results. Additionally we need to expand UMULO/SMULO during vector op legalization, as it may result in unrolling, which may need additional type legalization. Differential Revision: https://reviews.llvm.org/D57997 llvm-svn: 354513
* [X86] Add more load folding patterns for blend instructions as a follow up ↵Craig Topper2019-02-201-6/+66
| | | | | | | | | | | | | | to r354363. This avoids depending on the peephole pass to do load folding. Also adds some load folding for some insert_subvector patterns that use blend. All of this was found by temporarily adding TB_NO_FORWARD to the blend immediate entries in the load folding tables. I've added -disable-peephole to some of the affected tests from that experiment to ensure we're testing isel patterns. llvm-svn: 354511
* Revert r354498 "[X86] Add test case to show missed opportunity to remove an ↵Craig Topper2019-02-201-7/+3
| | | | | | | | explicit AND on the bit position from BT when it has known zeros." I accidentally committed more than just the test. llvm-svn: 354499
* [X86] Add test case to show missed opportunity to remove an explicit AND on ↵Craig Topper2019-02-201-3/+7
| | | | | | | | | | the bit position from BT when it has known zeros. If the bit position has known zeros in it, then the AND immediate will likely be optimized to remove bits. This can prevent GetDemandedBits from recognizing that the AND is unnecessary. llvm-svn: 354498
* [MCA][Scheduler] Collect resource pressure and memory dependency bottlenecks.Andrea Di Biagio2019-02-203-26/+31
| | | | | | | | | | | | | | | | | | Every cycle, the Scheduler checks if instructions in the ReadySet can be issued to the underlying pipelines. If an instruction cannot be issued because one or more pipeline resources are unavailable, then field Instruction::CriticalResourceMask is updated with the resource identifier of the unavailable resources. If an instruction cannot be promoted from the PendingSet to the ReadySet because of a memory dependency, then field Instruction::CriticalMemDep is updated with the identifier of the dependending memory instruction. Bottleneck information is collected after every cycle for instructions that are waiting to execute. The idea is to help identify causes of bottlenecks; this information can be used in future to implement a bottleneck analysis. llvm-svn: 354490
* [X86][SSE] combineX86ShufflesRecursively - begin generalizing the number of ↵Simon Pilgrim2019-02-201-11/+7
| | | | | | | | shuffle inputs. NFCI. We currently bail if the target shuffle decodes to more than 2 input vectors, this is some initial cleanup that still has the limit but generalizes the opindices to an array that will be necessary when we drop the limit. llvm-svn: 354489
* GlobalISel: Fix fewerElementsVector for ctlz with different result typeMatt Arsenault2019-02-202-3/+7
| | | | | | Also complete the set of related operations. llvm-svn: 354480
* GlobalISel: Implement moreElementsVector for g_insert resultsMatt Arsenault2019-02-202-14/+32
| | | | llvm-svn: 354477
* Re-land the refactoring part of r354244 "[DAGCombiner] Eliminate dead stores ↵Clement Courbet2019-02-202-35/+80
| | | | | | | | to stack." This is an NFC. llvm-svn: 354476
* [Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTENDKrzysztof Parzyszek2019-02-202-0/+7
| | | | llvm-svn: 354473
* [MCA][ResourceManager] Add a table that maps processor resource indices to ↵Andrea Di Biagio2019-02-201-21/+24
| | | | | | | | | | | | processor resource identifiers. This patch adds a lookup table to speed up resource queries in the ResourceManager. This patch also moves helper function 'getResourceStateIndex()' from ResourceManager.cpp to Support.h, so that we can reuse that logic in the SummaryView (and potentially other views in llvm-mca). No functional change intended. llvm-svn: 354470
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