summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Add support to set/get ordering for load/store from the C APIAndrew Wilkins2015-08-021-1/+34
| | | | | | | | | | | | Summary: As per title Reviewers: chandlerc, bogner, majnemer, axw Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11141 llvm-svn: 243847
* Mark CompositeType::getTypeAtIndex as const. NFCCraig Topper2015-08-011-5/+7
| | | | llvm-svn: 243845
* Mark Type::getPointerTo as const. Unfortunately, this requires a const_cast ↵Craig Topper2015-08-011-2/+2
| | | | | | inside, but at least it makes all methods on Type const. NFC llvm-svn: 243844
* Merge the const and non-const Type::getScalarType to a const version that ↵Craig Topper2015-08-011-9/+3
| | | | | | returns a non-const pointer. Since we don't put const on Types all places were already calling the non-const version. llvm-svn: 243843
* De-constify pointers to Type since they can't be modified. NFCCraig Topper2015-08-0126-116/+113
| | | | | | This was already done in most places a while ago. This just fixes the ones that crept in over time. llvm-svn: 243842
* [NVPTX] allow register copy between float and intJingyue Wu2015-08-011-22/+23
| | | | | | | | | | | | | | | Summary: Fixes PR24303. With Bruno's WIP (D11197) on PeepholeOptimizer, across-class register copying (e.g. i32 to f32) becomes possible. Enhance NVPTXInstrInfo::copyPhysReg to handle these cases. Reviewers: jholewinski Subscribers: eliben, jholewinski, llvm-commits, bruno Differential Revision: http://reviews.llvm.org/D11622 llvm-svn: 243839
* Remove trailing whitespace. NFCI.Simon Pilgrim2015-08-011-7/+7
| | | | llvm-svn: 243838
* Use SDValue bool check. NFCI.Simon Pilgrim2015-08-011-20/+10
| | | | llvm-svn: 243837
* [DAGCombiner] Convert constant AND masks to shuffle clear masks down to the ↵Simon Pilgrim2015-08-011-21/+64
| | | | | | | | | | | | | | byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-012-9/+1
| | | | | | | | | | deprecated in C++11 Remove some unnecessary explicit special members in Hexagon that, once removed, allow the other implicit special members to be used without depending on deprecated features. llvm-svn: 243825
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-012-15/+20
| | | | | | deprecated in C++11 llvm-svn: 243824
* WebAssembly: handle more than int32 argument/returnJF Bastien2015-08-014-8/+30
| | | | | | | | | | | | Summary: Also test 64-bit integers, except shifts for now which are broken because isel dislikes the 32-bit truncate that precedes them. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11699 llvm-svn: 243822
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-011-81/+0
| | | | | | | | | | | | deprecated in C++11 Various targets use std::swap on specific MCAsmOperands (ARM and possibly Hexagon as well). It might be helpful to mark those subclasses as final, to ensure that the availability of move/copy operations can't lead to slicing. (same sort of requirements as the non-vitual dtor - protected or a final class) llvm-svn: 243820
* [libFuzzer] more refactoring of the Mutator and adding tests to itKostya Serebryany2015-08-013-26/+133
| | | | llvm-svn: 243818
* [libFuzzer] start refactoring the Mutator and adding tests to itKostya Serebryany2015-08-015-14/+58
| | | | llvm-svn: 243817
* AMDGPU/SI: Add implicit register operands in the correct order.Alex Lorenz2015-07-312-21/+1
| | | | | | | | | | | | | | | | | | This commit fixes a bug in the class 'SIInstrInfo' where the implicit register machine operands were added to a machine instruction in an incorrect order - the implicit uses were added before the implicit defs. I found this bug while working on moving the implicit register operand verification code from the MIR parser to the machine verifier. This commit also makes the method 'addImplicitDefUseOperands' in the machine instruction class public so that it can be reused in the 'SIInstrInfo' class. Reviewers: Matt Arsenault Differential Revision: http://reviews.llvm.org/D11689 llvm-svn: 243799
* MIR Parser: Report an error when a jump table entry is redefined.Alex Lorenz2015-07-311-2/+5
| | | | llvm-svn: 243798
* MIR Parser: Remove unused variable.Alex Lorenz2015-07-311-1/+0
| | | | | | This variable is unused as of r243572. llvm-svn: 243796
* [libFuzzer] limit the size of the inputs printed to stderrKostya Serebryany2015-07-311-4/+10
| | | | llvm-svn: 243795
* [NVPTX] convert pointers in byval kernel arguments to globalJingyue Wu2015-07-311-20/+81
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: For example, in struct S { int *x; int *y; }; __global__ void foo(S s) { int *b = s.y; // use b } "b" is guaranteed to point to global. NVPTX should emit ld.global/st.global for accessing "b". Reviewers: jholewinski Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11505 llvm-svn: 243790
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-07-311-4/+3
| | | | | | deprecated in C++11 llvm-svn: 243788
* WebAssembly: handle `ret void`.JF Bastien2015-07-313-3/+3
| | | | | | | | | | | | | | | Summary: Use -1 as numoperands for the return SDTypeProfile, denoting that return is variadic. Note that the patterns in InstrControl.td still need to match the inputs, so this ins't an "anything goes" variadic on ret! The next step will be to handle other local types (not just int32). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11692 llvm-svn: 243783
* [libFuzzer] make sure that 2-byte arguments of switch() are handled properlyKostya Serebryany2015-07-313-13/+52
| | | | llvm-svn: 243781
* MIR Serialization: Serialize the floating point immediate machine operands.Alex Lorenz2015-07-314-2/+80
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243780
* [dwarfdump] Ignore scattered relocations for mach-o.Frederic Riss2015-07-311-3/+9
| | | | | | | | | | | | | | When encountering a scattered relocation, the code would assert trying to access an unexisting section. I couldn't find a way to expose the result of the processing of a scattered reloc, and I'm really unsure what the right thing to do is. This patch just skips them during the processing in DwarfContext and adds a mach-o file to the tests that exposed the asserting behavior. (This is a new failure that is being exposed by Rafael's recent work on the libObject interfaces. I think the wrong behavior has always happened, but now it's asserting) llvm-svn: 243778
* DI: Remove DW_TAG_arg_variable and DW_TAG_auto_variableDuncan P. N. Exon Smith2015-07-3112-51/+44
| | | | | | | | | | | | | | | | | | | | | | | | Remove the fake `DW_TAG_auto_variable` and `DW_TAG_arg_variable` tags, using `DW_TAG_variable` in their place Stop exposing the `tag:` field at all in the assembly format for `DILocalVariable`. Most of the testcase updates were generated by the following sed script: find test/ -name "*.ll" -o -name "*.mir" | xargs grep -l 'DILocalVariable' | xargs sed -i '' \ -e 's/tag: DW_TAG_arg_variable, //' \ -e 's/tag: DW_TAG_auto_variable, //' There were only a handful of tests in `test/Assembly` that I needed to update by hand. (Note: a follow-up could change `DILocalVariable::DILocalVariable()` to set the tag to `DW_TAG_formal_parameter` instead of `DW_TAG_variable` (as appropriate), instead of having that logic magically in the backend in `DbgVariable`. I've added a FIXME to that effect.) llvm-svn: 243774
* x86: check hasOpaqueSPAdjustment in canRealignStackJF Bastien2015-07-311-4/+6
| | | | | | | | | | | | | | | Summary: @rnk pointed out in [1] that x86's canRealignStack logic should match that in CantUseSP from hasBasePointer. [1]: http://reviews.llvm.org/D11160?id=29713#inline-89350 Reviewers: rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D11377 llvm-svn: 243772
* WebAssembly: handle unused function arguments.JF Bastien2015-07-311-4/+6
| | | | | | | | Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11684 llvm-svn: 243770
* [libFuzzer] record traces from the switch statements only when told to do soKostya Serebryany2015-07-311-0/+1
| | | | llvm-svn: 243768
* New EH representation for MSVC compatibilityDavid Majnemer2015-07-3126-49/+1180
| | | | | | | | | | This introduces new instructions neccessary to implement MSVC-compatible exception handling support. Most of the middle-end and none of the back-end haven't been audited or updated to take them into account. Differential Revision: http://reviews.llvm.org/D11097 llvm-svn: 243766
* DI: Rewrite the DIBuilder local variable APIDuncan P. N. Exon Smith2015-07-311-3/+23
| | | | | | | | | | | | Replace the general `createLocalVariable()` with two more specific functions: `createParameterVariable()` and `createAutoVariable()`, and rewrite the documentation. Besides cleaning up the API, this avoids exposing the fake DWARF tags `DW_TAG_arg_variable` and `DW_TAG_auto_variable` to frontends, and is preparation for removing them completely. llvm-svn: 243764
* WebAssembly: print basic integer assembly.JF Bastien2015-07-316-10/+134
| | | | | | | | | | | | | | | | | | | Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
* [COFF] Consider the ImageBase when reporting section addressesDavid Majnemer2015-07-311-2/+10
| | | | | | This lets us reenable the lld test disabled in r243758. llvm-svn: 243761
* [libFuzzer] support switch interception in dfsan modeKostya Serebryany2015-07-314-4/+41
| | | | llvm-svn: 243760
* [CodeGenPrepare] Compress a pair. No functional change.Benjamin Kramer2015-07-311-7/+3
| | | | llvm-svn: 243759
* [x86] reassociate integer multiplies using machine combiner passSanjay Patel2015-07-311-10/+30
| | | | | | | | | | | | | Add i16, i32, i64 imul machine instructions to the list of reassociation candidates. A new bit of logic is needed to handle integer instructions: they have an implicit EFLAGS operand, so we have to make sure it's dead in order to do any reassociation with integer ops. Differential Revision: http://reviews.llvm.org/D11660 llvm-svn: 243756
* [COFF] Return symbol VAs instead of RVAs for PE filesReid Kleckner2015-07-311-0/+8
| | | | | | | | This makes llvm-nm consistent with binutils nm on executables and DLLs. For a vanilla hello world executable, the address of main should include the default image base of 0x400000. llvm-svn: 243755
* [AArch64] Favor extended reg patterns for subGeoff Berry2015-07-311-0/+2
| | | | | | | | | | | | | | Summary: Favor the extended reg patterns over the shifted reg patterns that match only the operand shift and not the full sign/zero extend and shift. Reviewers: jmolloy, t.p.northover Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11569 llvm-svn: 243753
* [CaptureTracker] Provide an ordered basic block to PointerMayBeCapturedBeforeBruno Cardoso Lopes2015-07-315-72/+123
| | | | | | | | | | | | | | | | | | This patch is a follow up from r240560 and is a step further into mitigating the compile time performance issues in CaptureTracker. By providing the CaptureTracker with a "cached ordered basic block" instead of computing it every time, MemDepAnalysis can use this cache throughout its calls to AA->callCapturesBefore, avoiding to recompute it for every scanned instruction. In the same testcase used in r240560, compile time is reduced from 2min to 30s. This also fixes PR22348. rdar://problem/19230319 Differential Revision: http://reviews.llvm.org/D11364 llvm-svn: 243750
* [regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when ↵Daniel Sanders2015-07-311-0/+8
| | | | | | | | | | | | | | | | | | | | | hoisting def's upwards. Summary: This prevents vreg260 and D7 from being merged in: %vreg260<def> = LDC1 ... JAL <ga:@sin>, <regmask ... list not containing D7 ...> %D7<def> = COPY %vreg260; ... Doing so is not valid because the JAL clobbers the D7. This fixes the almabench regression in the LLVM 3.7.0 release branch. Reviewers: MatzeB Subscribers: MatzeB, qcolombet, hans, llvm-commits Differential Revision: http://reviews.llvm.org/D11649 llvm-svn: 243745
* Refactor: Simplify boolean conditional return statements in lib/Target/NVPTXJingyue Wu2015-07-313-37/+15
| | | | | | | | | | | | Summary: Use clang-tidy to simplify boolean conditional return statements Reviewers: rafael, echristo, chandlerc, bkramer, craig.topper, dexonsmith, chapuni, eliben, jingyue, jholewinski Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D9983 llvm-svn: 243734
* AMDGPU: Fix v16i32 to v16i8 truncstoreMatt Arsenault2015-07-311-0/+1
| | | | llvm-svn: 243731
* [libFuzzer] trace switch statements and apply mutations based on the ↵Kostya Serebryany2015-07-315-4/+111
| | | | | | expected case values llvm-svn: 243726
* ELFYAML: Enable parsing of EM_AMDGPUTom Stellard2015-07-311-0/+1
| | | | | | | | Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11263 llvm-svn: 243724
* AMDGPU/SI: Set DwarfRegNumMatt Arsenault2015-07-311-6/+14
| | | | | | | This requires a fix in tablegen for the cast<int> from bits<16> to work in the list initializer. llvm-svn: 243723
* TableGen: Support folding casts from bits to intMatt Arsenault2015-07-311-0/+8
| | | | | | | | | | | | | | | This is to fix an incorrect error when trying to initialize DwarfNumbers with a !cast<int> of a bits initializer. getValuesAsListOfInts("DwarfNumbers") would not see an IntInit and instead the cast, so would give up. It seems likely that this could be generalized to attempt the convertInitializerTo for any type. I'm not really sure why the existing code seems to special case the string cast cases when convertInitializerTo seems like it should generally handle this sort of thing. llvm-svn: 243722
* AMDGPU/SI: Remove unused pattern for f32 constant loadsTom Stellard2015-07-311-1/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11603 llvm-svn: 243719
* [ARM] Lower modulo operation to generate __aeabi_divmod on AndroidSumanth Gundapaneni2015-07-311-3/+4
| | | | | | | | | | | | | | For a modulo (reminder) operation, clang -target armv7-none-linux-gnueabi generates "__modsi3" clang -target armv7-none-eabi generates "__aeabi_idivmod" clang -target armv7-linux-androideabi generates "__modsi3" Android bionic libc doesn't provide a __modsi3, instead it provides a "__aeabi_idivmod". This patch fixes the LLVM ARMISelLowering to generate the correct call when ever there is a modulo operation. Differential Revision: http://reviews.llvm.org/D11661 llvm-svn: 243717
* MIR Parser: Report an error when a constant pool item is redefined.Alex Lorenz2015-07-301-3/+6
| | | | llvm-svn: 243696
* MIR Parser: Report an error when a virtual register is redefined.Alex Lorenz2015-07-301-3/+5
| | | | llvm-svn: 243695
OpenPOWER on IntegriCloud