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* Attempt to recover gdb bot after r174445.Manman Ren2013-02-061-0/+2
| | | | | | | | | Failure: undefined symbol 'Lline_table_start0'. Root-cause: we use a symbol subtraction to calculate at_stmt_list, but the line table entries are not dumped in the assembly. Fix: use zero instead of a symbol subtraction for Compile Unit 0. llvm-svn: 174479
* Fix some formatting & add comments, following Eric's reviewEli Bendersky2013-02-061-12/+19
| | | | llvm-svn: 174473
* Add the target-dependent (string) attributes from the AttrBuilder to the ↵Bill Wendling2013-02-051-2/+13
| | | | | | AttributeSet. llvm-svn: 174467
* Add missing file to CMake listEli Bendersky2013-02-051-0/+1
| | | | llvm-svn: 174465
* Initial support for DWARF CFI parsing and dumping in LLVMEli Bendersky2013-02-054-1/+281
| | | | llvm-svn: 174463
* Convert to storing the attribute's internals as enums, integers, and strings.Bill Wendling2013-02-052-127/+251
| | | | | | | | The stuff we're handing are all enums (Attribute::AttrKind), integers and strings. Don't convert them to Constants, which is an unnecessary step here. The rest of the changes are mostly mechanical. llvm-svn: 174456
* Make sure the correct opcodes are used to SUB and ADD the stackEli Bendersky2013-02-051-13/+18
| | | | | | | pointer in function prologs/epilogs. The opcodes should depend on the data model (LP64 vs. ILP32) rather than the architecture bit-ness. llvm-svn: 174446
* Dwarf: support for LTO where a single object file can have multiple line tablesManman Ren2013-02-053-15/+61
| | | | | | | | | We generate one line table for each compilation unit in the object file. Reviewed by Eric and Kevin. rdar://problem/13067005 llvm-svn: 174445
* [mips] Do not use function CC_MipsN_VarArg unless the function being analyzedAkira Hatanaka2013-02-051-1/+1
| | | | | | | | | | | is a vararg function. The original code was examining flag OutputArg::IsFixed to determine whether CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this flag is often set to false when the function being analyzed is a non-variadic function. llvm-svn: 174442
* InstCombine: Fix and simplify the inttoptr side too.Benjamin Kramer2013-02-051-13/+8
| | | | llvm-svn: 174438
* Removed explicit inline as per the LLVM style guide.Michael Gottesman2013-02-051-7/+7
| | | | llvm-svn: 174432
* Reapply r174343, with a fix for a scary DAG combine bug where it failed to ↵Owen Anderson2013-02-051-2/+5
| | | | | | | | | | | | | | | | | | differentiate between the alignment of the base point of a load, and the overall alignment of the load. This caused infinite loops in DAG combine with the original application of this patch. ORIGINAL COMMIT LOG: When the target-independent DAGCombiner inferred a higher alignment for a load, it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. llvm-svn: 174431
* InstCombine: Harden code to work with vectors of pointers and simplify it a bit.Benjamin Kramer2013-02-051-11/+7
| | | | | | Found by running instcombine on a fabricated test case for the constant folder. llvm-svn: 174430
* Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma2013-02-052-1/+214
| | | | | | zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. llvm-svn: 174429
* ConstantFolding: Fix a crash when encoutering a truncating inttoptr.Benjamin Kramer2013-02-051-3/+7
| | | | | | This was introduced in r173293. llvm-svn: 174424
* Loop Vectorizer: Refactor code to compute vectorized memory instruction costArnold Schwaighofer2013-02-051-79/+178
| | | | | | | Introduce a helper class that computes the cost of memory access instructions. No functionality change intended. llvm-svn: 174422
* [SjLj Prepare] When demoting an invoke instructions to the stack, if the normalChad Rosier2013-02-051-5/+15
| | | | | | | edge is critical, then split it so we can insert the store. rdar://13126179 llvm-svn: 174418
* Remove liveout lists from MachineRegisterInfo.Jakob Stoklund Olesen2013-02-053-16/+2
| | | | | | | | All targets are now adding return value registers as implicit uses on return instructions, and there is no longer a need for the live out lists. llvm-svn: 174417
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-056-142/+7
| | | | | | | Now that return value registers are return instruction uses, there is no need for special treatment of return blocks. llvm-svn: 174416
* Move MRI liveouts to AArch64 return instructions.Jakob Stoklund Olesen2013-02-052-14/+12
| | | | llvm-svn: 174415
* Move MRI liveouts to XCore return instructions.Jakob Stoklund Olesen2013-02-052-16/+14
| | | | llvm-svn: 174414
* Move MRI liveouts to Sparc return instructions.Jakob Stoklund Olesen2013-02-052-16/+13
| | | | llvm-svn: 174413
* Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma2013-02-051-102/+70
| | | | llvm-svn: 174412
* Move MRI liveouts to MSP430 return instructions.Jakob Stoklund Olesen2013-02-052-13/+9
| | | | llvm-svn: 174411
* Move MRI liveouts to Mips return instructions.Jakob Stoklund Olesen2013-02-052-16/+12
| | | | llvm-svn: 174410
* Move MRI liveouts to PowerPC return instructions.Jakob Stoklund Olesen2013-02-051-21/+9
| | | | llvm-svn: 174409
* Move MRI liveouts to MBlaze return instructions.Jakob Stoklund Olesen2013-02-052-19/+17
| | | | llvm-svn: 174408
* Move MRI liveouts to Hexagon return instructions.Jakob Stoklund Olesen2013-02-052-11/+10
| | | | llvm-svn: 174407
* Move MRI liveouts to ARM return instructions.Jakob Stoklund Olesen2013-02-053-18/+22
| | | | llvm-svn: 174406
* Move MRI liveouts to X86 return instructions.Jakob Stoklund Olesen2013-02-052-12/+12
| | | | llvm-svn: 174402
* [MC] Bundle alignment: Invalidate relaxed fragmentsDerek Schuff2013-02-051-7/+8
| | | | | | | | | | | | | | | | Currently, when a fragment is relaxed, its size is modified, but its offset is not (it gets laid out as a side effect of checking whether it needs relaxation), then all subsequent fragments are invalidated because their offsets need to change. When bundling is enabled, relaxed fragments need to get laid out again, because the increase in size may push it over a bundle boundary. So instead of only invalidating subsequent fragments, also invalidate the fragment that gets relaxed, which causes it to get laid out again. This patch also fixes some trailing whitespace and fixes the bundling-related debug output of MCFragments. llvm-svn: 174401
* Don't use MRI liveouts in R600.Jakob Stoklund Olesen2013-02-053-5/+14
| | | | | | | | | | | | Something very strange is going on with the output registers in this target. Its ISelLowering code is inserting dangling CopyToReg nodes, hoping that those physregs won't get clobbered before the RETURN. This patch adds the output registers as implicit uses on RETURN instructions in the custom emission pass. I'd much prefer to have those CopyToReg nodes glued to the RETURNs, but I don't see how. llvm-svn: 174400
* Avoid using MRI::liveout_iterator for computing VRSAVEs.Jakob Stoklund Olesen2013-02-051-6/+15
| | | | | | | | | | The liveout lists are about to be removed from MRI, this is the only place they were used after register allocation. Get the live out V registers directly from the return instructions instead. llvm-svn: 174399
* R600: Fold remaining CONST_COPY after expand pseudo instTom Stellard2013-02-052-12/+160
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174395
* R600: improve inputs/interpolation handlingTom Stellard2013-02-0510-252/+130
| | | | | | | | | | | | | | | | Use one intrinsic for all sorts of interpolation. Use two separate unexpanded instructions to represent INTERP_XY and _ZW - this will allow to eliminate one part if it's not used. Track liveness of special interpolation regs instead of reserving them - this will allow to reuse those regs, lowering reg pressure. Patch By: Vadim Girlin v2[Vincent Lejeune]: Rebased against current llvm master Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174394
* R600: Emit function name in the AsmPrinterTom Stellard2013-02-051-0/+3
| | | | | | | | Emitting the function name allows us to check for it in the FileCheck tests so we can make sure FileCheck is checking the output of the correct function. llvm-svn: 174392
* R600/SI: Add patterns for fcos and fsin.Tom Stellard2013-02-051-0/+10
| | | | | | | | | | Fixes 37 piglit tests and allows e.g. FlightGear to run with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174391
* Fix commentsEli Bendersky2013-02-051-1/+1
| | | | llvm-svn: 174390
* Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma2013-02-051-16/+143
| | | | | | for the existing instructions. llvm-svn: 174389
* Fix signed-unsigned comparison warning.Tim Northover2013-02-051-8/+10
| | | | llvm-svn: 174387
* Loop Vectorizer: Handle pointer stores/loads in getWidestType()Arnold Schwaighofer2013-02-051-9/+31
| | | | | | | | | | | | | | | | | In the loop vectorizer cost model, we used to ignore stores/loads of a pointer type when computing the widest type within a loop. This meant that if we had only stores/loads of pointers in a loop we would return a widest type of 8bits (instead of 32 or 64 bit) and therefore a vector factor that was too big. Now, if we see a consecutive store/load of pointers we use the size of a pointer (from data layout). This problem occured in SingleSource/Benchmarks/Shootout-C++/hash.cpp (reduced test case is the first test in vector_ptr_load_store.ll). radar://13139343 llvm-svn: 174377
* Fix remaining StringRef abuse.Tim Northover2013-02-051-2/+2
| | | | | | This should fix the valgrind buildbot failure. llvm-svn: 174375
* Revert r174343, "When the target-independent DAGCombiner inferred a higher ↵NAKAMURA Takumi2013-02-051-5/+2
| | | | | | | | alignment for a load," It caused hangups in compiling clang/lib/Parse/ParseDecl.cpp and clang/lib/Driver/Tools.cpp in stage2 on some hosts. llvm-svn: 174374
* Link .ARM.exidx with corresponding text section.Logan Chien2013-02-051-0/+18
| | | | | | | | The sh_link in the ELF section header of .ARM.exidx should be filled with the section index of the corresponding text section. llvm-svn: 174372
* ARM cost model: Cost for scalar integer casts and floating point conversionsArnold Schwaighofer2013-02-051-7/+108
| | | | | | Also adds some costs for vector integer float conversions. llvm-svn: 174371
* Fix formatting in AArch64 backend.Tim Northover2013-02-0524-841/+577
| | | | | | | | | | | This should fix three purely whitespace issues: + 80 column violations. + Tab characters. + TableGen brace placement. No functional changes. llvm-svn: 174370
* Remove cyclic dependency in AArch64 librariesTim Northover2013-02-0523-814/+874
| | | | | | | | This moves the bit twiddling and string fiddling functions required by other parts of the backend into a separate library. Previously they resided in AArch64Desc, which created a circular dependency between various components. llvm-svn: 174369
* This patch that sets the Mips ELF header flag for Jack Carter2013-02-054-1/+12
| | | | | | | | MicroMips architectures. Contributer: Zoran Jovanovic llvm-svn: 174360
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-054-36/+56
| | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
* Add target-dependent versions of addAttribute/removeAttribute to AttrBuilder.Bill Wendling2013-02-051-1/+13
| | | | llvm-svn: 174356
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