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* Don't pass null to memcpy. Should fix the asan bots.Rafael Espindola2016-10-051-1/+2
| | | | llvm-svn: 283336
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-057-19/+43
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert r282920 "X86: Allow conditional tail calls in Win64 "leaf" functions ↵Hans Wennborg2016-10-052-6/+6
| | | | | | | | | (PR26302)" This is suspected to cause a miscompile in Chromium. Reverting while investigating. llvm-svn: 283329
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-058-77/+25
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [X86] Don't randomly encode %rip where illegalDouglas Katzman2016-10-052-4/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D25112 llvm-svn: 283326
* [Thumb] Don't try and emit LDRH/LDRB from the constant poolJames Molloy2016-10-051-0/+1
| | | | | | | | This is not a valid encoding - these instructions cannot do PC-relative addressing. The underlying problem here is of whitelist in ARMISelDAGToDAG that unwraps ARMISD::Wrappers during addressing-mode selection. This didn't realise TargetConstantPool was actually possible, so didn't handle it. llvm-svn: 283323
* Test commit permissionOren Ben Simhon2016-10-051-2/+2
| | | | llvm-svn: 283318
* [AVR] Don't select 'MOVW' instructions when they are not supportedDylan McKay2016-10-051-15/+41
| | | | | | | We have a subtarget feature which we were ignoring, which was causing us to generate unsupported instructions for some older chips. llvm-svn: 283317
* [AVR] Add AVRRegisterInfo::splitReg functionDylan McKay2016-10-052-2/+14
| | | | | | | No tests are included just yet - this is used from the pseudo instruction expander pass, which hasn't been pulled in-tree yet. llvm-svn: 283316
* Fix machine operand traversal in ScheduleDAGInstrs::fixupKillsKrzysztof Parzyszek2016-10-051-2/+7
| | | | llvm-svn: 283315
* [AVR] Update return type of dynamic alloca passDylan McKay2016-10-051-2/+2
| | | | | | It was recently changed from 'const char*' to StringRef llvm-svn: 283312
* [AVR] Add the AVR frame lowering codeDylan McKay2016-10-052-0/+538
| | | | | | | | | | | | Summary: This allows AVR to lower frames into assembly code. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25032 llvm-svn: 283311
* [AVR] Split all of the AVR device definitions into a separate fileDylan McKay2016-10-052-487/+493
| | | | | | | We have ~500 lines of subtarget feature definitions, they don't belong in our main TableGen file. llvm-svn: 283310
* [AVR] Enable the instruction printer in the target definitionDylan McKay2016-10-051-5/+5
| | | | llvm-svn: 283309
* [AVR] Add definitions for the ATTiny102 and ATtiny104 chipsDylan McKay2016-10-051-0/+2
| | | | llvm-svn: 283308
* Re-commit "Use StringRef in Support/Darf APIs (NFC)"Mehdi Amini2016-10-0510-92/+108
| | | | | | | This reverts commit r283285 and re-commit r283275 with a fix for format("%s", Str); where Str is a StringRef. llvm-svn: 283298
* [AVR] Add the machine code backendDylan McKay2016-10-053-0/+552
| | | | | | | | | | | | | | Summary: This adds the AVR machine code backend (`AVRAsmBackend.cpp`). This will allow us to generate machine code from assembled AVR instructions. Reviewers: arsenm, kparzysz Subscribers: modocache, japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25029 llvm-svn: 283297
* [Support][CommandLine] Add cl::getRegisteredSubcommands()Dean Michael Berris2016-10-051-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | This should allow users of the library to get a range to iterate through all the subcommands that are registered to the global parser. This allows users to define subcommands in libraries that self-register to have dispatch done at a different stage (like main). It allows for writing code like the following: for (auto *S : cl::getRegisteredSubcommands()) { if (*S) { // Dispatch on S->getName(). } } This change also contains tests that show this usage pattern. Reviewers: zturner, dblaikie, echristo Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24489 llvm-svn: 283296
* Blind attempt to fix windows build after r283290 - Use StringRef in ↵Mehdi Amini2016-10-051-1/+1
| | | | | | StringSaver API (NFC) llvm-svn: 283294
* Use StringRef in ARMConstantPool APIs (NFC)Mehdi Amini2016-10-053-16/+15
| | | | llvm-svn: 283293
* Revert "Codegen: Tail-duplicate during placement."Kyle Butt2016-10-053-326/+41
| | | | | | | | | | This reverts commit 062ace9764953e9769142c1099281a345f9b6bdc. Issue with loop info and block removal revealed by polly. I have a fix for this issue already in another patch, I'll re-roll this together with that fix, and a test case. llvm-svn: 283292
* Use StringRef in FastISel API (NFC)Mehdi Amini2016-10-051-1/+1
| | | | llvm-svn: 283291
* Use StringRef in StringSaver API (NFC)Mehdi Amini2016-10-052-7/+7
| | | | llvm-svn: 283290
* Use StringRef in ARCRuntimeEntryPoints APIs (NFC)Mehdi Amini2016-10-051-6/+3
| | | | llvm-svn: 283288
* [libFuzzer] add ShrinkValueProfileTest, move code around, NFCKostya Serebryany2016-10-058-111/+141
| | | | llvm-svn: 283286
* Revert "Re-commit "Use StringRef in Support/Darf APIs (NFC)""Mehdi Amini2016-10-059-104/+90
| | | | | | One test seems randomly broken: DebugInfo/X86/gnu-public-names.ll llvm-svn: 283285
* Use StringRef in MCSectionMachO (NFC)Mehdi Amini2016-10-051-16/+14
| | | | llvm-svn: 283284
* Use StringRef in DarwinAsmParser (NFC)Mehdi Amini2016-10-051-4/+3
| | | | llvm-svn: 283283
* [LoopDistribute] Fix a typo in the pass name.Michael Zolotukhin2016-10-051-1/+1
| | | | llvm-svn: 283282
* Re-commit "Use StringRef in Support/Darf APIs (NFC)"Mehdi Amini2016-10-059-90/+104
| | | | | | | This reverts commit r283278 and re-commit r283275 with the update to fix the build on the LLDB side. llvm-svn: 283281
* [libFuzzer] clear the corpus elements if they are evicted (i.e. smaller ↵Kostya Serebryany2016-10-053-6/+38
| | | | | | elements with proper coverage are found). Make sure we never try to mutate empty element. Print the corpus size in bytes in the status lines llvm-svn: 283279
* Revert "Use StringRef in Support/Darf APIs (NFC)"Mehdi Amini2016-10-059-104/+90
| | | | | | This reverts commit r283275, it broke LLDB Android debug server. llvm-svn: 283278
* Use StringRef instead of raw pointers in ARMBuildAttrs (NFC)Mehdi Amini2016-10-051-6/+12
| | | | llvm-svn: 283277
* Use StringRef in Support/Darf APIs (NFC)Mehdi Amini2016-10-049-90/+104
| | | | llvm-svn: 283275
* Codegen: Tail-duplicate during placement.Kyle Butt2016-10-043-41/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | The tail duplication pass uses an assumed layout when making duplication decisions. This is fine, but passes up duplication opportunities that may arise when blocks are outlined. Because we want the updated CFG to affect subsequent placement decisions, this change must occur during placement. In order to achieve this goal, TailDuplicationPass is split into a utility class, TailDuplicator, and the pass itself. The pass delegates nearly everything to the TailDuplicator object, except for looping over the blocks in a function. This allows the same code to be used for tail duplication in both places. This change, in concert with outlining optional branches, allows triangle shaped code to perform much better, esepecially when the taken/untaken branches are correlated, as it creates a second spine when the tests are small enough. Issue from previous rollback fixed, and a new test was added for that case as well. Differential revision: https://reviews.llvm.org/D18226 llvm-svn: 283274
* [C API] Add LLVMConstExactUDiv and LLVMBuildExactUDiv functions.Manuel Jacob2016-10-041-0/+11
| | | | | | | | | | | | | | Summary: These are analog to the existing LLVMConstExactSDiv and LLVMBuildExactSDiv functions. Reviewers: deadalnix, majnemer Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D25259 llvm-svn: 283269
* Misc improvements to StringTableBuilder.Rafael Espindola2016-10-044-81/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds write methods to StringTableBuilder so that it is easier to change the underlying implementation. Using the write methods, avoid creating a temporary buffer when using mmaped output. It also uses a more compact key in the DenseMap. Overall this produces a slightly faster lld: firefox master 6.853419709 patch 6.841968912 1.00167361138x faster chromium master 4.297280174 patch 4.298712163 1.00033323147x slower chromium fast master 1.802335952 patch 1.806872459 1.00251701521x slower the gold plugin master 0.3247149 patch 0.321971644 1.00852017888x faster clang master 0.551279945 patch 0.543733194 1.01387951128x faster llvm-as master 0.032743458 patch 0.032143478 1.01866568391x faster the gold plugin fsds master 0.350814247 patch 0.348571741 1.00643341309x faster clang fsds master 0.6281672 patch 0.621130222 1.01132931187x faster llvm-as fsds master 0.030168899 patch 0.029797155 1.01247582194x faster scylla master 3.104222518 patch 3.059590248 1.01458766252x faster llvm-svn: 283266
* [cpu-detection] Copy simplified version of get_cpuid_max to remove ↵Alina Sbirlea2016-10-041-5/+37
| | | | | | | | | | | | | | | | | dependency to clang's implementation Summary: Attempting to fix PR30384. Take the same approach as in compiler_rt and add a simplified version of __get_cpuid_max. Including cpuid.h is no longer needed. Reviewers: echristo, joerg Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D24597 llvm-svn: 283265
* Revert r283248. It caused failures in the hexagon buildbots.David L Kreitzer2016-10-041-6/+7
| | | | llvm-svn: 283254
* [Target] move reciprocal estimate settings from TargetOptions to TargetLoweringSanjay Patel2016-10-046-65/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | The motivation for the change is that we can't have pseudo-global settings for codegen living in TargetOptions because that doesn't work with LTO. Ideally, these reciprocal attributes will be moved to the instruction-level via FMF, metadata, or something else. But making them function attributes is at least an improvement over the current state. The ingredients of this patch are: Remove the reciprocal estimate command-line debug option. Add TargetRecip to TargetLowering. Remove TargetRecip from TargetOptions. Clean up the TargetRecip implementation to work with this new scheme. Set the default reciprocal settings in TargetLoweringBase (everything is off). Update the PowerPC defaults, users, and tests. Update the x86 defaults, users, and tests. Note that if this patch needs to be reverted, the related clang patch checked in at r283251 should be reverted too. Differential Revision: https://reviews.llvm.org/D24816 llvm-svn: 283252
* Next set of additional error checks for invalid Mach-O files for theKevin Enderby2016-10-041-0/+47
| | | | | | | | | | | load commands that uses the MachO::encryption_info_command and MachO::encryption_info_command types but not used in llvm libObject code but used in llvm tool code. This includes just LC_ENCRYPTION_INFO and LC_ENCRYPTION_INFO_64 load commands. llvm-svn: 283250
* [safestack] Requires a valid TargetMachine to be passed to the SafeStack pass.David L Kreitzer2016-10-041-7/+6
| | | | | | | | Patch by Michael LeMay Differential revision: http://reviews.llvm.org/D24896 llvm-svn: 283248
* AArch64: Macrofusion: Split features, add missing combinations.Matthias Braun2016-10-043-11/+59
| | | | | | | | | | | | | | | | AArch64InstrInfo::shouldScheduleAdjacent() determines whether two instruction can benefit from macroop fusion on apple CPUs. The list turned out to be incomplete: - the "rr" variants of the instructions were missing - even the "rs" variants can have shift value == 0 and behave like the "rr" variants This also splits the MacropFusion target feature into ArithmeticBccFusion and ArithmeticCbzFusion. Differential Revision: https://reviews.llvm.org/D25142 llvm-svn: 283243
* [asan] LLVM: Switch to using dynamic shadow offset on iOSAnna Zaks2016-10-041-2/+3
| | | | | | | | | | The VM layout is not stable between iOS version releases, so switch to dynamic shadow offset. This is the LLVM counterpart of https://reviews.llvm.org/D25218 Differential Revision: https://reviews.llvm.org/D25219 llvm-svn: 283239
* Don't filter diagnostics written as YAML to the output fileHal Finkel2016-10-041-1/+1
| | | | | | | | | | | | | | | The purpose of the YAML diagnostic output file is to collect information on optimizations performed, or not performed, for later processing by tools that help users (and compiler developers) understand how code was optimized. As such, the diagnostics that appear in the file should not be coupled to what a user might want to see summarized for them as the compiler runs, and in fact, because the user likely does not know what optimization diagnostics their tools might want to use, the user cannot provide a useful filter regardless. As such, we shouldn't filter the diagnostics going to the output file. Differential Revision: https://reviews.llvm.org/D25224 llvm-svn: 283236
* Serialize remark argument as a mapping to get proper quotation for the value.Adam Nemet2016-10-041-11/+5
| | | | llvm-svn: 283231
* Allow derived classes of OptimizationRemarkAnalysis in YAMLAdam Nemet2016-10-041-0/+8
| | | | llvm-svn: 283230
* [RS4GC] Handle ShuffleVector instruction in findBasePointerAnna Thomas2016-10-041-10/+32
| | | | | | | | | | | | | | | Summary: This patch modifies the findBasePointer to handle the shufflevector instruction. Tests run: RS4GC tests, local downstream tests. Reviewers: reames, sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25197 llvm-svn: 283219
* Remove duplicated typedef. NFC.Rafael Espindola2016-10-041-5/+4
| | | | llvm-svn: 283216
* [Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register setNemanja Ivanovic2016-10-043-6/+81
| | | | | | | | | | | | | This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
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