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* [IR] Use isIntOrIntVectorTy instead of writing it out the long way. NFCCraig Topper2017-06-251-10/+4
| | | | llvm-svn: 306250
* [X86][SSE] Remove unused memopfsf32_128/memopfsf64_128 scalar memopsSimon Pilgrim2017-06-251-10/+0
| | | | | | The 'scalar' simd bitops were dropped a while ago llvm-svn: 306248
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-06-252-2/+2
| | | | llvm-svn: 306247
* [InstCombine] add (sext i1 X), 1 --> zext (not X)Sanjay Patel2017-06-251-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://rise4fun.com/Alive/i8Q A narrow bitwise logic op is obviously better than math for value tracking, and zext is better than sext. Typically, the 'not' will be folded into an icmp predicate. The IR difference would even survive through codegen for x86, so we would see worse code: https://godbolt.org/g/C14HMF one_or_zero(int, int): # @one_or_zero(int, int) xorl %eax, %eax cmpl %esi, %edi setle %al retq one_or_zero_alt(int, int): # @one_or_zero_alt(int, int) xorl %ecx, %ecx cmpl %esi, %edi setg %cl movl $1, %eax subl %ecx, %eax retq llvm-svn: 306243
* AVX-512: Fixed a crash during legalization of <3 x i8> typeElena Demikhovsky2017-06-251-2/+1
| | | | | | | | | The compiler fails with assertion during legalization of SETCC for <3 x i8> operands. The result is extended to <4 x i8> and then truncated <4 x i1>. It does not happen on AVX2, because the final result of SETCC is <4 x i32>. Differential Revision: https://reviews.llvm.org/D34503 llvm-svn: 306242
* [AST] Fix a bug in aliasesUnknownInst. Make sure we are comparing the ↵Xin Tong2017-06-251-2/+2
| | | | | | | | | | | | | | | | unknown instructions in the alias set and the instruction interested in. Summary: Make sure we are comparing the unknown instructions in the alias set and the instruction interested in. I believe this is clearly a bug (missed opportunity). I can also add some test cases if desired. Reviewers: hfinkel, davide, dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34597 llvm-svn: 306241
* [GlobalISel][X86] Support vector type G_EXTRACT selection.Igor Breger2017-06-251-0/+104
| | | | | | | | | | | | | | | | Summary: Support vector type G_EXTRACT selection. For now G_EXTRACT marked as legal for any type, so nothing to do in legalizer. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: guyblank Subscribers: guyblank, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33957 llvm-svn: 306240
* [AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2Dorit Nuzman2017-06-252-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | The cost of an interleaved access was only implemented for AVX512. For other X86 targets an overly conservative Base cost was returned, resulting in avoiding vectorization where it is actually profitable to vectorize. This patch starts to add costs for AVX2 for most prominent cases of interleaved accesses (stride 3,4 chars, for now). Note1: Improvements of up to ~4x were observed in some of EEMBC's rgb workloads; There is also a known issue of 15-30% degradations on some of these workloads, associated with an interleaved access followed by type promotion/widening; the resulting shuffle sequence is currently inefficient and will be improved by a series of patches that extend the X86InterleavedAccess pass (such as D34601 and more to follow). Note 2: The costs in this patch do not reflect port pressure penalties which can be very dominant in the case of interleaved accesses since most of the shuffle operations are restricted to a single port. Further tuning, that may incorporate these considerations, will be done on top of the upcoming improved shuffle sequences (that is, along with the abovementioned work to extend X86InterleavedAccess pass). Differential Revision: https://reviews.llvm.org/D34023 llvm-svn: 306238
* Add support for Ananas platformEd Schouten2017-06-251-0/+2
| | | | | | | | | | | | | | | | | Ananas is a home-brew operating system, mainly for amd64 machines. After using GCC for quite some time, it has switched to clang and never looked back - yet, having to manually patch things is annoying, so it'd be much nicer if this was in the official tree. More information: https://github.com/zhmu/ananas/ https://rink.nu/projects/ananas.html Submitted by: Rink Springer Differential Revision: https://reviews.llvm.org/D32937 llvm-svn: 306237
* [pdb] Fix reading of llvm-generated PDBs by cvdump.Zachary Turner2017-06-251-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you dump a pdb to yaml, and then round-trip it back to a pdb, and run cvdump -l <file> on the new pdb, cvdump will generate output such as this. *** LINES ** Module: "d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj" Error: Line number corrupted: invalid file id 0 <Unknown> (MD5), 0001:00000010-0000001A, line/addr pairs = 3 5 00000010 6 00000013 7 00000018 Note the error message about the corrupted line number. It turns out that the problem is that cvdump cannot find the /names stream (e.g. the global string table), and the reason it can't find the /names stream is because it doesn't understand the NameMap that we serialize which tells pdb consumers which stream has the string table. Some experimentation shows that if we add items to the hash table in a specific order before serializing it, cvdump can read it. This suggests that either we're using the wrong hash function, or we're serializing something incorrectly, but it will take some deeper investigation to figure out how / why. For now, this at least allows cvdump to read our line information (and incidentally, produces an identical byte sequence to what Microsoft tools produce when writing the named stream map). Differential Revision: https://reviews.llvm.org/D34491 llvm-svn: 306233
* [PGO] Implementate profile counter regiser promotionXinliang David Li2017-06-253-15/+222
| | | | | | Differential Revision: http://reviews.llvm.org/D34085 llvm-svn: 306231
* [SCEV] Avoid copying ConstantRange just to get the min/max valueCraig Topper2017-06-241-67/+62
| | | | | | | | | | | | | | | | | | | | | Summary: This patch changes getRange to getRangeRef and returns a reference to the ConstantRange object stored inside the DenseMap caches. We then take advantage of that to add new helper methods that can return min/max value of a signed or unsigned ConstantRange using that reference without first copying the ConstantRange. getRangeRef calls itself recursively and I believe the reference return is fine for those calls. I've left getSignedRange and getUnsignedRange returning a ConstantRange object so they will make a copy now. This is to ensure safety since the reference will be invalidated if the DenseMap changes. I'm sure there are still more places that can take advantage of the reference and I'll submit future patches as I find them. Reviewers: sanjoy, davide Reviewed By: sanjoy Subscribers: zzheng, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D32978 llvm-svn: 306229
* fix trivial typos in comment, NFCHiroshi Inoue2017-06-242-2/+2
| | | | llvm-svn: 306211
* fix trivial typos in comment, NFCHiroshi Inoue2017-06-241-1/+1
| | | | | | dereferencable -> dereferenceable llvm-svn: 306210
* [SelectionDAG] set dereferenceable flag when expanding memcpy/memmoveHiroshi Inoue2017-06-242-8/+43
| | | | | | | | | | When SelectionDAG expands memcpy (or memmove) call into a sequence of load and store instructions, it disregards dereferenceable flag even the source pointer is known to be dereferenceable. This results in an assertion failure if SelectionDAG commonizes a load instruction generated for memcpy with another load instruction for the source pointer. This patch makes SelectionDAG to set the dereferenceable flag for the load instructions properly to avoid the assertion failure. Differential Revision: https://reviews.llvm.org/D34467 llvm-svn: 306209
* [IR][AssumptionCache] Add m_Shift and m_BitwiseLogic matchers to replace a ↵Craig Topper2017-06-241-9/+2
| | | | | | | | | | | | | | | | | | | couple m_CombineOr Summary: m_CombineOr isn't very efficient. The code using it is also quite verbose. This patch adds m_Shift and m_BitwiseLogic matchers to make the using code more concise and improve the match efficiency. Reviewers: spatel, davide Reviewed By: davide Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D34593 llvm-svn: 306206
* [ValueTracking][InstCombine] Use m_Shr instead m_CombineOr(m_LShr, m_AShr). NFCCraig Topper2017-06-242-7/+3
| | | | llvm-svn: 306205
* [Analysis][Transforms] Use commutable matchers instead of m_CombineOr in a ↵Craig Topper2017-06-243-8/+4
| | | | | | few places. NFC llvm-svn: 306204
* Simplify the processFixupValue interface. NFC.Rafael Espindola2017-06-247-30/+16
| | | | llvm-svn: 306202
* Remove a processFixupValue hack.Rafael Espindola2017-06-242-35/+32
| | | | | | | | | | | The intention of processFixupValue is not to redefine the semantics of MCExpr. It is odd enough that a expression lowers to a PCRel MCExpr or not depending on what it looks like. At least it is a local hack now. I left a fix for anyone trying to figure out what producers should be producing a different expression. llvm-svn: 306200
* [InstCombine] Don't replace allocas with smaller globalsVitaly Buka2017-06-241-1/+14
| | | | | | | | | | | | | | | | | | Summary: InstCombine replaces large allocas with small globals consts causing buffer overflows on valid code, see PR33372. This fix permits this optimization only if the global is dereference for alloca size. Fixes PR33372 Reviewers: eugenis, majnemer, chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34311 llvm-svn: 306194
* Make visible isDereferenceableAndAlignedPointer(..., const APInt &Size, ...)Vitaly Buka2017-06-241-0/+10
| | | | | | | | | | | | Summary: Used by D34311 and D34467 Reviewers: hfinkel, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34585 llvm-svn: 306193
* [WebAssembly] Fix build after r306177Derek Schuff2017-06-241-10/+14
| | | | llvm-svn: 306190
* Remove redundant argument.Rafael Espindola2017-06-2415-23/+24
| | | | llvm-svn: 306189
* [ORC] Re-apply r306166 and r306168 with fix for regression test.Lang Hames2017-06-234-27/+69
| | | | llvm-svn: 306182
* [llvm-pdbutil] Dump raw bytes of module symbols and debug chunks.Zachary Turner2017-06-231-8/+28
| | | | llvm-svn: 306179
* Move Value adjustment to applyFixup. NFC.Rafael Espindola2017-06-231-2/+1
| | | | llvm-svn: 306178
* ARM: move some logic from processFixupValue to applyFixup.Rafael Espindola2017-06-2315-50/+83
| | | | | | | | | | | | processFixupValue is called on every relaxation iteration. applyFixup is only called once at the very end. applyFixup is then the correct place to do last minute changes and value checks. While here, do proper range checks again for fixup_arm_thumb_bl. We used to do it, but dropped because of thumb2. We now do it again, but use the thumb2 range. llvm-svn: 306177
* This reverts commit r306166 and r306168.Rafael Espindola2017-06-233-51/+27
| | | | | | | | | Revert "[ORC] Remove redundant semicolons from DEFINE_SIMPLE_CONVERSION_FUNCTIONS uses." Revert "[ORC] Move ORC IR layer interface from addModuleSet to addModule and fix the module type as std::shared_ptr<Module>." They broke ExecutionEngine/OrcMCJIT/test-global-ctors.ll on linux. llvm-svn: 306176
* Reland r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic2017-06-231-3/+3
| | | | | | | | | | | | | | | | After fixing (r306173) a failing test in the lld test suite (r306173), reland r306095. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aui/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306174
* [AArch64][Falkor] Remove some non-existent opcodes from sched detail ↵Geoff Berry2017-06-231-12/+12
| | | | | | regexes. NFC. llvm-svn: 306170
* [DebugInfo] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-237-35/+61
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 306169
* [ORC] Remove redundant semicolons from DEFINE_SIMPLE_CONVERSION_FUNCTIONS uses.Lang Hames2017-06-231-2/+2
| | | | llvm-svn: 306168
* [llvm-pdbutil] Dump raw bytes of type and id records.Zachary Turner2017-06-232-1/+18
| | | | llvm-svn: 306167
* [ORC] Move ORC IR layer interface from addModuleSet to addModule and fix theLang Hames2017-06-233-27/+51
| | | | | | module type as std::shared_ptr<Module>. llvm-svn: 306166
* Revert "[LoopDeletion] NFC: Move phi node value setting into prepass"Anna Thomas2017-06-231-13/+11
| | | | | | | | | This reverts commit r306157. It caused some timeouts in clang tests. Perhaps unreachable loops have far too many phi nodes. Reverting and investigating. llvm-svn: 306162
* [llvm-pdbutil] Dump raw bytes of various DBI stream subsections.Zachary Turner2017-06-231-16/+36
| | | | llvm-svn: 306160
* [MSP430] Fix data layout string.Vadzim Dambrouski2017-06-231-2/+6
| | | | | | | | | | | | | | | | Summary: Without this patch some types have incorrect size and/or alignment according to the MSP430 EABI. Reviewers: asl, awygle Reviewed By: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34561 llvm-svn: 306159
* [LoopDeletion] NFC: Move phi node value setting into prepassAnna Thomas2017-06-231-11/+13
| | | | | | | | | | Currently, the implementation of delete dead loops has a special case when the loop being deleted is never executed. This special case (updating of exit block's incoming values for phis) can be run as a prepass for non-executable loops before performing the actual deletion. llvm-svn: 306157
* [APInt] Move the single word cases of countTrailingZeros and ↵Craig Topper2017-06-231-7/+2
| | | | | | countLeadingOnes inline for consistency with countTrailingOnes and countLeadingZeros. NFCI llvm-svn: 306153
* [CorrelatedValuePropagation] Fix typo in comment sense->since. NFCCraig Topper2017-06-231-1/+1
| | | | llvm-svn: 306152
* [CorrelatedValuePropagation] Remove comment about iterating switch cases in ↵Craig Topper2017-06-231-2/+1
| | | | | | reverse order. This is no longer being done after r298791. NFC llvm-svn: 306151
* [llvm-pdbutil] Dump raw bytes of pdb name map.Zachary Turner2017-06-231-0/+8
| | | | | | | | This patch dumps the raw bytes of the pdb name map which contains the mapping of stream name to stream index for the string table and other reserved streams. llvm-svn: 306148
* Revert "[Hexagon] Handle decreasing of stack alignment in frame lowering"Krzysztof Parzyszek2017-06-234-51/+2
| | | | | | This breaks passing of aligned function arguments. llvm-svn: 306145
* [AArch64] Prefer Bcc to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free".Chad Rosier2017-06-236-3/+387
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains a pass that transforms CBZ/CBNZ/TBZ/TBNZ instructions into a conditional branch (Bcc), when the NZCV flags can be set for "free". This is preferred on targets that have more flexibility when scheduling Bcc instructions as compared to CBZ/CBNZ/TBZ/TBNZ (assuming all other variables are equal). This can reduce register pressure and is also the default behavior for GCC. A few examples: add w8, w0, w1 -> cmn w0, w1 ; CMN is an alias of ADDS. cbz w8, .LBB_2 -> b.eq .LBB0_2 ; single def/use of w8 removed. add w8, w0, w1 -> adds w8, w0, w1 ; w8 has multiple uses. cbz w8, .LBB1_2 -> b.eq .LBB1_2 sub w8, w0, w1 -> subs w8, w0, w1 ; w8 has multiple uses. tbz w8, #31, .LBB6_2 -> b.ge .LBB6_2 In looking at all current sub-target machine descriptions, this transformation appears to be either positive or neutral. Differential Revision: https://reviews.llvm.org/D34220. llvm-svn: 306144
* [X86] Fix SP adjustment in stack probes emitted on 32-bit Windows.whitequark2017-06-231-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit r306010 adjusted the condition as follows: - if (Is64Bit) { + if (!STI.isTargetWin32()) { The intent was to preserve the behavior on all Windows platforms but extend the behavior on 64-bit Windows platforms to every other one. (Before r306010, emitStackProbeCall only ever executed when emitting code for Windows triples.) Unfortunately, if (Is64Bit && STI.isOSWindows()) is not the same as if (!STI.isTargetWin32()) because of the way isTargetWin32() is defined: bool isTargetWin32() const { return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC()); } In practice this broke the JIT tests on 32-bit Windows, which did not satisfy the new condition: LLVM :: ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll LLVM :: ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll LLVM :: ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll LLVM :: ExecutionEngine/MCJIT/test-loadstore.ll LLVM :: ExecutionEngine/OrcMCJIT/2003-01-15-AlignmentTest.ll LLVM :: ExecutionEngine/OrcMCJIT/2003-08-15-AllocaAssertion.ll LLVM :: ExecutionEngine/OrcMCJIT/2003-08-23-RegisterAllocatePhysReg.ll LLVM :: ExecutionEngine/OrcMCJIT/test-loadstore.ll because %esp was not updated correctly. The failures are only visible on a MSVC 2017 Debug build, for which we do not have bots. llvm-svn: 306142
* [llvm-pdbutil] Add a function for formatting MSF data.Zachary Turner2017-06-231-0/+8
| | | | | | | | | | | | | | | | | | | The goal here is to make it possible to display absolute file offsets when dumping byets from an MSF. The problem is that when dumping bytes from an MSF, often the bytes will cross a block boundary and encounter a discontinuity. We can't use the normal formatBinary() function for this because this would just treat the sequence as entirely ascending, and not account out-of-order blocks. This patch adds a formatMsfData() function to our printer, and then uses this function to improve the output of the -stream-data command line option for dumping bytes from a particular stream. Test coverage is also expanded to make sure to include all possible scenarios of offsets, sizes, and crossing block boundaries. llvm-svn: 306141
* [Hexagon] Remove call to printAndVerify from HexagonPassConfigKrzysztof Parzyszek2017-06-231-1/+0
| | | | | | | It causes an extra pass of the machine verifier to be added to the pass manager, and causes test/CodeGen/Generic/llc-start-stop.ll to fail. llvm-svn: 306140
* [x86] fix value types for SBB transform (PR33560)Sanjay Patel2017-06-231-8/+13
| | | | | | | | | | | I'm not sure yet why this wouldn't fail in the simple case, but clearly I used the wrong value type with: https://reviews.llvm.org/rL306040 ...and the bug manifests with: https://bugs.llvm.org/show_bug.cgi?id=33560 llvm-svn: 306139
* Fix a misleading indentation warning.Peter Collingbourne2017-06-231-3/+3
| | | | llvm-svn: 306130
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