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* Add missing override keywords.Craig Topper2014-11-231-2/+2
| | | | llvm-svn: 222634
* Masked Vector Load and Store Intrinsics.Elena Demikhovsky2014-11-2317-3148/+3872
| | | | | | | | | | | | | | Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 222632
* R600: Fix extloads of i1 on R600/EvergreenMatt Arsenault2014-11-231-0/+5
| | | | llvm-svn: 222631
* R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault2014-11-231-1/+2
| | | | | | | i1 is not a legal type on Evergreen, so this combine proceeded and tried to produce a bitcast between i1 and i8. llvm-svn: 222630
* InstCombine: Propagate exact for (sdiv X, Pow2) -> (udiv X, Pow2)David Majnemer2014-11-221-2/+4
| | | | llvm-svn: 222625
* InstCombine: Propagate exact for (sdiv X, Y) -> (udiv X, Y)David Majnemer2014-11-221-1/+3
| | | | llvm-svn: 222624
* InstCombine: Propagate exact for (sdiv -X, C) -> (sdiv X, -C)David Majnemer2014-11-221-4/+6
| | | | llvm-svn: 222623
* Tidied up target triple OS detection. NFCSimon Pilgrim2014-11-225-14/+9
| | | | | | Use Triple::isOS*() helper functions where possible. llvm-svn: 222622
* InstCombine: Propagate exact in (udiv (lshr X,C1),C2) -> (udiv x,C1<<C2)David Majnemer2014-11-221-2/+7
| | | | llvm-svn: 222620
* [x86] Teach the vector shuffle yet another step of canonicalization.Chandler Carruth2014-11-221-2/+13
| | | | | | | | No functionality changed yet, but this will prevent subsequent patches from having to handle permutations of various interleaved shuffle patterns. llvm-svn: 222614
* InstCombine: Propagate NSW/NUW for X*(1<<Y) -> X<<YDavid Majnemer2014-11-221-4/+17
| | | | llvm-svn: 222613
* InstCombine: Propagate NSW for -X * -Y -> X * YDavid Majnemer2014-11-221-3/+10
| | | | llvm-svn: 222612
* InstSimplify: Simplify (sub 0, X) -> X if it's NUWDavid Majnemer2014-11-221-11/+3
| | | | | | This is a generalization of the X - (0 - Y) -> X transform. llvm-svn: 222611
* InstCombine: Silence a parenthesis warningDavid Majnemer2014-11-221-1/+1
| | | | llvm-svn: 222609
* InstCombine: Preserve nsw when folding X*(2^C) -> X << CDavid Majnemer2014-11-221-0/+2
| | | | llvm-svn: 222606
* InstCombine: Preserve nsw/nuw for ((X << C2)*C1) -> (X * (C1 << C2))David Majnemer2014-11-221-3/+12
| | | | llvm-svn: 222605
* InstCombine: Preserve nsw for (mul %V, -1) -> (sub 0, %V)David Majnemer2014-11-221-2/+7
| | | | llvm-svn: 222604
* [InstCombine] Re-commit of r218721 (Optimize icmp-select-icmp sequence)Gerolf Hoflehner2014-11-214-10/+190
| | | | | | | Fixes the self-host fail. Note that this commit activates dominator analysis in the combiner by default (like the original commit did). llvm-svn: 222590
* Fix transformation of add with pc argument to adr for non-immediateJoerg Sonnenberger2014-11-211-5/+25
| | | | | | arguments. llvm-svn: 222587
* [asan] remove old experimental codeKostya Serebryany2014-11-211-38/+0
| | | | llvm-svn: 222586
* R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2014-11-212-24/+8
| | | | | | | We need to use a s_mov_b32 rather than a copy, so that CSE will eliminate redundant moves to the m0 register. llvm-svn: 222584
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-216-40/+28
| | | | | | | | | | | | This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. llvm-svn: 222583
* R600/SI: Add SIFoldOperands passTom Stellard2014-11-214-0/+209
| | | | | | | This pass attempts to fold the source operands of mov and copy instructions into their uses. llvm-svn: 222581
* [mips][microMIPS] This patch implements functionality in MIPS delay slotJozef Kolek2014-11-213-11/+53
| | | | | | | | | | | filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS BEQ or BNE instruction which uses the register $0, then instead of emitting NOP this instruction is replaced by the corresponding microMIPS compact branch instruction, i.e. BEQZC or BNEZC. Differential Revision: http://reviews.llvm.org/D3566 llvm-svn: 222580
* R600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializableTom Stellard2014-11-211-0/+2
| | | | llvm-svn: 222579
* [Hexagon] Adding sxth instruction.Colin LeMahieu2014-11-213-8/+10
| | | | llvm-svn: 222577
* [Hexagon] Adding sxtb instruction. Renaming some identically named classes ↵Colin LeMahieu2014-11-212-15/+87
| | | | | | that will be removed after converting referencing defs. llvm-svn: 222575
* [asan] add statistic counter to dynamic alloca instrumentationKostya Serebryany2014-11-211-0/+3
| | | | llvm-svn: 222573
* [Hexagon] Removing SUB_rr and replacing with A2_sub.Colin LeMahieu2014-11-214-23/+6
| | | | llvm-svn: 222571
* Remove duplication of relocation names in lib/Object/ELFYAML.cppTim Northover2014-11-211-330/+7
| | | | | | | | | | We can now use the ELF relocation .def files to create the mapping of relocation numbers to names and avoid having to duplicate the list of relocations. Patch by Will Newton. llvm-svn: 222567
* Remove duplication of relocation names in lib/Object/ELF.cppTim Northover2014-11-211-742/+14
| | | | | | | | | | We can now use the ELF relocation .def files to create the mapping of relocation numbers to names and avoid having to duplicate the list of relocations. Patch by Will Newton. llvm-svn: 222566
* Debug Info: revert r222195, r222210 and r222239.Manman Ren2014-11-213-6/+6
| | | | | | | This is no longer needed after David's fix at r222377 + r222485. rdar://18958417 llvm-svn: 222563
* Disable header duplication at -Oz in loop-rotate pass.Roman Divacky2014-11-211-1/+2
| | | | llvm-svn: 222562
* Debug Info: add an assertion that the context field of a global variable can notManman Ren2014-11-211-1/+8
| | | | | | | | | | | be a DIType with identifier. This makes sure that there is no need to use DIScopeRef for global variable's context. rdar://18958417 llvm-svn: 222561
* [Objective-C] Support a new special module flag that will be put into theManman Ren2014-11-211-1/+2
| | | | | | | | objc_imageinfo struct. rdar://17954668 llvm-svn: 222558
* LazyValueInfo: range'ify some for-loops. No functional change.Hans Wennborg2014-11-211-34/+19
| | | | llvm-svn: 222557
* Add params() to FunctionType. NFC.Rafael Espindola2014-11-211-4/+3
| | | | | | While at it, also use makeArrayRef in elements(). llvm-svn: 222556
* Don't repeat class/function/variable names in comments. NFC.Sanjay Patel2014-11-211-47/+35
| | | | llvm-svn: 222555
* LazyValueInfo: fix some typos and indentation, etc. NFC.Hans Wennborg2014-11-211-10/+12
| | | | llvm-svn: 222554
* Add and use a helper elements() to StructType. NFC.Rafael Espindola2014-11-211-3/+2
| | | | llvm-svn: 222553
* Allow multiple -debug-only argsMatthias Braun2014-11-211-6/+17
| | | | | | Debug output is shown if any of the -debug-only arguments match. llvm-svn: 222547
* Less space; NFCSanjay Patel2014-11-211-8/+4
| | | | llvm-svn: 222546
* Add a feature flag for slow 32-byte unaligned memory accesses [x86].Sanjay Patel2014-11-214-10/+19
| | | | | | | | | | | | | | This patch adds a feature flag to avoid unaligned 32-byte load/store AVX codegen for Sandy Bridge and Ivy Bridge. There is no functionality change intended for those chips. Previously, the absence of AVX2 was being used as a proxy to detect this feature. But that hindered codegen for AVX-enabled AMD chips such as btver2 that do not have the 32-byte unaligned access slowdown. Performance measurements are included in PR21541 ( http://llvm.org/bugs/show_bug.cgi?id=21541 ). Differential Revision: http://reviews.llvm.org/D6355 llvm-svn: 222544
* Revert "Allow FDE references outside the +/-2GB range supported by PC ↵Duncan P. N. Exon Smith2014-11-211-11/+0
| | | | | | | | | | | | | | | | | relative offsets for code models other than small/medium. For JIT application, memory layout is less controlled and can result in truncations otherwise." This reverts commit r222538. It's causing test failures for CFI, at least on Darwin: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental/1189/ http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/1391/ Note that the previous incremental build was on r222537, and the CFI tests weren't failing: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental/1188/ llvm-svn: 222542
* [x86] Restructure the checking patterns for v16 and v32 avx2 vectorChandler Carruth2014-11-211-28/+24
| | | | | | | | | | shuffle lowering to allow much better blend matching. Specifically, with the new structure the code seems clearer to me and we correctly can hit the cases where merging two 128-bit lanes is a clear win and can be shuffled cheaply afterward. llvm-svn: 222539
* Allow FDE references outside the +/-2GB range supported by PC relativeJoerg Sonnenberger2014-11-211-0/+11
| | | | | | | | | | | | offsets for code models other than small/medium. For JIT application, memory layout is less controlled and can result in truncations otherwise. Patch from Akos Kiss. Differential Revision: http://reviews.llvm.org/D6079 llvm-svn: 222538
* [x86] Make the previous logic significantly less conservative and getChandler Carruth2014-11-211-14/+10
| | | | | | | | | | | | | a bunch more improvements. Non-lane-crossing is fine, the key is that lane merging only makes sense for single-input shuffles. Not sure why I got so turned around here. The code all works, I was just using the wrong model for it. This only updates v4 and v8 lowering. The v16 and v32 lowering requires restructuring the entire check sequence. llvm-svn: 222537
* [DAG] Teach how to turn a build_vector into a shuffle if some of the ↵Andrea Di Biagio2014-11-211-11/+39
| | | | | | | | | | | | | | operands are zero. Before this patch, the DAGCombiner only tried to convert build_vector dag nodes into shuffles if all operands were either extract_vector_elt or undef. This patch improves that logic and teaches the DAGCombiner how to deal with build_vector dag nodes where one or more operands are zero. A build_vector dag node with some zero operands is turned into a shuffle only if the resulting shuffle mask is legal for the target. llvm-svn: 222536
* [x86] Teach the x86 vector shuffle lowering to detect mergable 128-bitChandler Carruth2014-11-211-4/+154
| | | | | | | | | | | | | | | | | | | lanes. By special casing these we can often either reduce the total number of shuffles significantly or reduce the number of (high latency on Haswell) AVX2 shuffles that potentially cross 128-bit lanes. Even when these don't actually cross lanes, they have much higher latency to support that. Doing two of them and a blend is worse than doing a single insert across the 128-bit lanes to blend and then doing a single interleaved shuffle. While this seems like a narrow case, it kept cropping up on me and the difference is *huge* as you can see in many of the test cases. I first hit this trying to perfectly fix the interleaving shuffle patterns used by Halide for AVX2. llvm-svn: 222533
* [DAG] Refactor the shuffle combining logic in DAGCombiner. NFC.Andrea Di Biagio2014-11-211-153/+73
| | | | | | | | This patch simplifies the logic that combines a pair of shuffle nodes into a single shuffle if there is a legal mask. Also added comments to better describe the algorithm. No functional change intended. llvm-svn: 222522
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