summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Fixing warnings in the MSVC build. No functional changes intended.Aaron Ballman2014-04-015-42/+42
| | | | llvm-svn: 205301
* [mips] Extend ParseJumpTarget to support the full symbol expression syntax.Daniel Sanders2014-04-011-27/+6
| | | | | | | | | | | | | | | | Summary: This should fix the issues the D3222 caused in lld. Testcase is based on the one that failed in the buildbot. Depends on D3233 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3234 llvm-svn: 205298
* [mips] Use AsmLexer::peekTok() to resolve the conflict between $reg and $symDaniel Sanders2014-04-011-15/+10
| | | | | | | | | | | | | | | Summary: Parsing registers no longer consume the $ token before it's confirmed whether it really has a register or not, therefore it's no longer impossible to match symbols if registers were tried first. Depends on D3232 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3233 llvm-svn: 205297
* [mips] Hoist Parser.Lex() calls out of MatchAnyRegisterNameWithoutDollar()Daniel Sanders2014-04-011-9/+8
| | | | | | | | | | | | | | | Summary: No functional change Depends on D3222 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3232 llvm-svn: 205295
* ARM64: add patterns for more lane-wise ld1/st1 operations.Tim Northover2014-04-012-59/+80
| | | | llvm-svn: 205294
* ARM64: fix bug in ld3r (1d) SelectionDAG.Tim Northover2014-04-011-1/+1
| | | | llvm-svn: 205293
* [mips] Rewrite MipsAsmParser and MipsOperand.Daniel Sanders2014-04-018-1017/+864
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
* [x86] Do not convert to cmp32 for Atom arch by Sergey OkunevAlexey Volkov2014-04-011-4/+6
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D2824 llvm-svn: 205288
* DebugInfo: Avoid creating unnecessary/empty line tables and remove the ↵David Blaikie2014-04-014-17/+22
| | | | | | | | | | | | special case of '0' in DwarfCompileUnit::initStmtList by just always using a label difference This moves one case of raw text checking down into the MCStreamer interfaces in the form of a virtual function, even if we ultimately end up consolidating on the one-or-many line tables issue one day, this is nicer in the interim. This just generally streamlines a bunch of use cases into a common code path. llvm-svn: 205287
* DebugInfo: Emit relocation to debug_line section when emitting asm for asmDavid Blaikie2014-04-014-32/+44
| | | | | | | | | | | | | | I don't think this is reachable by any frontend (why would you transform asm to asm+debug info?) but it helps tidy up some of this code, avoid the weird special case of "emit the first CU, store the label, then emit the rest" in MCDwarfLineTable::Emit by instead having the DWARF-for-assembly case use the same codepath as DwarfDebug.cpp, by registering the label of the debug_line section, thus causing it to be emitted. (with a special case in asm output to just emit the label since asm output uses the .loc directives, etc, rather than the debug_loc directly) llvm-svn: 205286
* LTO type uniquing: store the Decl field of a DIImportedEntity as a DIRef.Adrian Prantl2014-04-013-5/+5
| | | | | | | | | | No other functionality changes, DIBuilder testcase is included in a paired CFE commit. This relaxes the assertion in isScopeRef to also accept subclasses of DIScope. llvm-svn: 205279
* Move partial/runtime unrolling late in the pipelineHal Finkel2014-03-312-1/+8
| | | | | | | | | | | | | | | | The generic (concatenation) loop unroller is currently placed early in the standard optimization pipeline. This is a good place to perform full unrolling, but not the right place to perform partial/runtime unrolling. However, most targets don't enable partial/runtime unrolling, so this never mattered. However, even some x86 cores benefit from partial/runtime unrolling of very small loops, and follow-up commits will enable this. First, we need to move partial/runtime unrolling late in the optimization pipeline (importantly, this is after SLP and loop vectorization, as vectorization can drastically change the size of a loop), while keeping the full unrolling where it is now. This change does just that. llvm-svn: 205264
* Revert "SLPVectorizer: Ignore users that are insertelements we can ↵Arnold Schwaighofer2014-03-311-65/+30
| | | | | | | | | | | | | | reschedule them" This reverts commit r205018. Conflicts: lib/Transforms/Vectorize/SLPVectorizer.cpp test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll This is breaking libclc build. llvm-svn: 205260
* [Stackmaps] Update the stackmap format to use 64-bit relocations for the ↵Juergen Ributzka2014-03-311-20/+36
| | | | | | | | | | | | function address and properly align all entries. This commit updates the stackmap format to version 1 to indicate the reorganizaion of several fields. This was done in order to align stackmap entries to their natural alignment and to minimize padding. Fixes <rdar://problem/16005902> llvm-svn: 205254
* [X86] Adjust cost of FP_TO_UINT v4f64->v4i32 as wellAdam Nemet2014-03-311-0/+1
| | | | | | | | | Pretty obvious follow-on to r205159 to also handle conversion from double besides float. Fixes <rdar://problem/16373208> llvm-svn: 205253
* R600/SI: Remove leftover pattern splitting 64-bit ors.Matt Arsenault2014-03-311-8/+0
| | | | | | | It's now matched to the scalar 64-bit or and split later if necessary.' llvm-svn: 205252
* Register allocator: set CSRFirstUseCost to 5 for ARM64.Manman Ren2014-03-311-0/+7
| | | | | | | | | | | | A value of 5 means if we have a split or spill option that has a really low cost (1 << 14 is the entry frequency), we will choose to spill or split the really cold path before using a callee-saved register. This gives us the performance benefit on SPECInt2k and is also conservative. rdar://16162005 llvm-svn: 205248
* Change shouldSplitVectorElementType to better match the description.Matt Arsenault2014-03-315-7/+7
| | | | | | Pass the entire vector type, and not just the element. llvm-svn: 205247
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-314-18/+37
| | | | llvm-svn: 205244
* Add an optional ability to expand larger BUILD_VECTORs with shufflesHal Finkel2014-03-311-20/+117
| | | | | | | | | | | | | | | | | | | | | | | This adds the ability to expand large (meaning with more than two unique defined values) BUILD_VECTOR nodes in terms of SCALAR_TO_VECTOR and (legal) vector shuffles. There is now no limit of the size we are capable of expanding this way, although we don't currently do this for vectors with many unique values because of the default implementation of TLI's shouldExpandBuildVectorWithShuffles function. There is currently no functional change to any existing targets because the new capabilities are not used unless some target overrides the TLI shouldExpandBuildVectorWithShuffles function. As a result, I've not included a test case for the new functionality in this commit, but regression tests will (at least) be added soon when I commit support for the PPC QPX vector instruction set. The benefit of committing this now is that it makes the shouldExpandBuildVectorWithShuffles callback, which had to be added for other reasons regardless, fully functional. I suspect that other targets will also benefit from tuning the heuristic. llvm-svn: 205243
* R600: Compute masked bits for min and maxMatt Arsenault2014-03-311-0/+44
| | | | llvm-svn: 205242
* Don't relocate with sections if there might be a paired relocation.Rafael Espindola2014-03-311-2/+18
| | | | llvm-svn: 205240
* Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot ↵Daniel Sanders2014-03-318-864/+1017
| | | | | | | | errors in lld tests. It's currently unable to parse 'sym + imm' without surrounding parenthesis. llvm-svn: 205237
* R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.Matt Arsenault2014-03-313-1/+33
| | | | llvm-svn: 205236
* R600: Add target nodes for BFM and BFIMatt Arsenault2014-03-315-3/+14
| | | | llvm-svn: 205235
* ARM: fix typoSaleem Abdulrasool2014-03-311-1/+1
| | | | llvm-svn: 205233
* [PowerPC] Don't ever expand BUILD_VECTOR of v2i64 with shufflesHal Finkel2014-03-312-0/+14
| | | | | | | If we have two unique values for a v2i64 build vector, this will always result in two vector loads if we expand using shuffles. Only one is necessary. llvm-svn: 205231
* Add a TLI hook to control when BUILD_VECTOR might be expanded using shufflesHal Finkel2014-03-311-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two general methods for expanding a BUILD_VECTOR node: 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle them together. 2. Build the vector on the stack and then load it. Currently, we use a fixed heuristic: If there are only one or two unique defined values, then we attempt an expansion in terms of SCALAR_TO_VECTOR and vector shuffles (provided that the required shuffle mask is legal). Otherwise, always expand via the stack. Even when SCALAR_TO_VECTOR is not legal, this can still be a good idea depending on what tricks the target can play when lowering the resulting shuffle. If the target can't do anything special, however, and if SCALAR_TO_VECTOR is expanded via the stack, this heuristic leads to sub-optimal code (two stack loads instead of one). Because only the target knows whether the SCALAR_TO_VECTORs and shuffles for a build vector of a particular type are likely to be optimial, this adds a new TLI function: shouldExpandBuildVectorWithShuffles which takes the vector type and the count of unique defined values. If this function returns true, then method (1) will be used, subject to the constraint that all of the necessary shuffles are legal (as determined by isShuffleMaskLegal). If this function returns false, then method (2) is always used. This commit does not enhance the current code to support expanding a build_vector with more than two unique values using shuffles, but I'll commit an implementation of the more-general case shortly. llvm-svn: 205230
* [mips] Rewrite MipsAsmParser and MipsOperand.Daniel Sanders2014-03-318-1017/+864
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205229
* Disable each MachineFunctionPass for 'optnone' functions, unless thatPaul Robinson2014-03-3114-0/+42
| | | | | | | pass normally runs at optimization level None, or is part of the register allocation pipeline. llvm-svn: 205228
* [PowerPC] Correct P7 dispatch unit allocation for vector instructionsHal Finkel2014-03-311-16/+8
| | | | llvm-svn: 205222
* This patch fixes LTO's RecordStreamer so that it records symbols in the MCExprTom Roeder2014-03-311-0/+1
| | | | | | | | | | | part of an asm .symver directive as being used. This prevents referenced functions from being internalized and deleted. Without the patch to LTOModule.cpp, the test case will produce the error: LLVM ERROR: A @@ version cannot be undefined. llvm-svn: 205221
* Support: generalise object type handling for WindowsSaleem Abdulrasool2014-03-311-7/+15
| | | | | | | | | This generalises the object file type parsing to all Windows environments. This is used by cygwin as well as MSVC environments for MCJIT. This also makes the triple more similar to Chandler's suggestion of a separate field for the object file format. llvm-svn: 205219
* PR19099 - revert r203483Eli Bendersky2014-03-312-48/+16
| | | | | | | Now that r205212 was committed, r203483 is no longer necessary; it was a temporary workaround that only handled a small number of the problematic cases. llvm-svn: 205216
* ARM: change parameter names of the ELFARMAsmBackend constructorChristian Pirker2014-03-311-2/+2
| | | | | | | I removed the underscore at the beginning of the parameter name, because of a comment from Tim. llvm-svn: 205215
* Test commit.Robert Khasanov2014-03-311-2/+2
| | | | llvm-svn: 205214
* [mips] Fix use of uninitialized value reported by the ↵Daniel Sanders2014-03-311-0/+2
| | | | | | sanitizer-x86_64-linux-bootstrap buildbot llvm-svn: 205213
* Fix for PR19099 - NVPTX produces invalid symbol names.Eli Bendersky2014-03-314-0/+89
| | | | | | | | This is a more thorough fix for the issue than r203483. An IR pass will run before NVPTX codegen to make sure there are no invalid symbol names that can't be consumed by the ptxas assembler. llvm-svn: 205212
* ARM64: add extra patterns for scalar shiftsTim Northover2014-03-311-6/+12
| | | | llvm-svn: 205209
* ARM64: add extra scalar neg pattern & tests.Tim Northover2014-03-311-1/+2
| | | | llvm-svn: 205208
* ARM64: add patterns for scalar sqdmlal & sqdmlsl.Tim Northover2014-03-311-0/+9
| | | | llvm-svn: 205207
* ARM64: add more patterns for commuted fmsub operations.Tim Northover2014-03-311-0/+8
| | | | llvm-svn: 205206
* ARM64: shuffle patterns around for fmin/fmax & add tests.Tim Northover2014-03-311-8/+8
| | | | llvm-svn: 205205
* ARM64: add more scalar patterns for usqadd & suqadd.Tim Northover2014-03-311-7/+11
| | | | llvm-svn: 205204
* ARM64: add more scalar patterns for reciprocal ops.Tim Northover2014-03-311-0/+15
| | | | llvm-svn: 205203
* ARM64: add i64 scalar pattern for @llvm.arm64.absTim Northover2014-03-312-7/+3
| | | | | | This will be used by the Clang front-end code for vabsd_s64. llvm-svn: 205202
* [mips] Implement missing relocations in the integrated assembler.Daniel Sanders2014-03-311-0/+8
| | | | | | | | | | %got_hi, %got_lo, %call_hi, %call_lo, %higher, and %highest are now recognised by MipsAsmParser::getVariantKind(). To prevent future issues with missing entries in this StringSwitch, I've added an assertion to the default case. llvm-svn: 205200
* Revert r205194 - [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.Daniel Sanders2014-03-311-0/+1
| | | | | | There's a couple additional bits I missed. llvm-svn: 205195
* [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.Daniel Sanders2014-03-311-1/+0
| | | | llvm-svn: 205194
* Capitalize the D in parseDirectiveGpDWord.Rafael Espindola2014-03-311-4/+4
| | | | | | | | DWord seems to be the canonical way to camel case dword in llvm. Thanks to Daniel Sander for noticing. llvm-svn: 205191
OpenPOWER on IntegriCloud