summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Fix a null pointer dereference in llvm-pdbutil pretty.Zachary Turner2017-06-121-2/+3
| | | | | | | | Static data members were causing a problem because I mistakenly assumed all members would affect a class's layout and so the Layout member would be non-null. llvm-svn: 305229
* SplitKit: Fix partially live subreg splittingMatthias Braun2017-06-121-2/+1
| | | | | | | | | Fix thinko/typo in subreg aware liverange splitting logic. I'm not sure how to write a proper testcase for this. The original problem only happens on an out-of-tree target. Forcing subreg enabled targets to spill and split in a predictable way is near impossible. llvm-svn: 305228
* IR: Replace the "Linker Options" module flag with "llvm.linker.options" ↵Peter Collingbourne2017-06-126-44/+41
| | | | | | | | | | named metadata. The new metadata is easier to manipulate than module flags. Differential Revision: https://reviews.llvm.org/D31349 llvm-svn: 305227
* [llvm-ar] Make llvm-lib behave more like the MSVC archiverReid Kleckner2017-06-121-6/+8
| | | | | | | | | | | | | | | | | | | | | | Summary: Use the filepath used to open the archive member as the archive member name instead of the file basename. This path might be absolute or relative. This is important because the archive member name will show up in the PDB, and we want our PDBs to look as much like MSVC's as possible. This also helps avoid an issue in our PDB module descriptor writing code, which assumes that all module names are unique. Relative paths still aren't guaranteed to be unique, but they're much better than basenames, which definitely aren't unique. Reviewers: ruiu, zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33575 llvm-svn: 305223
* Same expressions on both sides of the returnSylvestre Ledru2017-06-121-1/+1
| | | | | | | | | | | | | | | | | | | Summary: I guess we want PointerToMemberFunction & PointerToDataMember Fix coverity cid 1376038 Reviewers: zturner Reviewed By: zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34110 llvm-svn: 305219
* [PowerPC] Match vec_revb builtins to P9 instructions.Tony Jiang2017-06-124-7/+105
| | | | | | | | | | | | Power9 has instructions that will reverse the bytes within an element for all sizes (half-word, word, double-word and quad-word). These can be used for the vec_revb builtins in altivec.h. However, we implement these to match vector shuffle nodes as that will cover both the builtins and vector shuffles that occur in the SDAG through other means. Differential Revision: https://reviews.llvm.org/D33690 llvm-svn: 305214
* [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.Tony Jiang2017-06-124-5/+51
| | | | | | | | | | | Note that if we need the result of both the divide and the modulo then we compute the modulo based on the result of the divide and not using the new hardware instruction. Commit on behalf of STEFAN PINTILIE. Differential Revision: https://reviews.llvm.org/D33940 llvm-svn: 305210
* AMDGPU: Don't add same implicit use multiple timesMatt Arsenault2017-06-121-4/+2
| | | | | | | For the last component, the same register use was added as an implicit use and another implicit kill use. llvm-svn: 305205
* [SelectionDAG] Allow sin/cos -> sincos optimization on GNU triples w/ just ↵Geoff Berry2017-06-121-14/+1
| | | | | | | | | | | | | | | | | | | | | -fno-math-errno Summary: This change enables the sin(x) cos(x) -> sincos(x) optimization on GNU target triples. This optimization was being inhibited when -ffast-math wasn't set because sincos in GLibC does not set errno, while sin and cos do. However, this optimization will only run if the attributes on the sin/cos calls include readnone, which is how clang represents the fact that it doesn't care about the errno values set by these functions (via the -fno-math-errno flag). Reviewers: hfinkel, bogner Subscribers: mcrosier, javed.absar, llvm-commits, paul.redmond Differential Revision: https://reviews.llvm.org/D32921 llvm-svn: 305204
* AMDGPU: Teach isLegalAddressingMode about flat offsetsMatt Arsenault2017-06-121-3/+11
| | | | | | | Also fix reporting r+r as a valid addressing mode without offsets. llvm-svn: 305203
* AMDGPU: Start selecting flat instruction offsetsMatt Arsenault2017-06-122-18/+42
| | | | llvm-svn: 305201
* AMDGPU: Verify that flat offsets aren't used pre-GFX9Matt Arsenault2017-06-121-2/+11
| | | | | | | For convenience the operand is always present in the instruction, but it isn't valid to use except on GFX9. llvm-svn: 305200
* [Falkor] Enable SW Prefetch.Haicheng Wu2017-06-121-0/+4
| | | | | | | | SW prefetch is good for Falkor. Differential Revision: http://reviews.llvm.org/D34084 llvm-svn: 305199
* AMDGPU: Start adding offset fields to flat instructionsMatt Arsenault2017-06-125-25/+94
| | | | llvm-svn: 305194
* StackColoring: smarter check for slot overlapThan McIntosh2017-06-121-60/+177
| | | | | | | | | | | | | | | | | | | | | | | Summary: The old check for slot overlap treated 2 slots `S` and `T` as overlapping if there existed a CFG node in which both of the slots could possibly be active. That is overly conservative and caused stack blowups in Rust programs. Instead, check whether there is a single CFG node in which both of the slots are possibly active *together*. Fixes PR32488. Patch by Ariel Ben-Yehuda <ariel.byd@gmail.com> Reviewers: thanm, nagisa, llvm-commits, efriedma, rnk Reviewed By: thanm Subscribers: dotdash Differential Revision: https://reviews.llvm.org/D31583 llvm-svn: 305193
* [DAG] add helper to bind memop chains; NFCISanjay Patel2017-06-124-49/+23
| | | | | | | | | | This step is just intended to reduce code duplication rather than change any functionality. A follow-up would be to replace PPCTargetLowering::spliceIntoChain() usage with this new helper. Differential Revision: https://reviews.llvm.org/D33649 llvm-svn: 305192
* [InstCombine] lshr (sext iM X to iN), N-M --> zext (ashr X, min(N-M, M-1)) to iNSanjay Patel2017-06-121-4/+10
| | | | | | | | | | | | | | | | | | | This is a follow-up to https://reviews.llvm.org/D33879 / https://reviews.llvm.org/rL304939 , and was discussed in https://reviews.llvm.org/D33338. We prefer this form because a narrower shift may be cheaper, and we can more easily fold a zext than a sext. http://rise4fun.com/Alive/slVe Name: shz %s = sext i8 %x to i12 %r = lshr i12 %s, 4 => %a = ashr i8 %x, 4 %r = zext i8 %a to i12 llvm-svn: 305190
* Const correctness for TTI::getRegisterBitWidthDaniel Neilson2017-06-1210-10/+10
| | | | | | | | | | | | | | Summary: The method TargetTransformInfo::getRegisterBitWidth() is declared const, but the type erasing implementation classes (TargetTransformInfo::Concept & TargetTransformInfo::Model) that were introduced by Chandler in https://reviews.llvm.org/D7293 do not have the method declared const. This is an NFC to tidy up the const consistency between TTI and its implementation. Reviewers: chandlerc, rnk, reames Reviewed By: reames Subscribers: reames, jfb, arsenm, dschuff, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D33903 llvm-svn: 305189
* [X86][SSE] Change memop fragment to inherit from vec128load with local ↵Simon Pilgrim2017-06-121-8/+4
| | | | | | | | | | | | alignment controls First possible step towards merging SSE/AVX memory folding pattern fragments. Also allows us to remove the duplicate non-temporal load logic. Differential Revision: https://reviews.llvm.org/D33902 llvm-svn: 305184
* [AVX-512] Add VPCONFLICT and VPLZCNT to load folding tables.Craig Topper2017-06-121-0/+36
| | | | llvm-svn: 305180
* Address http://bugs.llvm.org/pr32207 by making BannerPrinted local to ↵Yaron Keren2017-06-121-4/+4
| | | | | | | | | | runOnSCC and skipping banner for function declarations. Reviewed By: Mehdi AMINI Differential Revision: https://reviews.llvm.org/D34086 llvm-svn: 305179
* [x86] use vperm2f128 rather than vinsertf128 when there's a chance to fold a ↵Sanjay Patel2017-06-111-9/+13
| | | | | | | | | | | | | | | | | | | | | 32-byte load I was looking closer at the x86 test diffs in D33866, and the first change seems like it shouldn't happen in the first place. So this patch will resolve that. Using Agner's tables and AMD docs, vperm2f128 and vinsertf128 have identical timing for any given CPU model, so we should be able to interchange those without affecting perf. But as we can see in some of the diffs here, using vperm2f128 allows load folding, so we should take that opportunity to reduce code size and register pressure. A secondary advantage is making AVX1 and AVX2 codegen more similar. Given that vperm2f128 was introduced with AVX1, we should be selecting it in all of the same situations that we would with AVX2. If there's some reason that an AVX1 CPU would not want to use this instruction, that should be fixed up in a later pass. Differential Revision: https://reviews.llvm.org/D33938 llvm-svn: 305171
* [PartialInlining] Support shrinkwrap life_range markersXinliang David Li2017-06-111-16/+203
| | | | | | Differential Revision: http://reviews.llvm.org/D33847 llvm-svn: 305170
* Fix unused variable warning on non-debug EXPENSIVE_CHECKS buildsSimon Pilgrim2017-06-111-1/+2
| | | | llvm-svn: 305163
* [DAGCombine] Make sure we check the ResNo from UADDO before combiningAmaury Sechet2017-06-111-1/+2
| | | | | | | | | | | | Summary: UADDO has 2 result, and one must check the result no before doing any kind of combine. Without it, the transform is invalid. Reviewers: joerg Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34088 llvm-svn: 305162
* [MemorySSA] preservesAll() implies preserves<MemorySSA>(). NFCI.Davide Italiano2017-06-111-1/+0
| | | | llvm-svn: 305160
* dwarfdump: Handle relocs to zlib (.zdebug*) compressed sectionsDavid Blaikie2017-06-101-1/+1
| | | | llvm-svn: 305152
* Fix a ubsan failure introduced by r305092Vedant Kumar2017-06-101-2/+2
| | | | | | | | | | | | lib/Object/WindowsResource.cpp:578:3: runtime error: store to misaligned address 0x7fa09aedebbe for type 'unsigned int', which requires 4 byte alignment 0x7fa09aedebbe: note: pointer points here 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ^ llvm-svn: 305149
* [EarlyCSE] Add option to use MemorySSA for function simplification run of ↵Geoff Berry2017-06-102-2/+10
| | | | | | | | | | | | | | | | EarlyCSE (off by default). Summary: Use MemorySSA for memory dependency checking in the EarlyCSE pass at the start of the function simplification portion of the pipeline. We rely on the fact that GVNHoist runs just after this pass of EarlyCSE to amortize the MemorySSA construction cost since GVNHoist uses MemorySSA and EarlyCSE preserves it. This is turned off by default. A follow-up change will turn it on to allow for easier reversion in case it breaks something. llvm-svn: 305146
* Added llvm_unreachable as ReportError cannot be specified as noreturn.Galina Kistanova2017-06-101-0/+1
| | | | llvm-svn: 305143
* AMDGPU : Fix ISA Version Definitions.Wei Ding2017-06-104-27/+99
| | | | | | Differential Revision: http://reviews.llvm.org/D28531 llvm-svn: 305137
* [InstSimplify] Don't constant fold or DCE calls that are marked nobuiltinAndrew Kaylor2017-06-097-24/+36
| | | | | | Differential Revision: https://reviews.llvm.org/D33737 llvm-svn: 305132
* [CGP] add a reference to DataLayout in MemCmpExpansion; NFCISanjay Patel2017-06-091-20/+22
| | | | | | | | We're currently passing endian-ness around as a param (and not uniformly), so this eliminates the need for that. I'd like to add a constant fold call too, and that requires a DL. llvm-svn: 305129
* [AArch64] Add fallback in FastISel fp16 conversionsI-Jui (Ray) Sung2017-06-091-1/+5
| | | | | | | | | | | | | | | | | Summary: - Fix assertion failures on F16 to/from int types in FastISel by falling back to regular ISel - Add a testcase of various conversion cases with FastISel (-O0) Reviewers: kristof.beyls, jmolloy, SjoerdMeijer Reviewed By: SjoerdMeijer Subscribers: SjoerdMeijer, llvm-commits, srhines, pirama, aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D33734 llvm-svn: 305127
* [LVI] Fix spelling error in comment. NFCCraig Topper2017-06-091-1/+1
| | | | llvm-svn: 305115
* [LVI] Const correct and rename the LVILatticeVal parameter to ↵Craig Topper2017-06-091-9/+8
| | | | | | | | getPredicateResult. NFC Previously it was non-const reference named Result which would tend to make someone think that it was an outparam when really its an input. llvm-svn: 305114
* [pdb] Support CoffSymbolRVA debug subsection.Zachary Turner2017-06-094-0/+93
| | | | llvm-svn: 305108
* [SROA] Fix APInt size when load/store have different address spaceYaxun Liu2017-06-091-7/+12
| | | | | | | | | | | | | | | Currently there is a bug in SROA::presplitLoadsAndStores which causes assertion in GEPOperator::accumulateConstantOffset. Basically it does not consider the situation that the pointer operand of load or store may be in a non-zero address space and its size may be different from the size of a pointer in address space 0. This patch fixes assertion when compiling Blender Cycles kernels for amdgpu backend. Diffferential Revision: https://reviews.llvm.org/D33298 llvm-svn: 305107
* [Sink] Fix predicate in legality checkKeno Fischer2017-06-091-1/+1
| | | | | | | | | | | | | | | | | | Summary: isSafeToSpeculativelyExecute is the wrong predicate to use here. All that checks for is whether it is safe to hoist a value due to unaligned/un-dereferencable accesses. However, not only are we doing sinking rather than hoisting, our concern is that the location we're loading from may have been modified. Instead forbid sinking any load across a critical edge. Reviewers: majnemer Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D33179 llvm-svn: 305102
* [AMDGPU] Add intrinsics for alignbit and alignbyte instructionsStanislav Mekhanoshin2017-06-091-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D34046 llvm-svn: 305098
* Allow VarStreamArray to use stateful extractors.Zachary Turner2017-06-095-16/+15
| | | | | | | | | | | Previously extractors tried to be stateless with any additional context information needed in order to parse items being passed in via the extraction method. This led to quite cumbersome implementation challenges and awkwardness of use. This patch brings back support for stateful extractors, making the implementation and usage simpler. llvm-svn: 305093
* Implement COFF emission for parsed Windows Resource ( .res) files.Eric Beckmann2017-06-091-9/+507
| | | | | | | | | | | | Summary: Add the WindowsResourceCOFFWriter class for producing the final COFF after all parsing is done. Reviewers: hiraditya!, zturner, ruiu Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34020 llvm-svn: 305092
* [X86][SSE] Add support for PACKSS nodes to faux shuffle extractionSimon Pilgrim2017-06-091-6/+32
| | | | | | If the inputs won't saturate during packing then we can treat the PACKSS as a truncation shuffle llvm-svn: 305091
* [LazyValueInfo] Don't run the more complex predicate handling code for EQ ↵Craig Topper2017-06-091-8/+8
| | | | | | | | | | | | | | | | | | | and NE in getPredicateResult Summary: Unless I'm mistaken, the special handling for EQ/NE should cover everything and there is no reason to fallthrough to the more complex code. For that matter I'm not sure there's any reason to special case EQ/NE other than avoiding creating temporary ConstantRanges. This patch moves the complex code into an else so we only do it when we are handling a predicate other than EQ/NE. Reviewers: anna, reames, resistor, Farhana Reviewed By: anna Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34000 llvm-svn: 305086
* [Hexagon] Fixes and updates to the selection patternsKrzysztof Parzyszek2017-06-091-28/+52
| | | | | | | | - Add some missing patterns. - Use C4_cmplte in branch patterns. - Fix signedness of immediate operand in M2_accii. llvm-svn: 305085
* SelectionDAG: Remove deleted nodes from legalized set to avoid clash with ↵Zvi Rackover2017-06-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | newly created nodes Summary: During DAG legalization loop in SelectionDAG::Legalize(), bookkeeping of the SDNodes that were already legalized is implemented with SmallPtrSet (LegalizedNodes). This kind of set stores only pointers to objects, not the objects themselves. Unfortunately, if SDNode is deleted during legalization for some reason, LegalizedNodes set is not informed about this fact. This wouldn’t be so bad, if SelectionDAG wouldn’t reuse space deallocated after deletion of unused nodes, for creation of new ones. Because of this, new nodes, created during legalization often can have pointers identical to ones that have been previously legalized, added to the LegalizedNodes set, and deleted afterwards. This in turn causes, that newly created nodes, sharing the same pointer as deleted old ones, are present in LegalizedNodes *already at the moment of creation*, so we never call Legalize on them. The fix facilitates the fact, that DAG notifies listeners about each modification. I have registered DAGNodeDeletedListener inside SelectionDAG::Legalize, with a callback function that removes any pointer of any deleted SDNode from the LegalizedNodes set. With this modification, LegalizeNodes set does not contain pointers to nodes that were deleted, so newly created nodes can always be inserted to it, even if they share pointers with old deleted nodes. Patch by pawel.szczerbuk@intel.com The issue this patch addresses causes failures in an out-of-tree target, and i was not able to create a reproducer for an in-tree target, hence there is no test-case. Reviewers: delena, spatel, RKSimon, hfinkel, davide, qcolombet Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33891 llvm-svn: 305084
* Reland "[SelectionDAG] Enable target specific vector scalarization of calls ↵Simon Dardis2017-06-0910-81/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and returns" By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown, backends can request that LLVM to scalarize vector types for calls and returns. The MIPS vector ABI requires that vector arguments and returns are passed in integer registers. With SelectionDAG's new hooks, the MIPS backend can now handle LLVM-IR with vector types in calls and returns. E.g. 'call @foo(<4 x i32> %4)'. Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for calls and returns if vector types were not legal. If vector types were legal, a single 128bit vector argument would be assigned to a single 32 bit / 64 bit integer register. By teaching the MIPS backend to inspect the original types, it can now implement the MIPS vector ABI which requires a particular method of scalarizing vectors. Previously, the MIPS backend relied on clang to scalarize types such as "call @foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3, i32 inreg %4)". This patch enables the MIPS backend to take either form for vector types. The previous version of this patch had a "conditional move or jump depends on uninitialized value". Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur Differential Revision: https://reviews.llvm.org/D27845 llvm-svn: 305083
* [SimplifyLibCalls] fix formatting; NFCSanjay Patel2017-06-091-1/+1
| | | | llvm-svn: 305081
* [ValueTracking] fix typo; NFCSanjay Patel2017-06-091-1/+1
| | | | llvm-svn: 305080
* [AMDGPU] Fix for issue in alloca to vector promotion passDavid Stuttard2017-06-091-6/+12
| | | | | | | | | | | | | | | Summary: Alloca promotion pass not dealing with non-canonical input Added some additional checks so the pass simply backs-off forms it can't deal with (non-canonical) Also added some test cases in non-canonical form to check that it no longer crashes Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tpr, t-tye Differential Revision: https://reviews.llvm.org/D31710 llvm-svn: 305079
OpenPOWER on IntegriCloud