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* [IR] Add a `makeNoWrapRegion` method to `ConstantRange`Sanjoy Das2015-10-221-0/+53
| | | | | | | | | | | | Summary: This will be used in a future change to ScalarEvolution. Reviewers: hfinkel, reames, nlewycky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13612 llvm-svn: 250975
* [OperandBundles] Make function attributes conservatively correctSanjoy Das2015-10-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This makes attribute accessors on `CallInst` and `InvokeInst` do the (conservatively) right thing. This essentially involves, in some cases, *not* falling back querying the attributes on the called `llvm::Function` when operand bundles are present. Attributes locally present on the `CallInst` or `InvokeInst` will still override operand bundle semantics. The LangRef has been amended to reflect this. Note: this change does not do anything prevent `-function-attrs` from inferring `CallSite` local attributes after inspecting the called function -- that will be done as a separate change. I've used `-adce` and `-early-cse` to test these changes. There is nothing special about these passes (and they did not require any changes) except that they seemed be the easiest way to write the tests. This change does not add deal with `argmemonly`. That's a later change because alias analysis requires a related fix before `argmemonly` can be tested. Reviewers: reames, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13961 llvm-svn: 250973
* WebAssembly: fix more syntaxJF Bastien2015-10-222-5/+5
| | | | | | | br_if shouldn't start with a dot. div and rem went from prefix u/s to suffix. llvm-svn: 250972
* Add missing load/store flags to thumb2 instructions.Pete Cooper2015-10-221-1/+4
| | | | | | | | | | | | | | | | | | These were the cause of a verifier error when building 7zip with -verify-machineinstrs. Running 'make check' with the verifier triggered the same error on the test here so i've updated the test to run the verifier on one of its runs instead of adding a new one. While looking at this code, there was a stale comment that these instructions were only used for disassembly. This probably used to be the case, but they are now used in the 'ARM load / store optimization pass' too. This reapplies r242300 which was reverted in r242428 due to bot failures. Ultimately those failures were spurious and completely unrelated to this commit. I reverted this at the time because it was thought to be at fault. llvm-svn: 250969
* [WinEH] Remove extraneous call to emitEHRegistrationOffsetLabelDavid Majnemer2015-10-211-1/+0
| | | | | | It's a relic from the earlier implementation, let's remove it. llvm-svn: 250964
* AMDGPU: Fix adding redundant m0 usesMatt Arsenault2015-10-211-2/+0
| | | | | | BuildMI already adds these since they are defined correctly now. llvm-svn: 250961
* AMDGPU: Fix verifier error in SIFoldOperandsMatt Arsenault2015-10-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | There may be other use operands that also need their kill flags cleared. This happens in a few tests when SIFoldOperands is moved after PeepholeOptimizer. PeepholeOptimizer rewrites cases that look like: %vreg0 = ... %vreg1 = COPY %vreg0 use %vreg1<kill> %vreg2 = COPY %vreg0 use %vreg2<kill> to use the earlier source to %vreg0 = ... use %vreg0 use %vreg0 Currently SIFoldOperands sees the copied registers, so there is only one use. So far I haven't managed to come up with a test that currently has multiple uses of a foldable VGPR -> VGPR copy. llvm-svn: 250960
* AMDGPU: Split DiagnosticInfoUnsupported into its own fileMatt Arsenault2015-10-214-41/+76
| | | | llvm-svn: 250959
* AMDGPU: Simplify VOP3 operand legalization.Matt Arsenault2015-10-213-42/+58
| | | | | | | | | | | | | | | | | | | | | | | | | This was checking for a variety of situations that should never happen. This saves a tiny bit of compile time. We should not be selecting instructions with invalid operands in the first place. Most of the time for registers copys are inserted to the correct operand register class. For VOP3, since all operand types are supported and literal constants never are, we just need to verify the constant bus requirements (all immediates should be legal inline ones). The only possibly tricky case to maybe worry about is if when legalizing operands in moveToVALU with s_add_i32 and similar instructions. If the original s_add_i32 had a literal constant and we need to replace it with v_add_i32_e64 we would have an unsupported literal operand. However, I don't think we should worry about that because SIFoldOperands should handle folding literal constant operands into the SALU instructions based on the uses. At SIFoldOperands time, the legality and profitability of operand types is a bit different. llvm-svn: 250951
* AMDGPU: Fix not checking implicit operands in verifyInstructionMatt Arsenault2015-10-211-15/+29
| | | | | | | When verifying constant bus restrictions, this wasn't catching uses in implicit operands. llvm-svn: 250948
* Use numeric_limits instead of LLONG_MAXMatt Arsenault2015-10-211-2/+2
| | | | | | | This is a build fix for configurations where LLONG_MAX is not defined in system headers. llvm-svn: 250946
* LegalizeDAG: Implement promote for build_vectorMatt Arsenault2015-10-211-0/+30
| | | | | | | | | | This will be used in future commits for AMDGPU to promote operations on i64 vectors into operations on 32-bit vector components. This will be used / tested in future AMDGPU commits. llvm-svn: 250945
* [Verifier] Minor comment update, NFCVedant Kumar2015-10-211-2/+1
| | | | llvm-svn: 250943
* [RuntimeDyld] Ignore ST_FILE symbols when constructing GlobalSymbolTableKeno Fischer2015-10-211-1/+2
| | | | | | | | | | | | | | Summary: ELF's STT_File symbols may overlap with regular globals in other files, so we should ignore them here in order to avoid having bogus entries in the symbol table that confuse us when resolving relocations. Reviewers: lhames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13888 llvm-svn: 250942
* Drop assert that a call with struct return goes to a function with sretJoerg Sonnenberger2015-10-211-2/+2
| | | | | | | attribute. Clang incorrectly misses it on __muldc3 and friends and the type system doesn't include it properly either. llvm-svn: 250938
* Silence Visual C++ warning in function summary parsing code (NFC)Teresa Johnson2015-10-211-0/+1
| | | | llvm-svn: 250929
* [x86] move recursive add match for LEA to helper function; NFCISanjay Patel2015-10-211-30/+37
| | | | llvm-svn: 250926
* [SimplifyCFG] Don't use-after-free an SSA valueDavid Majnemer2015-10-211-1/+2
| | | | | | | | | SimplifyTerminatorOnSelect didn't consider the possibility that the condition might be related to one of PHI nodes. This fixes PR25267. llvm-svn: 250922
* [X86] Add AMD mwaitx, monitorx, and clzero instructions to the assembly ↵Craig Topper2015-10-211-0/+26
| | | | | | parser and disassembler. llvm-svn: 250911
* Backing out commit r250906 as it broke lld.Kevin Enderby2015-10-214-121/+48
| | | | llvm-svn: 250908
* This removes the eating of the error in Archive::Child::getSize() when the ↵Kevin Enderby2015-10-214-48/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | characters in the size field in the archive header for the member is not a number. To do this we have all of the needed methods return ErrorOr to push them up until we get out of lib. Then the tools and can handle the error in whatever way is appropriate for that tool. So the solution is to plumb all the ErrorOr stuff through everything that touches archives. This include its iterators as one can create an Archive object but the first or any other Child object may fail to be created due to a bad size field in its header. Thanks to Lang Hames on the changes making child_iterator contain an ErrorOr<Child> instead of a Child and the needed changes to ErrorOr.h to add operator overloading for * and -> . We don’t want to use llvm_unreachable() as it calls abort() and is produces a “crash” and using report_fatal_error() to move the error checking will cause the program to stop, neither of which are really correct in library code. There are still some uses of these that should be cleaned up in this library code for other than the size field. Also corrected the code where the size gets us to the “at the end of the archive” which is OK but past the end of the archive will return object_error::parse_failed now. The test cases use archives with text files so one can see the non-digit character, in this case a ‘%’, in the size field. llvm-svn: 250906
* [Option] Use an ArrayRef to store the Option Infos in OptTable. NFCCraig Topper2015-10-212-8/+6
| | | | llvm-svn: 250901
* [mips][mips16] Re-work the inline assembly stubs to work with IAS. NFC.Daniel Sanders2015-10-211-89/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, we were inserting an InlineAsm statement for each line of the inline assembly. This works for GAS but it triggers prologue/epilogue emission when IAS is in use. This caused: .set noreorder .cpload $25 to be emitted as: .set push .set reorder .set noreorder .set pop .set push .set reorder .cpload $25 .set pop which led to assembler errors and caused the test to fail. The whitespace-after-comma changes included in this patch are necessary to match the output when IAS is in use. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13653 llvm-svn: 250895
* [AA] Enhance the new AliasAnalysis infrastructure with an optionalChandler Carruth2015-10-211-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "external" AA wrapper pass. This is a generic hook that can be used to thread custom code into the primary AAResultsWrapperPass for the legacy pass manager in order to allow it to merge external AA results into the AA results it is building. It does this by threading in a raw callback and so it is *very* powerful and should serve almost any use case I have come up with for extending the set of alias analyses used. The only thing not well supported here is using a *different order* of alias analyses. That form of extension *is* supportable with the new pass manager, and I can make the callback structure here more elaborate to support it in the legacy pass manager if this is a critical use case that people are already depending on, but the only use cases I have heard of thus far should be reasonably satisfied by this simpler extension mechanism. It is hard to test this using normal facilities (the built-in AAs don't use this for obvious reasons) so I've written a fairly extensive set of custom passes in the alias analysis unit test that should be an excellent test case because it models the out-of-tree users: it adds a totally custom AA to the system. This should also serve as a reasonably good example and guide for out-of-tree users to follow in order to rig up their existing alias analyses. No support in opt for commandline control is provided here however. I'm really unhappy with the kind of contortions that would be required to support that. It would fully re-introduce the analysis group self-recursion kind of patterns. =/ I've heard from out-of-tree users that this will unblock their use cases with extending AAs on top of the new infrastructure and let us retain the new analysis-group-free-world. Differential Revision: http://reviews.llvm.org/D13418 llvm-svn: 250894
* Masked Load/Store optimization for scalar codeElena Demikhovsky2015-10-211-12/+72
| | | | | | | | | When we have to convert the masked.load, masked.store to scalar code, we generate a chain of conditional basic blocks. I added optimization for constant mask vector. Differential Revision: http://reviews.llvm.org/D13855 llvm-svn: 250893
* [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.Daniel Sanders2015-10-213-5/+32
| | | | | | | | | | | | | | | | | | | | | | | Summary: The forwards compatibility strategy employed by MIPS is to consider registers to be infinitely sign-extended. Then on ISA's with a wider register, the result of existing instructions are sign-extended to register width and zero-extended counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this strategy and we have therefore corrected the MSA specs to fix this. We still keep track of sign/zero-extension during legalization but we now match copy_s.[wd] where required. No change required to clang since __builtin_msa_copy_u_[wd] will map to copy_s.[wd] where appropriate for the target. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13472 llvm-svn: 250887
* Let MachineVerifier be aware of mem-to-mem instructions.Jonas Paulsson2015-10-211-2/+8
| | | | | | | | | | | | | | | A mem-to-mem instruction (that both loads and stores), which store to an FI, cannot pass the verifier since it thinks it is loading from the FI. For the mem-to-mem instruction, do a looser check in visitMachineOperand() and only check liveness at the reg-slot while analyzing a frame index operand. Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs, which now runs with this flag. Reviewed by Evan Cheng and Quentin Colombet. llvm-svn: 250885
* Do not use `dyn_cast<X>` after `isa<X>` (NFC)Mehdi Amini2015-10-211-1/+1
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 250883
* Tail duplication can mix incompatible registers in phi nodesKrzysztof Parzyszek2015-10-211-0/+21
| | | | | | | | | Do not tail duplicate blocks where the successor has a phi node, and the corresponding value in that phi node uses a subregister. http://reviews.llvm.org/D13922 llvm-svn: 250877
* WebAssembly: support importsJF Bastien2015-10-211-1/+23
| | | | | | C/C++ code can declare an extern function, which will show up as an import in WebAssembly's output. It's expected that the linker will resolve these, and mark unresolved imports as call_import (I have a patch which does this in wasmate). llvm-svn: 250875
* Tolerate negative offset when matching sample profile.Dehao Chen2015-10-212-10/+31
| | | | | | | | In some cases (as illustrated in the unittest), lineno can be less than the heade_lineno because the function body are included from some other files. In this case, offset will be negative. This patch makes clang still able to match the profile to IR in this situation. http://reviews.llvm.org/D13914 llvm-svn: 250873
* [Hexagon] Bit-based instruction simplificationKrzysztof Parzyszek2015-10-203-0/+2793
| | | | | | | Analyze bit patterns of operands and values of instructions to perform various simplifications, dead/redundant code elimination, etc. llvm-svn: 250868
* [Hexagon] Fix isNVStorable flag in .td filesKrzysztof Parzyszek2015-10-202-20/+48
| | | | | | | An upper half and a double word cannot be used as value sources in a new-value store. llvm-svn: 250867
* [MemorySanitizer] NFC. Do not use GET_INTRINSIC_MODREF_BEHAVIOR table.Igor Laevsky2015-10-201-28/+3
| | | | | | | | | It is now possible to infer intrinsic modref behaviour purely from intrinsic attributes. This change will allow to completely remove GET_INTRINSIC_MODREF_BEHAVIOR table. Differential Revision: http://reviews.llvm.org/D13907 llvm-svn: 250860
* [Hexagon] Capture aggregate variables by reference, not valueKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250851
* [Hexagon] Do not fall-through if there is no CFG edgeKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250850
* [Hexagon] Use symbolic name for subregister instead of hardcoded numberKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250849
* [Hexagon] Change Based->Base in getBasedWithImmOffsetKrzysztof Parzyszek2015-10-202-3/+3
| | | | llvm-svn: 250848
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-207-125/+27
| | | | llvm-svn: 250845
* Two switch blocks in VectorLegalizer::LegalizeOp already have aArtyom Skrobov2015-10-201-0/+1
| | | | | | | | | | default: llvm_unreachable("This action is not supported yet!"); -- so I'm adding one to the third switch block, too. This is a follow-up fix for http://reviews.llvm.org/D13862 llvm-svn: 250830
* [SystemZ] Use LivePhysRegs helper class in SystemZShortenInst.cpp.Jonas Paulsson2015-10-201-80/+35
| | | | | | | | | Don't use home brewed liveness tracking code for phys regs, since this class does the job. Reviewed by Ulrich Weigand. llvm-svn: 250829
* Adding support for TargetLoweringBase::LibCallArtyom Skrobov2015-10-202-253/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: TargetLoweringBase::Expand is defined as "Try to expand this to other ops, otherwise use a libcall." For ISD::UDIV and ISD::SDIV, the choice between the two possibilities was defined in a rather convoluted way: - if DIVREM is legal, expand to DIVREM - if DIVREM has a custom lowering, expand to DIVREM - if DIVREM libcall is defined and a remainder from the same division is computed elsewhere, expand to a DIVREM libcall - else, expand to a DIV libcall This had the undesirable effect that if both DIV and DIVREM are implemented as libcalls, then ISD::UDIV and ISD::SDIV are expanded to the heavier DIVREM libcall, even when the remainder isn't used. The new code adds a new LegalizeAction, TargetLoweringBase::LibCall, so that backends can directly control whether they prefer an expansion or a conversion to a libcall. This makes the generic lowering code even more generic, allowing its reuse in a wider range of target-specific configurations. The useful effect is that ARM backend will now generate a call to __aeabi_{i,u}div rather than __aeabi_{i,u}divmod in cases where it doesn't need the remainder. There's no functional change outside the ARM backend. Reviewers: t.p.northover, rengolin Subscribers: t.p.northover, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D13862 llvm-svn: 250826
* Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into ↵Artyom Skrobov2015-10-203-67/+99
| | | | | | | | | | | | | | | | | | | | | | | | DAGCombiner. Summary: In addition to moving the code over, this patch amends the DIV,REM -> DIVREM combining to run on all affected nodes at once: if the nodes are converted to DIVREM one at a time, then the resulting DIVREM may get legalized by the backend into something target-specific that we won't be able to recognize and correlate with the remaining nodes. The motivation is to "prepare terrain" for D13862: when we set DIV and REM to be legalized to libcalls, instead of the DIVREM, we otherwise lose the ability to combine them together. To prevent this, we need to take the DIV,REM -> DIVREM combining out of the lowering stage. Reviewers: RKSimon, eli.friedman, rengolin Subscribers: john.brawn, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D13733 llvm-svn: 250825
* AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.Igor Breger2015-10-203-106/+109
| | | | | | Differential Revision: http://reviews.llvm.org/D13884 llvm-svn: 250819
* Fix missing INITIALIZE_PASS_DEPENDENCY for AddressSanitizerKeno Fischer2015-10-201-0/+1
| | | | | | | | | | | | | | Summary: In r231241, TargetLibraryInfoWrapperPass was added to `getAnalysisUsage` for `AddressSanitizer`, but the corresponding `INITIALIZE_PASS_DEPENDENCY` was not added. Reviewers: dvyukov, chandlerc, kcc Subscribers: kcc, llvm-commits Differential Revision: http://reviews.llvm.org/D13629 llvm-svn: 250813
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-207-40/+111
| | | | llvm-svn: 250797
* AMDGPU: Stop reserving v[254:255]Matt Arsenault2015-10-201-4/+0
| | | | | | | | | | | This wasn't doing anything useful. They weren't explicitly used anywhere, and the RegScavenger ignores reserved registers. This for some reason caused a random scheduling change in the test. Getting the check lines to pass is too frustrating, and there's probably not too much value in checking the vector case's operands N times. llvm-svn: 250794
* WebAssembly: fix call/return syntax.JF Bastien2015-10-201-1/+6
| | | | | | They are now typeless, unlike other operations. llvm-svn: 250793
* MSP430: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-5/+3
| | | | llvm-svn: 250792
* AsmParser: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-5/+4
| | | | llvm-svn: 250791
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