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* Rename members to match LLVM naming conventions more closely.Jakob Stoklund Olesen2011-03-141-111/+109
| | | | | | | | Remove the unused reserved_ bit vector, no functional change intended. This doesn't break 'svn blame', this file really is all my fault. llvm-svn: 127607
* Remove some dead patterns.Jim Grosbach2011-03-144-56/+0
| | | | llvm-svn: 127601
* BIT_CONVERT has been renamed to BITCAST.Evan Cheng2011-03-141-1/+1
| | | | llvm-svn: 127600
* Minor optimization. sign-ext/anyext of undef is still undef.Evan Cheng2011-03-141-0/+4
| | | | llvm-svn: 127598
* Indentation.Evan Cheng2011-03-141-1/+1
| | | | llvm-svn: 127595
* Negating a recurrence preserves no-self-wrap.Andrew Trick2011-03-141-0/+11
| | | | llvm-svn: 127593
* HowFarToZero can compute a trip count as long as the recurrence has ↵Andrew Trick2011-03-141-16/+20
| | | | | | no-self-wrap. llvm-svn: 127591
* Added SCEV::NoWrapFlags to manage unsigned, signed, and self wrapAndrew Trick2011-03-145-149/+234
| | | | | | | | | properties. Added the self-wrap flag for SCEV::AddRecExpr. A slew of temporary FIXMEs indicate the intention of the no-self-wrap flag without changing behavior in this revision. llvm-svn: 127590
* whitespaceAndrew Trick2011-03-141-66/+66
| | | | llvm-svn: 127589
* PTX: Emit global arrays with proper sizesJustin Holewinski2011-03-141-5/+34
| | | | | | | - Emit all arrays as type .b8 and proper sizes in bytes to conform to the output of nvcc llvm-svn: 127584
* PTX: Add support for sqrt/sin/cos intrinsicsJustin Holewinski2011-03-141-0/+33
| | | | llvm-svn: 127578
* ptx: add set.p instruction and related changes to predicate executionChe-Liang Chiou2011-03-144-17/+59
| | | | llvm-svn: 127577
* This case is solved by Scalar Replacement of Aggregates (DT) andJin-Gu Kang2011-03-141-25/+3
| | | | | | Early CSE pass so this patch reverts it to original source code. llvm-svn: 127574
* ptx: add basic support of predicate executionChe-Liang Chiou2011-03-134-59/+177
| | | | llvm-svn: 127569
* Add comment as following:Jin-Gu Kang2011-03-131-0/+12
| | | | | | | | | | | | | | | | | load and store reference same memory location, the memory location is represented by getelementptr with two uses (load and store) and the getelementptr's base is alloca with single use. At this point, instructions from alloca to store can be removed. (this pattern is generated when bitfield is accessed.) For example, %u = alloca %struct.test, align 4 ; [#uses=1] %0 = getelementptr inbounds %struct.test* %u, i32 0, i32 0;[#uses=2] %1 = load i8* %0, align 4 ; [#uses=1] %2 = and i8 %1, -16 ; [#uses=1] %3 = or i8 %2, 5 ; [#uses=1] store i8 %3, i8* %0, align 4 llvm-svn: 127565
* Now that we are deleting unused live intervals during allocation, pointers ↵Jakob Stoklund Olesen2011-03-131-2/+4
| | | | | | | | may be reused. Use the virtual register number as a cache tag instead. They are not reused. llvm-svn: 127561
* Tell the register allocator about new unused virtual registers.Jakob Stoklund Olesen2011-03-134-1/+26
| | | | | | | This allows the allocator to free any resources used by the virtual register, including physical register assignments. llvm-svn: 127560
* Build CompilerDriver library.Oscar Fuentes2011-03-122-4/+7
| | | | llvm-svn: 127554
* Teach ComputeMaskedBits about sub nsw.Benjamin Kramer2011-03-121-8/+16
| | | | llvm-svn: 127548
* Speculatively revert commit 127478 (jsjodin) in an attempt to fix theDuncan Sands2011-03-121-0/+7
| | | | | | | | | | llvm-gcc-i386-linux-selfhost and llvm-x86_64-linux-checks buildbots. The original log entry: Remove optimization emitting a reference insted of label difference, since it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used. llvm-svn: 127540
* This patch removes some of useless instructions generated by bitfield access.Jin-Gu Kang2011-03-121-3/+13
| | | | llvm-svn: 127539
* Include snippets in the live stack interval.Jakob Stoklund Olesen2011-03-121-1/+3
| | | | llvm-svn: 127530
* Spill multiple registers at once.Jakob Stoklund Olesen2011-03-122-48/+210
| | | | | | | | | | | Live range splitting can create a number of small live ranges containing only a single real use. Spill these small live ranges along with the large range they are connected to with copies. This enables memory operand folding and maximizes the spill to fill distance. Work in progress with known bugs. llvm-svn: 127529
* Fixed the comparison operator for the enhancedSean Callanan2011-03-121-7/+2
| | | | | | disassembler's disassembler map. llvm-svn: 127527
* That's it, I am declaring this a failure of the C++03 STL.Jakob Stoklund Olesen2011-03-121-119/+15
| | | | | | | | | | | | | | There are too many compatibility problems with using mixed types in std::upper_bound, and I don't want to spend 110 lines of boilerplate setting up a call to a 10-line function. Binary search is not /that/ hard to implement correctly. I tried terminating the binary search with a linear search, but that actually made the algorithm slower against my expectation. Most live intervals have less than 4 segments. The early test against endIndex() does pay, and this version is 25% faster than plain std::upper_bound(). llvm-svn: 127522
* Sometimes isPredicable lies to us and tells us we don't need the operands.Eric Christopher2011-03-121-6/+25
| | | | | | | | | Go ahead and add them on when we might want to use them and let later passes remove them. Fixes rdar://9118569 llvm-svn: 127518
* Add FIXME.Jim Grosbach2011-03-121-0/+3
| | | | llvm-svn: 127516
* Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the sameJim Grosbach2011-03-122-27/+33
| | | | | | | | actual instruction as the non-Darwin defs, but have different call-clobber semantics and so need separate patterns. They don't need to duplicate the encoding information, however. llvm-svn: 127515
* Add a FIXME.Jim Grosbach2011-03-111-0/+2
| | | | llvm-svn: 127511
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-112-7/+14
| | | | llvm-svn: 127510
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-1/+1
| | | | llvm-svn: 127509
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-112-6/+17
| | | | llvm-svn: 127506
* 80 columnsJim Grosbach2011-03-111-1/+2
| | | | llvm-svn: 127505
* Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-Jim Grosbach2011-03-112-10/+14
| | | | | | effect that we get proper instruction printing using the "pop" mnemonic for it. llvm-svn: 127502
* Roll r127459 back in:Cameron Zwarich2011-03-111-0/+14
| | | | | | | | | | | Optimize trivial branches in CodeGenPrepare, which often get created from the lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. llvm-svn: 127498
* Fix the GCC test suite issue exposed by r127477, which was caused by stackCameron Zwarich2011-03-111-3/+3
| | | | | | | protector insertion not working correctly with unreachable code. Since that revision was rolled out, this test doesn't actual fail before this fix. llvm-svn: 127497
* Teach FastISel to support register-immediate-immediate instructions.Owen Anderson2011-03-111-0/+23
| | | | llvm-svn: 127496
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-111-8/+2
| | | | | | as for VDUP32d and VDUP32q, respectively. llvm-svn: 127489
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-112-8/+9
| | | | | | and VDUPLN32d, respectively. llvm-svn: 127486
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-111-2/+2
| | | | | | as for VREV64d32 and VREV64q32, respectively. llvm-svn: 127485
* This FIXME has been fixed.Jim Grosbach2011-03-111-3/+0
| | | | llvm-svn: 127483
* Properly pseudo-ize ARM MVNCCi.Jim Grosbach2011-03-112-12/+15
| | | | llvm-svn: 127482
* Remove optimization emitting a reference insted of label difference, since ↵Jan Sjödin2011-03-111-7/+0
| | | | | | it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used. llvm-svn: 127478
* Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often getDaniel Dunbar2011-03-111-14/+0
| | | | | | created from the", it broke some GCC test suite tests. llvm-svn: 127477
* Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).Jim Grosbach2011-03-111-3/+3
| | | | llvm-svn: 127469
* Replace -dag-chain-limit flag with constant. It has survived a release cycle ↵Andrew Trick2011-03-111-3/+1
| | | | | | without being touched, so no longer needs to pollute the hidden-help text. llvm-svn: 127468
* ComputeMaskedBits: sub falls through to add, and sub doesn't have the same ↵Benjamin Kramer2011-03-111-1/+2
| | | | | | | | overflow semantics as add. Should fix the selfhost failures that started with r127463. llvm-svn: 127465
* InstCombine: Fix a thinko where transform an icmp under the assumption that ↵Benjamin Kramer2011-03-111-3/+2
| | | | | | | | it's a zero comparison when it's not. Fixes PR9454. llvm-svn: 127464
* Teach ComputeMaskedBits about nsw on add. I don't think there's anything we canNick Lewycky2011-03-111-0/+14
| | | | | | | do with nuw here, but sub and mul should be given similar treatment. Fixes PR9343 #15! llvm-svn: 127463
* Fix use of CompEnd predicate to be standards conformingJohn Wiegley2011-03-111-9/+111
| | | | | | | | | | | | | The existing CompEnd predicate does not define a strict weak order as required by the C++03 standard; therefore, its use as a predicate to std::upper_bound is invalid. For a discussion of this issue, see http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270 This patch replaces the asymmetrical comparison with an iterator adaptor that achieves the same effect while being strictly standard-conforming by ensuring an apples-to-apples comparison. llvm-svn: 127462
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