| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 57734
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llvm-svn: 57733
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ISD condition opcodes into helper functions.
llvm-svn: 57726
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is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file.
llvm-svn: 57723
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reuse happened.
Patch by Lang Hames!
llvm-svn: 57720
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llvm-svn: 57715
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have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.
Oh! for a good debug info architecture!
llvm-svn: 57714
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touches memory and need an associated MemOperand
llvm-svn: 57712
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ISD condition opcodes into helper functions.
llvm-svn: 57710
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llvm-svn: 57709
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in 32-bit mode instead of assigning a register pair. This has nothing to
do with PR2356, but I happened to notice it while working on it.
llvm-svn: 57704
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that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand.
llvm-svn: 57699
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except they do not have any operands. The RegModRM byte is encoded with register number 0.
llvm-svn: 57692
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llvm-svn: 57691
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llvm-svn: 57690
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constraint. Reject asms where an output has multiple
input constraints tied to it.
llvm-svn: 57687
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array. Improve some minor comments, refactor some helpers in
AsmOperandInfo. No functionality change for valid code.
llvm-svn: 57686
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of aliases.
llvm-svn: 57673
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should work for intel long double, but ppc long double aborts
in convert.
llvm-svn: 57672
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use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.
A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.
To support this, teach tablegen how to handle 64-bit constants.
llvm-svn: 57663
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shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.
Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.
Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.
These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.
llvm-svn: 57662
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llvm-svn: 57660
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llvm-svn: 57649
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llvm-svn: 57644
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using the 'volatile' qualifier. This should not have any operational consequences
on code, because tags should always be stripped off (giving a non-volatile pointer)
before dereferencing. The new qualification is there to catch some attempts to use
tagged pointers in a context where an untagged pointer is appropriate.
Notably this approach does not catch dereferencing of tagged pointers, but helps
in separating the two concepts a bit.
llvm-svn: 57641
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uninitialized in these functions with gcc-4.3.
llvm-svn: 57635
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warning on x86-64 with gcc-4.3.
llvm-svn: 57634
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llvm-svn: 57631
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x86 backend. These will all be answered with "patches welcome", so
a PR doesn't help drive them along.
llvm-svn: 57630
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basically working, feel free to remove the tag. The other targets have
really basic things that break them.
llvm-svn: 57628
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llvm-svn: 57626
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llvm-svn: 57625
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llvm-svn: 57622
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llvm-svn: 57621
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additional information in Loads, Stores, Calls, Invokes,
InsertValueInsts, and ExtractValueInsts.
llvm-svn: 57620
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llvm-svn: 57618
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because it declares a std::vector<MachineMove>, and strict
concept checking requires the definition of MachineMove to be
available.
llvm-svn: 57617
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computation. A def of a register doesn't necessarily kill
live super-registers.
llvm-svn: 57614
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an unindexed load.
llvm-svn: 57612
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to find opportunities for store-to-load forwarding or load CSE,
in the same way that visitStore scans back to do DSE. Also, define
a new helper function for testing whether the addresses of two
memory accesses are known to have the same value, and use it in
both visitStore and visitLoad.
These two changes allow instcombine to eliminate loads in code
produced by front-ends that frequently emit obviously redundant
addressing for memory references.
llvm-svn: 57608
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llvm-svn: 57606
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llvm-svn: 57595
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llvm-svn: 57594
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This fixes PR2894.
llvm-svn: 57589
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llvm-svn: 57586
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llvm-svn: 57582
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llvm-svn: 57579
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llvm-svn: 57577
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llvm-svn: 57576
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llvm-svn: 57575
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