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* GlobalISel: Don't call changingInstruction before giving upMatt Arsenault2019-01-311-1/+1
| | | | llvm-svn: 352718
* GlobalISel: Allow bitcount ops to have different result typeMatt Arsenault2019-01-313-13/+48
| | | | | | For AMDGPU the result is always 32-bit for 64-bit inputs. llvm-svn: 352717
* GlobalISel: Use helper function for MMO splittingMatt Arsenault2019-01-312-26/+21
| | | | | | | | Also fix an alignment bug getMachineMemOperand. If the tracked value is null, the offset isn't tracked so the base alignment needs to be reduced. llvm-svn: 352716
* GlobalISel: Fix creating MMOs with align 0Matt Arsenault2019-01-317-16/+27
| | | | llvm-svn: 352712
* [LegalizeVectorTypes] Allow illegal indices when splitting extract_vector_eltThomas Lively2019-01-311-1/+0
| | | | | | | | | | | | | | | | | Summary: Fixes PR40267, in which the removed assertion was triggering on perfectly valid IR. As far as I can tell, constant out of bounds indices should be allowed when splitting extract_vector_elt, since they will simply be propagated as out of bounds indices in the resulting split vector and handled appropriately elsewhere. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya Differential Revision: https://reviews.llvm.org/D57471 llvm-svn: 352702
* [LegalizeTypes] Use report_fatal_error instead of llvm_unreachable in the ↵Craig Topper2019-01-311-2/+3
| | | | | | | | | | default case of some type legalization handlers that can be reached with intrinsics with result or operands that aren't legal types. These can be triggered by mistakenly using a 64-bit mode only intrinsics with a -mtriple=i686. Using report_fatal_error gives a better experience for this mistake in release builds instead of probably crashing. We already do this for some of the vector type legalization handles. llvm-svn: 352699
* [X86] Remove handling of ISD::INTRINSIC_WO_CHAIN in ReplaceNodeResults.Craig Topper2019-01-311-6/+0
| | | | | | I believe this was there to handle avx512bw intrinsics that returned i64 type in 32-bit mode. But all those intrinsics have since been changed to v64i1 results or replaced with generic IR. llvm-svn: 352698
* [RuntimeDyld] Don't try to allocate sections with align 0.Zachary Turner2019-01-301-0/+5
| | | | | | | | | | | | | ELF sections allow 0 for the alignment, which is specified to be the same as 1. However many clients do not expect this and will behave poorly in the presence of a 0-aligned section (for example by trying to modulo something by the section alignment). We can be more polite by making sure that we always pass a non-zero value to clients. Differential Revision: https://reviews.llvm.org/D57482 llvm-svn: 352694
* [GlobalISel][AArch64] Select G_FEXPJessica Paquette2019-01-303-2/+9
| | | | | | | | | | | | | | | This teaches the legalizer to handle G_FEXP in AArch64. As a result, it also allows us to select G_FEXP. It... - Updates the legalizer-info tests - Adds a test for legalizing exp - Updates the existing fp tests to show that we can now select G_FEXP https://reviews.llvm.org/D57483 llvm-svn: 352692
* [GlobalISel][LegalizerHelper] Add some missing MI change observer calls.Amara Emerson2019-01-301-0/+2
| | | | | | No test as it's a preventative fix. llvm-svn: 352691
* [PowerPC] delete no more needed workaround for readsRegister() in PowerPCChen Zheng2019-01-301-14/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D57439 llvm-svn: 352689
* MIR: Reject non-power-of-4 alignments in MMO parsingMatt Arsenault2019-01-301-0/+4
| | | | llvm-svn: 352686
* [GlobalISel][AArch64] Select G_FABSJessica Paquette2019-01-302-1/+2
| | | | | | | | | This adds instruction selection support for G_FABS in AArch64. It also updates the existing basic FP tests, adds a selection test for G_FABS. https://reviews.llvm.org/D57418 llvm-svn: 352684
* [WebAssembly] MC: Use WritePatchableLEB helper function. NFC.Sam Clegg2019-01-301-33/+30
| | | | | | | | Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D57477 llvm-svn: 352683
* [WebAssembly] Restore stack pointer right after catch instructionHeejin Ahn2019-01-305-98/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: After the staack is unwound due to a thrown exxception, `__stack_pointer` global can point to an invalid address. So a `global.set` to restore `__stack_pointer` should be inserted right after `catch` instruction. But after r352598 the `global.set` instruction is inserted not right after `catch` but after `block` - `br-on-exn` - `end_block` - `extract_exception` sequence. This CL fixes it. While doing that, we can actually move ReplacePhysRegs pass after LateEHPrepare and merge EHRestoreStackPointer pass into LateEHPrepare, and now placing `global.set` to `__stack_pointer` right after `catch` is much easier. Otherwise it is hard to guarantee that `global.set` is still right after `catch` and not touched with other transformations, in which case we have to do something to hoist it. Reviewers: dschuff Subscribers: mgorny, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D57421 llvm-svn: 352681
* [DAGCombiner] sub X, 0/1 --> add X, 0/-1Sanjay Patel2019-01-301-10/+22
| | | | | | | | | | This extends the existing transform for: add X, 0/1 --> sub X, 0/-1 ...to allow the sibling subtraction fold. This pattern could regress with the proposed change in D57401. llvm-svn: 352680
* [GlobalISel][AArch64] Add instruction selection support for @llvm.log2Jessica Paquette2019-01-303-2/+9
| | | | | | | | | | | | | This teaches GlobalISel to emit a RTLib call for @llvm.log2 when it encounters it. It updates the existing floating point tests to show that we don't fall back on the intrinsic, and select the correct instructions. It also adds a legalizer test for G_FLOG2. https://reviews.llvm.org/D57357 llvm-svn: 352673
* [GlobalISel][AArch64] Add instruction selection support for @llvm.sqrtJessica Paquette2019-01-303-1/+4
| | | | | | | | | | This teaches the legalizer about G_FSQRT in AArch64. Also adds a legalizer test for G_FSQRT, a selection test for it, and updates existing floating point tests. https://reviews.llvm.org/D57361 llvm-svn: 352671
* [GlobalISel] Add IRTranslator support for @llvm.sqrt -> G_FSQRTJessica Paquette2019-01-301-0/+5
| | | | | | | | | | | Follow-up commit to https://reviews.llvm.org/D57359. (r352668) This adds IRTranslator support for recognising a @llvm.sqrt intrinsic and translating it into a G_FSQRT. https://reviews.llvm.org/D57360 llvm-svn: 352670
* Reverting r352642 - Handle restore instructions in LiveDebugValues - as it's ↵Wolfgang Pieb2019-01-303-215/+94
| | | | | | | | causing assertions on some buildbots. llvm-svn: 352666
* Add a 'dynamic' parameter to the objectsize intrinsicErik Pilkington2019-01-307-26/+48
| | | | | | | | | | | | | | This is meant to be used with clang's __builtin_dynamic_object_size. When 'true' is passed to this parameter, the intrinsic has the potential to be folded into instructions that will be evaluated at run time. When 'false', the objectsize intrinsic behaviour is unchanged. rdar://32212419 Differential revision: https://reviews.llvm.org/D56761 llvm-svn: 352664
* [X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7.Craig Topper2019-01-302-2/+6
| | | | | | | | | | This fixes the test case in PR35982 by preventing MMX instructions that read MM0-7 from being moved below EMMS/FEMMS by the post RA scheduler. Though as discussed in bugzilla, this is not a complete fix. There is still the possibility of reordering in IR or by the pre-RA scheduler. Differential Revision: https://reviews.llvm.org/D57298 llvm-svn: 352660
* SimplifyDemandedVectorElts for all intrinsicsPhilip Reames2019-01-301-32/+15
| | | | | | | | | | The point is that this simplifies integration of new intrinsics into SimplifiedDemandedVectorElts, and ensures we don't miss any existing ones. This is intended to be NFC-ish, but as seen from the diffs, can produce slightly different output. This is due to order of transforms w/in instcombine resulting in two slightly different fixed points. That's something we should fix, but isn't a problem w/this patch per se. Differential Revision: https://reviews.llvm.org/D57398 llvm-svn: 352653
* [DEBUGINFO] Handle restore instructions in LiveDebugValuesWolfgang Pieb2019-01-303-94/+215
| | | | | | | | | | | | | The LiveDebugValues pass recognizes spills but not restores, which can cause large gaps in location information for some variables, depending on control flow. This patch make LiveDebugValues recognize restores and generate appropriate DBG_VALUE instructions. Reviewers: aprantl, NicolaPrica Differential Revision: https://reviews.llvm.org/D57271 llvm-svn: 352642
* GlobalISel: Add assert that legalize mutation makes senseMatt Arsenault2019-01-301-1/+64
| | | | | | | | | I've repeatedly encountered bugs resulting from custom legalize mutations returning nonsense legalize results, such as increasing the number of elements for FewerElements. Add an assert function to make sure the type to mutate to is consistent with the legalize action. llvm-svn: 352636
* AMDGPU: Stop generating unused intrinsic .inc filesMatt Arsenault2019-01-301-2/+0
| | | | llvm-svn: 352635
* [X86][AVX] Prefer to combine shuffle to broadcasts whenever possibleSimon Pilgrim2019-01-301-11/+14
| | | | | | This is the first step towards improving broadcast support on AVX1 targets. llvm-svn: 352634
* Properly use DT.verify in LoopSimplifyCFGMax Kazantsev2019-01-301-1/+1
| | | | llvm-svn: 352621
* Enable IRCE for narrow latch by defailtMax Kazantsev2019-01-301-1/+1
| | | | llvm-svn: 352619
* [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment ↵Shiva Chen2019-01-305-2/+86
| | | | | | | | | | | | | | | | | | | | when linker relaxation enabled Linker relaxation may change code size. We need to fix up the alignment of alignment directive in text section by inserting Nops and R_RISCV_ALIGN relocation type. So then linker could satisfy the alignment by removing Nops. To do this: 1. Add shouldInsertExtraNopBytesForCodeAlign target hook to calculate the Nops we need to insert. 2. Add shouldInsertFixupForCodeAlign target hook to insert R_RISCV_ALIGN fixup type. Differential Revision: https://reviews.llvm.org/D47755 llvm-svn: 352616
* [NativePDB] Fix access to both old & new fpo data entries from dbi streamAleksandr Urakov2019-01-301-36/+69
| | | | | | | | | | | | | | | | | | Summary: This patch fixes access to fpo streams in native pdb from DbiStream and makes code consistent with DbiStreamBuilder. Patch By: leonid.mashinskiy Reviewers: zturner, aleksandr.urakov Reviewed By: zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56725 llvm-svn: 352615
* [X86] Remove unnecessary code from the top of handleCompareFP in ↵Craig Topper2019-01-301-2/+0
| | | | | | | | X86FloatingPoint.cpp. There were checks to ensure some tables were sorted, but those tables aren't used by this function. The same tables are checked in the function that does use them. Maybe this was copy/pasted? llvm-svn: 352609
* [X86] Remove a couple places where we unnecessarily pass 0 to the ↵Craig Topper2019-01-301-4/+4
| | | | | | | | | | EmitPriority of some FP instruction aliases. NFC As far as I can tell we already won't emit these aliases due to an operand count check in the tablegen code. Removing these because I couldn't make sense of the inconsistency between fadd and fmul from reading the code. I checked the AsmMatcher and AsmWriter files before and after this change and there were no differences. llvm-svn: 352608
* [X86] Add FPSW as a Def on some FP instructions that were missing it.Craig Topper2019-01-301-5/+5
| | | | llvm-svn: 352607
* [NFC] fix trivial typos in commentsHiroshi Inoue2019-01-304-7/+7
| | | | llvm-svn: 352602
* GlobalISel: Implement fewerElementsVector for selectMatt Arsenault2019-01-302-1/+94
| | | | llvm-svn: 352601
* AMDGPU/GlobalISel: Fix clamping shifts with 16-bit instsMatt Arsenault2019-01-301-2/+3
| | | | llvm-svn: 352599
* [WebAssembly] Exception handling: Switch to the new proposalHeejin Ahn2019-01-3019-619/+456
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This switches the EH implementation to the new proposal: https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md (The previous proposal was https://github.com/WebAssembly/exception-handling/blob/master/proposals/old/Exceptions.md) - Instruction changes - Now we have one single `catch` instruction that returns a except_ref value - `throw` now can take variable number of operations - `rethrow` does not have 'depth' argument anymore - `br_on_exn` queries an except_ref to see if it matches the tag and branches to the given label if true. - `extract_exception` is a pseudo instruction that simulates popping values from wasm stack. This is to make `br_on_exn`, a very special instruction, work: `br_on_exn` puts values onto the stack only if it is taken, and the # of values can vay depending on the tag. - Now there's only one `catch` per `try`, this patch removes all special handling for terminate pad with a call to `__clang_call_terminate`. Before it was the only case there are two catch clauses (a normal `catch` and `catch_all` per `try`). - Make `rethrow` act as a terminator like `throw`. This splits BB after `rethrow` in WasmEHPrepare, and deletes an unnecessary `unreachable` after `rethrow` in LateEHPrepare. - Now we stop at all catchpads (because we add wasm `catch` instruction that catches all exceptions), this creates new `findWasmUnwindDestinations` function in SelectionDAGBuilder. - Now we use `br_on_exn` instrution to figure out if an except_ref matches the current tag or not, LateEHPrepare generates this sequence for catch pads: ``` catch block i32 br_on_exn $__cpp_exception end_block extract_exception ``` - Branch analysis for `br_on_exn` in WebAssemblyInstrInfo - Other various misc. changes to switch to the new proposal. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D57134 llvm-svn: 352598
* GlobalISel: Use appropriate extension for legalizing select conditionsMatt Arsenault2019-01-302-1/+22
| | | | llvm-svn: 352597
* [PowerPC] [NFC] Create a helper function to copy register to particular ↵Zi Xuan Wu2019-01-301-35/+18
| | | | | | | | | | | | register class at PPCFastISel Make copy register code as common function as following. unsigned copyRegToRegClass(const TargetRegisterClass *ToRC, unsigned SrcReg, unsigned Flag = 0, unsigned SubReg = 0); Differential Revision: https://reviews.llvm.org/D57368 llvm-svn: 352596
* GlobalISel: Support narrowScalar for uneven loadsMatt Arsenault2019-01-302-11/+48
| | | | llvm-svn: 352594
* [WebAssembly] Optimize BUILD_VECTOR lowering for sizeThomas Lively2019-01-303-112/+111
| | | | | | | | | | | | | | | | | | Summary: Implements custom lowering logic that finds the optimal value for the initial splat of the vector and either uses it or uses v128.const if it is available and if it would produce smaller code. This logic replaces large TableGen ISEL patterns that would lower all non-splat BUILD_VECTORs into a splat followed by a fixed number of replace_lane instructions. This CL fixes PR39685. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D56633 llvm-svn: 352592
* GlobalISel: Handle some odd splits in fewerElementsVectorMatt Arsenault2019-01-301-10/+55
| | | | | | Also add some quick hacks to AMDGPU legality for the tests. llvm-svn: 352591
* GlobalISel: Handle more cases for widenScalar for G_STOREMatt Arsenault2019-01-301-3/+10
| | | | llvm-svn: 352585
* [PowerPC] more opportunity for converting reg+reg to reg+immChen Zheng2019-01-301-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D57314 llvm-svn: 352583
* GlobalISel: Verify memory size for load/storeMatt Arsenault2019-01-301-4/+9
| | | | llvm-svn: 352578
* Remove a redundant space from an error message; NFCGeorge Burgess IV2019-01-301-1/+1
| | | | llvm-svn: 352576
* [WebAssembly] Add missing SymbolRef update from rL352551Sam Clegg2019-01-301-2/+2
| | | | | | | | This change broke some MC tests which are now fixed. Differential Revision: https://reviews.llvm.org/D57424 llvm-svn: 352573
* [WebAssembly] Lower SCALAR_TO_VECTOR to splatsThomas Lively2019-01-291-0/+13
| | | | | | | | | | Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish Differential Revision: https://reviews.llvm.org/D57269 llvm-svn: 352568
* GlobalISel: Fix unused variable warning in release buildsMatt Arsenault2019-01-291-2/+1
| | | | llvm-svn: 352565
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