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* Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => ↵Michael Gottesman2013-03-253-14/+14
| | | | | | IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h. llvm-svn: 177855
* [NVPTX] Fix handling of vector argumentsJustin Holewinski2013-03-242-7/+56
| | | | llvm-svn: 177847
* Clean up Sparc patterns.Jakob Stoklund Olesen2013-03-241-5/+5
| | | | | | | The types of register variables no longer need to be specified in output patterns. llvm-svn: 177845
* Allow TableGen DAG arguments to be just a name.Jakob Stoklund Olesen2013-03-241-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG arguments can optionally be named: (dag node, node:$name) With this change, the node is also optional: (dag node, node:$name, $name) The missing node is treated as an UnsetInit, so the above is equivalent to: (dag node, node:$name, ?:$name) This syntax is useful in output patterns where we currently require the types of variables to be repeated: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>; This is preferable: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; llvm-svn: 177843
* Minor cleanups. No functionality change.Jakub Staszak2013-03-241-6/+7
| | | | llvm-svn: 177837
* Use dyn_cast instead of isa && cast.Jakub Staszak2013-03-241-8/+6
| | | | | | No functionality change. llvm-svn: 177836
* Give Sparc instruction patterns direct types instead of register classes.Jakob Stoklund Olesen2013-03-241-81/+68
| | | | | | | Also update the documentation since Sparc is the nicest backend, and used as an example in WritingAnLLVMBackend. llvm-svn: 177835
* PPC ZERO register needs a register number of 0.Hal Finkel2013-03-231-0/+1
| | | | | | | | | In order for the new ZERO register to be used with MC, etc. we need to specify its register number (0). Thanks to Kai for reporting the problem! llvm-svn: 177833
* Note in PPCFunctionInfo VRSAVE spillsHal Finkel2013-03-234-14/+34
| | | | | | | | | | | | In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. llvm-svn: 177832
* MCize the bcl instruction in PPCAsmPrinterHal Finkel2013-03-231-4/+5
| | | | | | | | | I recently added a BCL instruction definition as part of implementing SjLj support. This can also be used to MCize bcl emission in the asm printer. No functionality change intended. llvm-svn: 177830
* Use direct types in Sparc def : Pat patterns.Jakob Stoklund Olesen2013-03-231-10/+10
| | | | | | | | | | The SelectionDAG graph has MVT type labels, not register classes, so this makes it clearer what is happening. This notation is also robust against adding more types to the IntRegs register class. llvm-svn: 177829
* Cleanup some unused reg. scavenger parameters in PPCRegisterInfoHal Finkel2013-03-232-33/+19
| | | | | | | | | | | These spilling functions will eventually make use of the register scavenger, however, they'll do so by taking advantage of PEI's virtual-register-based delayed scavenging mechanism. As a result, these function parameters will not be used, and can be removed. No functionality change intended. llvm-svn: 177827
* Remove dead PPC LR spilling codeHal Finkel2013-03-231-30/+8
| | | | | | | | | | The LR register is unconditionally reserved, and its spilling and restoration is handled by the prologue/epilogue code. As a result, it is never explicitly spilled by the register allocator. No functionality change intended. llvm-svn: 177823
* Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson2013-03-231-1/+0
| | | | | | | | | | @llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. llvm-svn: 177820
* Change method name ClearRefCount => ClearKnownPositiveRefCount to match the ↵Michael Gottesman2013-03-231-4/+4
| | | | | | name of the member that it is modifying. llvm-svn: 177818
* Changed the method name PtrState.IsKnownIncremented() to ↵Michael Gottesman2013-03-231-3/+3
| | | | | | | | | PtrState.HasKnownPositiveRefCount(). Now said method matches namewise every other method which refers to the member KnownPositiveRefCount of the class PtrState. llvm-svn: 177816
* Fix comparison of mixed signednessHal Finkel2013-03-231-1/+1
| | | | | | | | | | | 177774 broke the lld-x86_64-darwin11 builder; error: error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long') for (SI = 0; SI < Scavenged.size(); ++SI) ~~ ^ ~~~~~~~~~~~~~~~~ Fix this by making SI also unsigned. llvm-svn: 177780
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-229-28/+47
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. llvm-svn: 177774
* Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.Manman Ren2013-03-221-0/+72
| | | | | | | | | Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries between pointers do not include TBAA tags. Add testing case for "placement new". TBAA currently says NoAlias. llvm-svn: 177772
* Kill every call to @clang.arc.use in the ARC contract phase.John McCall2013-03-225-3/+22
| | | | llvm-svn: 177769
* Add all clauses when merging the landing pads. Duplicates will be handled ↵Bill Wendling2013-03-221-24/+14
| | | | | | later on. llvm-svn: 177757
* Swap the DIFile in DILexicalBlockFile out for the raw name/directory pairDavid Blaikie2013-03-222-5/+1
| | | | | | This is the last change in transitioning all DIScopes to have a common prefix. llvm-svn: 177756
* reorder the fields in DILexicalBlockFile to match the common prefix for DIScopesDavid Blaikie2013-03-221-2/+2
| | | | llvm-svn: 177754
* Don't use the removed API.Bill Wendling2013-03-221-5/+2
| | | | llvm-svn: 177749
* Revert r177675. This is language-specific and shouldn't be in the API.Bill Wendling2013-03-221-7/+0
| | | | llvm-svn: 177748
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma2013-03-225-494/+483
| | | | | | word. llvm-svn: 177747
* Refactor out the DIFile parameter to DILexicalBlock to refer to the raw ↵David Blaikie2013-03-222-5/+1
| | | | | | file/directory pair llvm-svn: 177742
* Remove ABI-duplicated call instruction patterns.Ulrich Weigand2013-03-228-148/+71
| | | | | | | | | | | | | | | | | | We currently have a duplicated set of call instruction patterns depending on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the different ABIs will result in different instruction sequences, the actual instructions themselves ought to be independent of the ABI. And in fact it turns out that the only nontrivial difference between the two sets of patterns is that in the PPC64 Linux ABI, the instruction used for indirect calls is marked to take X11 as extra input register (which is indeed used only with that ABI to hold an incoming environment pointer for nested functions). However, this does not need to be hard-coded at the .td pattern level; instead, the C++ code expanding calls can simply add that use, just like it adds uses for argument registers anyway. No change in generated code expected. llvm-svn: 177735
* Rename memrr ptrreg and offreg components.Ulrich Weigand2013-03-222-22/+22
| | | | | | | | | | | Currently, the sub-operand of a memrr address that corresponds to what hardware considers the base register is called "offreg", while the sub-operand that corresponds to the offset is called "ptrreg". To avoid confusion, this patch simply swaps the named of those two sub-operands and updates all uses. No functional change is intended. llvm-svn: 177734
* Fix swapped BasePtr and Offset in pre-inc memory addresses.Ulrich Weigand2013-03-224-20/+40
| | | | | | | | | | | | | | | | | | | | PPCTargetLowering::getPreIndexedAddressParts currently provides the base part of a memory address in the offset result, and the offset part in the base result. That swap is then undone again when an MI instruction is generated (in PPCDAGToDAGISel::Select for loads, and using .md Pat patterns for stores). This patch reverts this double swap, to make common code and back-end be in sync as to which part of the address is base and which is offset. To avoid performance regressions in certain cases, target code now checks whether the choice of base register would be rejected for pre-inc accesses by common code, and attempts to swap base and offset again in such cases. (Overall, this means that now pre-ice accesses are generated *more* frequently than before.) llvm-svn: 177733
* Tighten iaddroff ComplexPattern.Ulrich Weigand2013-03-221-4/+4
| | | | | | | | | | | | | | | | | The iaddroff ComplexPattern is supposed to recognize displacement expressions that have been processed by a SelectAddressRegImm, which means it needs to accept TargetConstant and TargetGlobalAddress nodes. Currently, it erroneously also accepts some other nodes, in particular Constant and PPCISD::Lo. While this problem is currently latent, it would cause wrong-code bugs with a follow-on patch I'm about to commit, so this patch tightens the ComplexPattern. The equivalent change is made in PPCDAGToDAGISel::Select, where pre-inc load patterns are handled (as opposed to store patterns, the loads are handled in C++ code without making use of the .td ComplexPattern). llvm-svn: 177732
* Remove the xaddroff ComplexPattern.Ulrich Weigand2013-03-223-31/+18
| | | | | | | | | The xaddroff pattern is currently (mistakenly) used to recognize the *base* register in pre-inc store patterns. This patch replaces those uses by ptr_rc_nor0 (as is elsewhere done to match the base register of an address), and removes the now unused ComplexPattern. llvm-svn: 177731
* R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer2013-03-224-15/+5
| | | | | | | | | | | | | | | | Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g. manifested by failure of two piglit/glean tests and intermittent black patches in many apps. Tested on SI and RS880. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g] NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 177730
* [asan] Change the way we report the alloca frame on stack-buff-overflow.Kostya Serebryany2013-03-221-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: the function name was stored by the compiler as a constant string and the run-time was printing it. Now: the PC is stored instead and the run-time prints the full symbolized frame. This adds a couple of instructions into every function with non-empty stack frame, but also reduces the binary size because we store less strings (I saw 2% size reduction). This change bumps the asan ABI version to v3. llvm part. Example of report (now): ==31711==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fffa77cf1c5 at pc 0x41feb0 bp 0x7fffa77cefb0 sp 0x7fffa77cefa8 READ of size 1 at 0x7fffa77cf1c5 thread T0 #0 0x41feaf in Frame0(int, char*, char*, char*) stack-oob-frames.cc:20 #1 0x41f7ff in Frame1(int, char*, char*) stack-oob-frames.cc:24 #2 0x41f477 in Frame2(int, char*) stack-oob-frames.cc:28 #3 0x41f194 in Frame3(int) stack-oob-frames.cc:32 #4 0x41eee0 in main stack-oob-frames.cc:38 #5 0x7f0c5566f76c (/lib/x86_64-linux-gnu/libc.so.6+0x2176c) #6 0x41eb1c (/usr/local/google/kcc/llvm_cmake/a.out+0x41eb1c) Address 0x7fffa77cf1c5 is located in stack of thread T0 at offset 293 in frame #0 0x41f87f in Frame0(int, char*, char*, char*) stack-oob-frames.cc:12 <<<<<<<<<<<<<< this is new This frame has 6 object(s): [32, 36) 'frame.addr' [96, 104) 'a.addr' [160, 168) 'b.addr' [224, 232) 'c.addr' [288, 292) 's' [352, 360) 'd' llvm-svn: 177724
* tsan: handle vptr loads speciallyDmitry Vyukov2013-03-221-0/+10
| | | | | | | This is required to determine ctor/dtor vs virtual call races. http://llvm-reviews.chandlerc.com/D566 llvm-svn: 177717
* Fix llvm::removeUnreachableBlocks to handle unreachable loops.Evgeniy Stepanov2013-03-221-12/+7
| | | | llvm-svn: 177713
* InstCombine: Improve the result bitvect type when folding (cmp pred (load ↵Arnaud A. de Grandmaison2013-03-222-11/+27
| | | | | | | | | | | | | | | (gep GV, i)) C) to a bit test. The original code used i32, and i64 if legal. This introduced unneeded casts when they aren't legal, or when the index variable i has another type. In order of preference: try to use i's type; use the smallest fitting legal type (using an added DataLayout method); default to i32. A testcase checks that this works when the index gep operand is i16. Patch by : Ahmed Bougacha <ahmed.bougacha@gmail.com> Reviewed by : Duncan llvm-svn: 177712
* Remove ScavengedRC from RegisterScavengingHal Finkel2013-03-221-3/+0
| | | | | | | ScavengedRC was a dead private variable (set, but not otherwise used). No functionality change intended. llvm-svn: 177708
* Reorder the DIFile field in DILexicalBlock to become a prefix common with ↵David Blaikie2013-03-221-1/+1
| | | | | | other DIScopes llvm-svn: 177703
* Revert r177543: Add timing of the IR parsing code with a newChandler Carruth2013-03-222-22/+0
| | | | | | | | | | | | | | | -time-ir-parsing flag This breaks the layering of the Support library. We can't add an implementation side to IRReader because it refers directly to entities only accessible as part of the IR, AsmParser, and BitcodeReader libraries. It can only be used in a context where all of those libraries will be available. We'll need to find some other way to get this functionality, and hopefully solve the long-standing layering problem of IRReader.h... llvm-svn: 177695
* Fix the invalid opcode for Mips branch instructions in the assemblerJack Carter2013-03-221-4/+6
| | | | | | | | | | | | | | | For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic llvm-svn: 177687
* This patch that enables the Mips assembler to use symbols for offset for ↵Jack Carter2013-03-222-17/+154
| | | | | | | | | | | | instructions This patch uses the generated instruction info tables to identify memory/load store instructions. After successful matching and based on the operand type and size, it generates additional instructions to the output. Contributor: Vladimir Medic llvm-svn: 177685
* Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register classHal Finkel2013-03-213-7/+12
| | | | | | | | | | | | As Jakob pointed out in his review of r177423, having a shared ZERO register between the 32- and 64-bit register classes causes this odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended, this adds a ZERO8 register which differentiates the 32- and 64-bit zeros. No functionality change intended. llvm-svn: 177683
* Always forward 'resume' instructions to the outter landing pad.Bill Wendling2013-03-211-16/+39
| | | | | | | | | | | | | | | | | How did this ever work? Basically, if you have a function that's inlined into the caller, it may not have any 'call' instructions, but any 'resume' instructions it may have should still be forwarded to the outer (caller's) landing pad. This requires that all of the 'landingpad' instructions in the callee have their clauses merged with the caller's outer 'landingpad' instruction (hence the bit of ugly code in the `forwardResume' method). Testcase in a follow commit to the test-suite repository. <rdar://problem/13360379> & PR15555 llvm-svn: 177680
* Fix a register-class comparison bug in PPCCTRLoopsHal Finkel2013-03-213-19/+1
| | | | | | | | | Thanks to Jakob for isolating the underlying problem from the test case in r177423. The original commit had introduced asymmetric copy operations, but these turned out to be a work-around to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops). llvm-svn: 177679
* Refactor the filename/directory information in DISubprogram to refer ↵David Blaikie2013-03-212-6/+2
| | | | | | directly to the pair rather than the DIFile. llvm-svn: 177677
* Add a query to tell if a landing pad has a catch-all.Bill Wendling2013-03-211-0/+7
| | | | llvm-svn: 177675
* Move the DIFile in DISubprogram to the beginning to be a common prefix along ↵David Blaikie2013-03-211-2/+2
| | | | | | with other DIScopes llvm-svn: 177674
* <rdar://problem/13477190> On Darwin, use DARWIN_USER_TEMP_DIR or ↵Douglas Gregor2013-03-211-0/+24
| | | | | | | | | | DARWIN_USER_CACHE_DIR for the system temporary directory. The DARWIN_USER_TEMP_DIR and DARWIN_USER_CACHE_DIR configuration settings are more idiomatic for Darwin than the TMPDIR environment variable. llvm-svn: 177669
* This patch enables the Mips .set directive to define aliasesJack Carter2013-03-211-6/+93
| | | | | | | | | | | | | | | | The .set directive in the Mips the assembler can be used to set the value of a symbol to an expression. This changes the symbol's value and type to conform to the expression's. Syntax: .set symbol, expression This patch implements the parsing of the above syntax and enables the parser to use defined symbols when parsing operands. Contributor: Vladimir Medic llvm-svn: 177667
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