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* [GVNSink] Add unary FNeg support to GVNSink passCameron McInally2019-06-281-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D63900 llvm-svn: 364678
* Default to Secure PLT on PPC for musl libc.Brad Smith2019-06-281-1/+2
| | | | | | This matches the default settings of clang. llvm-svn: 364675
* [X86] CombineShuffleWithExtract - recurse through EXTRACT_SUBVECTOR chainSimon Pilgrim2019-06-281-9/+9
| | | | llvm-svn: 364667
* hwasan: Remove the old frame descriptor mechanism.Peter Collingbourne2019-06-281-81/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D63470 llvm-svn: 364665
* [WebAssembly] Added visibility and ident directives to WasmAsmParser.Wouter van Oortmerssen2019-06-281-0/+54
| | | | | | | | | | | | | | | | | Summary: These are output by clang -S, so can now be roundtripped thru clang. (partially) fixes: https://bugs.llvm.org/show_bug.cgi?id=34544 Reviewers: dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63901 llvm-svn: 364658
* [AMDGPU][MC] Fix 2 for sanitizer failure in 364645Dmitry Preobrazhensky2019-06-282-6/+6
| | | | llvm-svn: 364656
* [ARM] Add support for the MVE long shift instructionsSam Tebbs2019-06-284-7/+85
| | | | | | | | | | | | MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers. The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl. test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions. Differential Revision: https://reviews.llvm.org/D63430 llvm-svn: 364654
* [AMDGPU][MC] Fix for sanitizer failure in 364645Dmitry Preobrazhensky2019-06-281-4/+10
| | | | llvm-svn: 364651
* [AMDGPU][MC] Enabled constant expressions as operands of sendmsgDmitry Preobrazhensky2019-06-285-210/+266
| | | | | | | | | | See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D62735 llvm-svn: 364645
* [X86] CombineShuffleWithExtract - only require 1 source to be EXTRACT_SUBVECTORSimon Pilgrim2019-06-281-8/+16
| | | | | | | | We were requiring that both shuffle operands were EXTRACT_SUBVECTORs, but we can relax this to only require one of them to be. Also, we shouldn't bother attempting this if both operands are from the lowest subvector (or not EXTRACT_SUBVECTOR at all). llvm-svn: 364644
* [ARM] Add MVE mul patternsDavid Green2019-06-281-0/+16
| | | | | | | | | This simply adds integer and floating point VMUL patterns for MVE, same as we have add and sub. Differential Revision: https://reviews.llvm.org/D63866 llvm-svn: 364643
* [ARM] Mark math routines as non-legal for MVEDavid Green2019-06-281-0/+9
| | | | | | | | | This adds handling and tests for a number of floating point math routines, which have no MVE instructions. Differential Revision: https://reviews.llvm.org/D63725 llvm-svn: 364641
* [ARM] MVE patterns for VABS and VNEGDavid Green2019-06-281-0/+14
| | | | | | | | This simply adds the required patterns for fp neg and abs. Differential Revision: https://reviews.llvm.org/D63861 llvm-svn: 364640
* [DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRangesFangrui Song2019-06-283-31/+18
| | | | | | | | | | Delete unnecessary getters of AddressRange. Simplify AddressRange::size(): Start <= End check should be checked in an upper layer. Delete isContiguousWith() that doesn't make sense. Simplify AddressRanges::insert. Delete commented code. Fix it when more than 1 ranges are to be deleted. Delete trailing newline. llvm-svn: 364637
* [ARM] Widening loads and narrowing storesDavid Green2019-06-283-4/+58
| | | | | | | | | | | | MVE has instructions to widen as it loads, and narrow as it stores. This adds the required patterns and legalisation to make them work including specifying that they are legal, patterns to select them and test changes. Patch by David Sherwood. Differential Revision: https://reviews.llvm.org/D63839 llvm-svn: 364636
* [ARM] Fix integer UB in MVE load/store immediate handling.Simon Tatham2019-06-282-6/+9
| | | | llvm-svn: 364635
* [DebugInfo] GSYM cleanups after D63104/r364427Fangrui Song2019-06-281-8/+4
| | | | llvm-svn: 364634
* [ARM] MVE loads and storesDavid Green2019-06-282-11/+52
| | | | | | | | | | | | | | | This fills in the gaps for basic MVE loads and stores, allowing unaligned access and adding far too many tests. These will become important as narrowing/expanding and pre/post inc are added. Big endian might still not be handled very well, because we have not yet added bitcasts (and I'm not sure how we want it to work yet). I've included the alignment code anyway which maps with our current patterns. We plan to return to that later. Code written by Simon Tatham, with additional tests from Me and Mikhail Maltsev. Differential Revision: https://reviews.llvm.org/D63838 llvm-svn: 364633
* [AVR] Don't look for the TargetFrameLowering in the FrameLowering implementationDylan McKay2019-06-281-1/+1
| | | | | | c.f. r364349 llvm-svn: 364632
* [ARM] Mark div and rem as expand for MVEDavid Green2019-06-281-0/+12
| | | | | | | | | We don't have vector operations for these, so they need to be expanded for both integer and float. Differential Revision: https://reviews.llvm.org/D63595 llvm-svn: 364631
* [ARM] Select MVE fp add and subDavid Green2019-06-281-0/+14
| | | | | | | | | | | The same as integer arithmetic, we can add simple floating point MVE addition and subtraction patterns. Initial code by David Sherwood Differential Revision: https://reviews.llvm.org/D63257 llvm-svn: 364629
* [HardwareLoops] Loop counter guard intrinsicSam Parker2019-06-281-16/+105
| | | | | | | | | Introduce llvm.test.set.loop.iterations which sets the loop counter and also produces an i1 after testing that the count is not zero. Differential Revision: https://reviews.llvm.org/D63809 llvm-svn: 364628
* [ARM] Select MVE add and subDavid Green2019-06-281-0/+18
| | | | | | | | | | | This adds the first few patterns for MVE code generation, adding simple integer add and sub patterns. Initial code by David Sherwood Differential Revision: https://reviews.llvm.org/D63255 llvm-svn: 364627
* [ARM] MVE vector shufflesDavid Green2019-06-285-183/+355
| | | | | | | | | | | | | | | | | | This patch adds necessary shuffle vector and buildvector support for ARM MVE. It essentially adds support for VDUP, VREVs and some VMOVs, which are often required by other code (like upcoming patches). This mostly uses the same code from Neon that already generated NEONvdup/NEONvduplane/NEONvrev's. These have been renamed to ARMvdup/etc and moved to ARMInstrInfo as they are common to both architectures. Most of the selection code seems to be applicable to both, but NEON does have some more instructions making some parts specific. Most code originally by David Sherwood. Differential Revision: https://reviews.llvm.org/D63567 llvm-svn: 364626
* [X86] Connect the output chain properly when combining vzext_movl+load into ↵Craig Topper2019-06-281-1/+1
| | | | | | vzext_load. llvm-svn: 364625
* [X86] Remove some duplicate patterns that already exist as part of their ↵Craig Topper2019-06-281-5/+1
| | | | | | instruction definition. NFC llvm-svn: 364623
* [Support] Add fs::getUmask() function and change fs::setPermissionsAlex Brachet2019-06-282-2/+19
| | | | | | | | | | | | | | | | Summary: This patch changes fs::setPermissions to optionally set permissions while respecting the umask. It also adds the function fs::getUmask() which returns the current umask. Reviewers: jhenderson, rupprecht, aprantl, lhames Reviewed By: jhenderson, rupprecht Subscribers: sanaanajjar231288, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63583 llvm-svn: 364621
* [NFC][PowerPC] Move XS*QP series instruction apart from XS*QPO series in ↵Zi Xuan Wu2019-06-281-33/+33
| | | | | | position of td file llvm-svn: 364620
* [AMDGPU] Packed thread ids in function call ABIStanislav Mekhanoshin2019-06-284-22/+132
| | | | | | Differential Revision: https://reviews.llvm.org/D63851 llvm-svn: 364619
* GlobalISel: Use RegisterMatt Arsenault2019-06-283-39/+39
| | | | llvm-svn: 364618
* [PowerPC][NFC] Use `|=` to update `Simplified` flagKai Luo2019-06-281-1/+1
| | | | llvm-svn: 364617
* AMDGPU/GlobalISel: Convert to using RegisterMatt Arsenault2019-06-284-44/+44
| | | | llvm-svn: 364616
* GlobalISel: Convert rest of MachineIRBuilder to using RegisterMatt Arsenault2019-06-281-50/+50
| | | | llvm-svn: 364615
* [GlobalISel][IRTranslator] Fix some PHI bugs related to jump tables when ↵Amara Emerson2019-06-271-14/+26
| | | | | | | | | | | | optimizations are used. The new switch lowering code that tries to generate jump tables and range checks were tested at -O0 on arm64, but on -O3 the generic switch lowering code goes to town on trying to generate optimized lowerings, e.g. multiple jump tables, range checks etc. This exposed bugs in the way PHI nodes are handled because the CFG looks even stranger after all of this is done. llvm-svn: 364613
* Fix ASAN error caused by commit r364512.Rumeet Dhindsa2019-06-271-4/+6
| | | | | | | | | This patch intends to fix ASAN stack-use-after-scope error. This is at least a short-term fix to unbreak LLVM's mainline. Differential Revision: https://reviews.llvm.org/D63905 llvm-svn: 364611
* hwasan: Use llvm.read_register intrinsic to read the PC on aarch64 instead ↵Peter Collingbourne2019-06-271-8/+17
| | | | | | | | | | | of taking the function's address. This shaves an instruction (and a GOT entry in PIC code) off prologues of functions with stack variables. Differential Revision: https://reviews.llvm.org/D63472 llvm-svn: 364608
* [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)Roman Lebedev2019-06-272-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222. There is no such action in "Add Action" menu... This implements an optimization described in Hacker's Delight 10-17: when `C` is constant, the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder. The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479. This is a recommit, the original commit rL364563 was reverted in rL364568 because test-suite detected miscompile - the new comparison constant 'Q' was being computed incorrectly (we divided by `D0` instead of `D`). Original patch D50222 by @hermord (Dmytro Shynkevych) Notes: - In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla. This seems to require an extra branch on overflow, so I refrained from implementing this for now. - An explicit check for when the `REM` can be reduced to just its LHS is included: the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise. I hadn't managed to find a better way to not generate worse output in this case. - The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390. Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00 Reviewed By: RKSimon, xbolva00 Subscribers: dexonsmith, kristina, xbolva00, javed.absar, llvm-commits, hermord Tags: #llvm Differential Revision: https://reviews.llvm.org/D63391 llvm-svn: 364600
* [GVN] Add support for unary FNeg to GVN passCameron McInally2019-06-271-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D63896 llvm-svn: 364592
* [x86] prevent crashing from select narrowing with AVX512Sanjay Patel2019-06-271-0/+9
| | | | llvm-svn: 364585
* [PowerPC][NFC] Remove unused (and unsupported) fusion feature bits.Jinsong Ji2019-06-273-7/+1
| | | | | | | | | | | | | | | FeatureFusion bits was first introduced in https://reviews.llvm.org/rL253724. for add/load integer fusion for P8. The only use of `hasFusion` was https://reviews.llvm.org/rL255319. However, this was removed later in https://reviews.llvm.org/rL280440. So, there is NO any reference to fusion in code now. Leaving it there is misleading and confusing, so remove it for now. We can alwasy add back if we ever support fusion in the future. llvm-svn: 364581
* Use "willreturn" in isGuaranteedToTransferExecutionToSuccessorJohannes Doerfert2019-06-271-0/+5
| | | | | | | | | | | | | | | | | | | | | The `willreturn` function attribute guarantees that a function call will come back to the call site if the call is also known not to throw. Therefore, this attribute can be used in `isGuaranteedToTransferExecutionToSuccessor`. Patch by Hideto Ueno (@uenoku) Reviewers: jdoerfert, sstefan1 Reviewed By: jdoerfert Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63372 llvm-svn: 364580
* Update -analyze -scalar-evolution output for multiple exit loops ↵Philip Reames2019-06-271-10/+14
| | | | | | | | w/computable exit values The previous output was next to useless if *any* exit was not computable. If we have more than one exit, show the exit count for each so that it's easier to see what's going from with SCEV analysis when debugging. llvm-svn: 364579
* Correct the file path. NFC.Michael Liao2019-06-271-1/+1
| | | | llvm-svn: 364577
* [WebAssembly] AsmParser: better atomic inst detectionWouter van Oortmerssen2019-06-271-26/+23
| | | | | | | | | | | | | | | | | Summary: Previously missed atomic.notify. Fixes https://bugs.llvm.org/show_bug.cgi?id=40728 Reviewers: aheejin Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits, dschuff Tags: #llvm Differential Revision: https://reviews.llvm.org/D63747 llvm-svn: 364576
* Revert "[LiveDebugValues] Emit the debug entry values"Djordje Todorovic2019-06-271-139/+20
| | | | | | | | | Appears that the 'test/DebugInfo/MIR/X86/dbginfo-entryvals.mir' does not pass on Windows. This reverts commit rL364553. llvm-svn: 364571
* [WebAssembly] Fix p2align in assembler.Wouter van Oortmerssen2019-06-272-12/+34
| | | | | | | | | | | | | | | | | | | | Summary: - Match the syntax output by InstPrinter. - Fix it always emitting 0 for align. Had to work around fact that opcode is not available for GetDefaultP2Align while parsing. - Updated tests that were erroneously happy with a p2align=0 Fixes https://bugs.llvm.org/show_bug.cgi?id=40752 Reviewers: aheejin, sbc100 Subscribers: jgravelle-google, sunfish, jfb, llvm-commits, dschuff Tags: #llvm Differential Revision: https://reviews.llvm.org/D63633 llvm-svn: 364570
* [X86] combineX86ShufflesRecursively - merge shuffles with more than 2 inputsSimon Pilgrim2019-06-271-4/+0
| | | | | | We already had the infrastructure for this, but were waiting for the fix for a number of regressions which were handled by the recent shuffle(extract_subvector(),extract_subvector()) -> extract_subvector(shuffle()) shuffle combines llvm-svn: 364569
* Revert "[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM ↵Roman Lebedev2019-06-271-107/+0
| | | | | | | | | | | | | | | | | | case) (try 2)" *Appears* to break test-suite on http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/23790 FAIL: burg.execution_time FAIL: spiff.execution_time FAIL: employ.execution_time FAIL: llu.execution_time FAIL: gramschmidt.execution_time FAIL: fdtd-apml.execution_time This reverts commit r364563. llvm-svn: 364568
* AMDGPU: Make fixing i1 copies robust against re-orderingNicolai Haehnle2019-06-271-10/+11
| | | | | | | | | | | | | | | | | Summary: The new test case led to incorrect code. Change-Id: Ief48b227e97aa662dd3535c9bafb27d4a184efca Reviewers: arsenm, david-salinas Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63871 llvm-svn: 364566
* Use getConstantOperandAPInt instead of getConstantOperandVal for comparisons.Simon Pilgrim2019-06-271-8/+8
| | | | | | getConstantOperandAPInt avoids any large integer issues - these are unlikely but the fuzzers do like to mess around..... llvm-svn: 364564
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