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* Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman2012-03-061-13/+13
| | | | llvm-svn: 152136
* Tidy up. Kill some dead code.Jim Grosbach2012-03-062-10/+0
| | | | llvm-svn: 152131
* Allow the same types in DPair as in QPR.Jakob Stoklund Olesen2012-03-061-1/+2
| | | | llvm-svn: 152129
* Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby2012-03-061-7/+7
| | | | llvm-svn: 152127
* Convert PowerPC to register mask operands.Roman Divacky2012-03-066-122/+52
| | | | llvm-svn: 152122
* Change ConstantAggrUniqueMap to use Chandler's new hashingJay Foad2012-03-061-36/+9
| | | | | | implementation. Patch by Meador Inge llvm-svn: 152116
* Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen2012-03-061-0/+4
| | | | | | | | | | When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. llvm-svn: 152095
* Avoid finalizeBundles infinite looping.Evan Cheng2012-03-061-0/+2
| | | | llvm-svn: 152089
* Make it possible for a target to mark FSUB as Expand. This requires ↵Owen Anderson2012-03-062-16/+39
| | | | | | providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. llvm-svn: 152079
* Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames2012-03-064-11/+17
| | | | | | | | | The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. llvm-svn: 152076
* A few more cases of missing masking in ComputeMaskedBits; found by inspection.Eli Friedman2012-03-051-3/+3
| | | | llvm-svn: 152070
* ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach2012-03-051-0/+8
| | | | | | rdar://10988114 llvm-svn: 152068
* Make sure we don't return bits outside the mask in ComputeMaskedBits. PR12189.Eli Friedman2012-03-051-2/+2
| | | | llvm-svn: 152066
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-055-26/+91
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM Remove a bit of dead code.Jim Grosbach2012-03-052-14/+0
| | | | llvm-svn: 152061
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-0511-246/+239
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-0521-30/+42
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Fix warnings about adding a bool to a string.Bill Wendling2012-03-051-2/+2
| | | | | | Patch by Sean Silva! llvm-svn: 152042
* Address Evan's comments for r151877.Chad Rosier2012-03-051-7/+6
| | | | | | | | | Specifically, remove the magic number when checking to see if the copy has a glue operand and simplify the checking logic. rdar://10930395 llvm-svn: 152041
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-057-39/+41
| | | | | | | | | | | In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> llvm-svn: 152036
* fix typosSebastian Pop2012-03-051-7/+7
| | | | llvm-svn: 152035
* remove spaces on empty linesSebastian Pop2012-03-051-9/+9
| | | | llvm-svn: 152034
* This is not a common case, in fact it never happens!Duncan Sands2012-03-051-4/+0
| | | | llvm-svn: 152027
* Switch mem2reg to use the new hashing infrastructure.Chandler Carruth2012-03-051-1/+3
| | | | llvm-svn: 152026
* Replace the ad-hoc hashing in GVN with the new hashing infrastructure.Chandler Carruth2012-03-051-10/+13
| | | | | | | | | | | | | | | | | This implicitly fixes a nasty bug in the GVN hashing (that thankfully could only manifest as a performance bug): actually include the opcode in the hash. The old code started the hash off with the opcode, but then overwrote it with the type pointer. Since this is likely to be pretty hot (GVN being already pretty expensive) I've included a micro-optimization to just not bother with the varargs hashing if they aren't present. I can't measure any change in GVN performance due to this, even with a big test case like Duncan's sqlite one. Everything I see is in the noise floor. That said, this closes a loop hole for a potential scaling problem due to collisions if the opcode were the differentiating aspect of the expression. llvm-svn: 152025
* Switch the TableGen record's string-based DenseMap key to use the newChandler Carruth2012-03-051-5/+11
| | | | | | | | hashing infrastructure. I wonder why we don't just use StringMap here, and I may revisit the issue if I have time, but for now I'm just trying to consolidate. llvm-svn: 152023
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-0518-61/+61
| | | | | | static data size. llvm-svn: 152016
* Make aliases for shld and shrd match gas. PR12173.Eli Friedman2012-03-051-14/+14
| | | | llvm-svn: 152014
* Stop fixing bad machine code in LiveIntervalAnalysis.Jakob Stoklund Olesen2012-03-041-15/+3
| | | | | | | | The first def of a virtual register cannot also read the register. Assert on such bad machine code instead of trying to fix it. TwoAddressInstructionPass should never create code like that. llvm-svn: 152010
* Stop adding <imp-def> operands when coalescing sub-registers.Jakob Stoklund Olesen2012-03-041-16/+0
| | | | | | | We are already setting <undef> flags, and that is good enough. The <imp-def> operands don't mean anything any more. llvm-svn: 152009
* Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen2012-03-041-14/+12
| | | | | | | | | | | MachineOperands that define part of a virtual register must have an <undef> flag if they are not intended as read-modify-write operands. The old trick of adding an <imp-def> operand doesn't work any longer. Fixes PR12177. llvm-svn: 152008
* Nick pointed out on IRC that GVN's propagateEquality wasn't propagatingDuncan Sands2012-03-041-1/+11
| | | | | | | | | | equalities into phi node operands for which the equality is known to hold in the incoming basic block. That's because replaceAllDominatedUsesWith wasn't handling phi nodes correctly in general (that this didn't give wrong results was just luck: the specific way GVN uses replaceAllDominatedUsesWith precluded wrong changes to phi nodes). llvm-svn: 152006
* Replace the hashing functions on APInt and APFloat with overloads of theChandler Carruth2012-03-043-106/+29
| | | | | | | | | | | | | | new hash_value infrastructure, and replace their implementations using hash_combine. This removes a complete copy of Jenkin's lookup3 hash function (which is both significantly slower and lower quality than the one implemented in hash_combine) along with a somewhat scary xor-only hash function. Now that APInt and APFloat can be passed directly to hash_combine, simplify the rest of the LLVMContextImpl hashing to use the new infrastructure. llvm-svn: 152004
* Add generic support for hashing StringRef objects using the new hashing library.Chandler Carruth2012-03-041-0/+7
| | | | llvm-svn: 152003
* Do trivial CSE of dead BBs during codegen preparation.Bill Wendling2012-03-041-1/+20
| | | | | | | | Some BBs can become dead after codegen preparation. If we delete them here, it could help enable tail-call optimizations later on. <rdar://problem/10256573> llvm-svn: 152002
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-0429-68/+68
| | | | llvm-svn: 152001
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-046-18/+18
| | | | | | static data size. llvm-svn: 151998
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-0431-52/+52
| | | | | | size of static data. llvm-svn: 151996
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-042-4/+4
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
* Correctly initialize LineSectionSymbol. Thanks to Duncan Sands for noticing it.Rafael Espindola2012-03-032-2/+2
| | | | llvm-svn: 151979
* Include cctype for isdigit. Patch by Stephen Hines.Duncan Sands2012-03-031-0/+1
| | | | llvm-svn: 151973
* LVI: Recognize the form instcombine canonicalizes range checks into when ↵Benjamin Kramer2012-03-021-4/+16
| | | | | | | | | | forming constant ranges. This could probably be made a lot smarter, but this is a common case and doesn't require LVI to scan a lot of code. With this change CVP can optimize away the "shift == 0" case in Hashing.h that only gets hit when "shift" is in a range not containing 0. llvm-svn: 151919
* ASan: use getTypeAllocSize instead of getTypeStoreSize.Evgeniy Stepanov2012-03-021-1/+1
| | | | | | | | | | | | | | | | This change replaces getTypeStoreSize with getTypeAllocSize in AddressSanitizer instrumentation for stack allocations. One case where old behaviour produced undesired results is an optimization in InstCombine pass (PromoteCastOfAllocation), which can replace alloca(T) with alloca(S), where S has the same AllocSize, but a smaller StoreSize. Another case is memcpy(long double => long double), where ASan will poison bytes 10-15 of a stack-allocated long double (StoreSize 10, AllocSize 16, sizeof(long double) = 16). See http://llvm.org/bugs/show_bug.cgi?id=12047 for more context. llvm-svn: 151887
* Prevent obscure and incorrect tail-call optimization.Chad Rosier2012-03-021-0/+5
| | | | | | | | | | | | In this instance we are generating the tail-call during legalizeDAG. The 2nd floor call can't be a tail call because it clobbers %xmm1, which is defined by the first floor call. The first floor call can't be a tail-call because it's not in the tail position. The only reasonable way I could think to fix this in a target-independent manner was to check for glue logic on the copy reg. rdar://10930395 llvm-svn: 151877
* Grammar-o in function name.Eric Christopher2012-03-021-2/+2
| | | | llvm-svn: 151875
* Grammar.Eric Christopher2012-03-021-1/+1
| | | | llvm-svn: 151874
* If the linkage name doesn't exist we're supposed to emit a referenceEric Christopher2012-03-021-4/+3
| | | | | | to the string table for the function name, not the function name. llvm-svn: 151873
* Fix an iterator invalidation problem. operator[] on a DenseMapDan Gohman2012-03-021-8/+28
| | | | | | | can insert a new element, invalidating iterators. Use find instead, and handle the case where the key is not found explicitly. llvm-svn: 151871
* Misc micro-optimizations.Dan Gohman2012-03-021-10/+12
| | | | llvm-svn: 151869
* Revert "Reorder the sections being output to reduce the number of assembler"Eric Christopher2012-03-021-3/+3
| | | | | | | | | The inline table needs to be constructed ahead of time so that it doesn't try to create new strings while we're emitting everything. This reverts commit a8ff9bccb399183cdd5f1c3cec2bda763664b4b0. llvm-svn: 151864
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