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* [SystemZ] Add CodeGen support for v2f64Ulrich Weigand2015-05-056-37/+342
| | | | | | | | | This adds ABI and CodeGen support for the v2f64 type, which is natively supported by z13 instructions. Based on a patch by Richard Sandiford. llvm-svn: 236522
* [SystemZ] Add CodeGen support for integer vector typesUlrich Weigand2015-05-0514-146/+2138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This the first of a series of patches to add CodeGen support exploiting the instructions of the z13 vector facility. This patch adds support for the native integer vector types (v16i8, v8i16, v4i32, v2i64). When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level (implemented in clang), but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. llvm-svn: 236521
* [SystemZ] Add z13 vector facility and MC supportUlrich Weigand2015-05-0516-116/+2075
| | | | | | | | | | | | | | | | | | | | | This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. llvm-svn: 236520
* Revert "Refactor UpdatePredRedefs and StepForward to avoid duplication. NFC"Pete Cooper2015-05-052-29/+31
| | | | | | | | This reverts commit 963cdbccf6e5578822836fd9b2ebece0ba9a60b7 (ie r236514) This is to get the bots green while i investigate. llvm-svn: 236518
* Revert "Fix IfConverter to handle regmask machine operands."Pete Cooper2015-05-051-14/+0
| | | | | | | | This reverts commit b27413cbfd78d959c18e713bfa271fb69e6b3303 (ie r236515). This is to get the bots green while i investigate the failures. llvm-svn: 236517
* Fix IfConverter to handle regmask machine operands.Pete Cooper2015-05-051-0/+14
| | | | | | | | | | A regmask (typically seen on a call) clobbers the set of registers it lists. The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks. These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier. Otherwise, uses after the if converted call could think they are reading an undefined register. Reviewed by Matthias Braun and Quentin Colombet. llvm-svn: 236515
* Refactor UpdatePredRedefs and StepForward to avoid duplication. NFCPete Cooper2015-05-052-31/+29
| | | | | | | | The code was basically the same here already. Just added an out parameter for a vector of seen defs so that UpdatePredRedefs can call StepForward first, then do its own post processing on the seen defs. Will be used in the next commit to also handle regmasks. llvm-svn: 236514
* Update BasicAliasAnalysis to understand that nothing aliases with undef values.Daniel Berlin2015-05-051-0/+5
| | | | | | | | | | It got this in some cases (if one of them was an identified object), but not in all cases. This caused stores to undef to block load-forwarding in some cases, etc. Added test to Transforms/GVN to verify optimization occurs as expected. llvm-svn: 236511
* [opaque pointer type] Track explicit GEP pointee type through in-memory IRDavid Blaikie2015-05-053-4/+9
| | | | llvm-svn: 236510
* Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"Reid Kleckner2015-05-057-6/+343
| | | | | | | | | | | | This reverts commit r236360. This change exposed a bug in WinEHPrepare by opting win32 code into EH preparation. We already knew that WinEHPrepare has bugs, and is the status quo for x64, so I don't think that's a reason to hold off on this change. I disabled exceptions in the sanitizer tests in r236505 and an earlier revision. llvm-svn: 236508
* [ShrinkWrap] Add (a simplified version) of shrink-wrapping.Quentin Colombet2015-05-0537-112/+632
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new pass that computes the safe point to insert the prologue and epilogue of the function. The interest is to find safe points that are cheaper than the entry and exits blocks. As an example and to avoid regressions to be introduce, this patch also implements the required bits to enable the shrink-wrapping pass for AArch64. ** Context ** Currently we insert the prologue and epilogue of the method/function in the entry and exits blocks. Although this is correct, we can do a better job when those are not immediately required and insert them at less frequently executed places. The job of the shrink-wrapping pass is to identify such places. ** Motivating example ** Let us consider the following function that perform a call only in one branch of a if: define i32 @f(i32 %a, i32 %b) { %tmp = alloca i32, align 4 %tmp2 = icmp slt i32 %a, %b br i1 %tmp2, label %true, label %false true: store i32 %a, i32* %tmp, align 4 %tmp4 = call i32 @doSomething(i32 0, i32* %tmp) br label %false false: %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ] ret i32 %tmp.0 } On AArch64 this code generates (removing the cfi directives to ease readabilities): _f: ; @f ; BB#0: stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething LBB0_2: ; %false mov sp, x29 ldp x29, x30, [sp], #16 ret With shrink-wrapping we could generate: _f: ; @f ; BB#0: cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething add sp, x29, #16 ; =16 ldp x29, x30, [sp], #16 LBB0_2: ; %false ret Therefore, we would pay the overhead of setting up/destroying the frame only if we actually do the call. ** Proposed Solution ** This patch introduces a new machine pass that perform the shrink-wrapping analysis (See the comments at the beginning of ShrinkWrap.cpp for more details). It then stores the safe save and restore point into the MachineFrameInfo attached to the MachineFunction. This information is then used by the PrologEpilogInserter (PEI) to place the related code at the right place. This pass runs right before the PEI. Unlike the original paper of Chow from PLDI’88, this implementation of shrink-wrapping does not use expensive data-flow analysis and does not need hack to properly avoid frequently executed point. Instead, it relies on dominance and loop properties. The pass is off by default and each target can opt-in by setting the EnableShrinkWrap boolean to true in their derived class of TargetPassConfig. This setting can also be overwritten on the command line by using -enable-shrink-wrap. Before you try out the pass for your target, make sure you properly fix your emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not necessarily the entry block. ** Design Decisions ** 1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but for debugging and clarity I thought it was best to have its own file. 2. Right now, we only support one save point and one restore point. At some point we can expand this to several save point and restore point, the impacted component would then be: - The pass itself: New algorithm needed. - MachineFrameInfo: Hold a list or set of Save/Restore point instead of one pointer. - PEI: Should loop over the save point and restore point. Anyhow, at least for this first iteration, I do not believe this is interesting to support the complex cases. We should revisit that when we motivating examples. Differential Revision: http://reviews.llvm.org/D9210 <rdar://problem/3201744> llvm-svn: 236507
* [Orc] Reapply r236465 with fixes for the MSVC bots.Lang Hames2015-05-053-178/+87
| | | | llvm-svn: 236506
* This patch adds ABI support for v1i128 data type.Kit Barton2015-05-055-13/+46
| | | | | | | | | | | | It adds v1i128 to the appropriate register classes and checks parameter passing and return values. This is related to http://reviews.llvm.org/D9081, which will add instructions that exploit the v1i128 datatype. Phabricator review: http://reviews.llvm.org/D9475 llvm-svn: 236503
* Emit comment for gc.relocate showing base and derived pointers in human ↵Igor Laevsky2015-05-051-0/+21
| | | | | | | | readable form. Differential Revision: http://reviews.llvm.org/D9326 llvm-svn: 236497
* [mips] Generate code for insert/extract operations when using the N64 ABI ↵Daniel Sanders2015-05-052-17/+146
| | | | | | | | | | | | | | | | | | | | | | and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
* Fix regression in parsing armv{6,7}hl- triples. These are used by SUSEIsmail Donmez2015-05-051-2/+3
| | | | | | | | and Redhat currently. Reviewed by Jonathan Roelofs. llvm-svn: 236492
* [mips][msa] Test basic operations for the N32 ABI too.Daniel Sanders2015-05-052-3/+13
| | | | | | | | | | | | | | | | | Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
* [lib/Fuzzer] use handle_abort=1 by default so that when assert() fires we ↵Kostya Serebryany2015-05-051-1/+2
| | | | | | save the test case llvm-svn: 236476
* [Orc] Revert r236465 - It broke the Windows bots.Lang Hames2015-05-043-87/+178
| | | | | | | Looks like the usual missing explicit move-constructor issue with MSVC. I should have a fix shortly. llvm-svn: 236472
* [X86] Fix assertion while DAG combining offsets and ExternalSymbolsReid Kleckner2015-05-041-1/+4
| | | | | | ExternalSymbol nodes do not contain offsets, unlike GlobalValue nodes. llvm-svn: 236471
* [ARM] IT block insertion needs to update kill flagsPete Cooper2015-05-041-0/+14
| | | | | | | | | | | | | | | | | When forming an IT block from the first MOV here: %R2<def> = t2MOVr %R0, pred:1, pred:%CPSR, opt:%noreg %R3<def> = tMOVr %R0<kill>, pred:14, pred:%noreg the move in to R3 is moved out of the IT block so that later instructions on the same predicate can be inside this block, and we can share the IT instruction. However, when moving the R3 copy out of the IT block, we need to clear its kill flags for anything in use at this point in time, ie, R0 here. This appeases the machine verifier which thought that R0 wasn't defined when used. I have a test case, but its extremely register allocator specific. It would be too fragile to commit a test which depends on the register allocator here. llvm-svn: 236468
* [Orc] Refactor the compile-on-demand layer to make module partitioning lazy,Lang Hames2015-05-043-178/+87
| | | | | | | | | | | | | | | and avoid cloning unused decls into every partition. Module partitioning showed up as a source of significant overhead when I profiled some trivial test cases. Avoiding the overhead of partitionging for uncalled functions helps to mitigate this. This change also means that it is no longer necessary to have a LazyEmittingLayer underneath the CompileOnDemand layer, since the CompileOnDemandLayer will not extract or emit function bodies until they are called. llvm-svn: 236465
* CodeGen: match up correct insertvalue indices when assessing tail calls.Tim Northover2015-05-041-1/+2
| | | | | | | | | | | | When deciding whether a value comes from the aggregate or inserted value of an insertvalue instruction, we compare the indices against those of the location we're interested in. One of the lists needs reversing because the input data is backwards (so that modifications take place at the end of the SmallVector), but we were reversing both before leading to incorrect results. Should fix PR23408 llvm-svn: 236457
* YAML: Add an optional 'flow' field to the mapping trait to allow flow ↵Alex Lorenz2015-05-041-4/+46
| | | | | | | | | | | | | mapping output. This patch adds an optional 'flow' field to the MappingTrait class so that yaml IO will be able to output flow mappings. Reviewers: Justin Bogner Differential Revision: http://reviews.llvm.org/D9450 llvm-svn: 236456
* Respect object format choice on DarwinKeno Fischer2015-05-041-1/+1
| | | | | | | | | | | | | | | Summary: The object format can be set to something other than MachO, e.g. to use ELF-on-Darwin for MCJIT. This already works on Windows, so there's no reason it shouldn't on Darwin. Reviewers: lhames, grosbach Subscribers: rafael, grosbach, t.p.northover, llvm-commits Differential Revision: http://reviews.llvm.org/D6185 llvm-svn: 236455
* Fix -Wmicrosoft warning by making enum unsignedReid Kleckner2015-05-041-1/+1
| | | | llvm-svn: 236436
* [IR/Diagnostic] Assert that DebugLoc is valid before accessing.Davide Italiano2015-05-041-0/+1
| | | | | | | | PR: 23380 Differential Revision: http://reviews.llvm.org/D9464 Reviewed by: dexonsmith llvm-svn: 236435
* Option parsing: properly handle flag aliases for joined options (PR23394)Hans Wennborg2015-05-041-0/+5
| | | | | | | | | A joined option always needs to have an argument, even if it's an empty one. Clang would previously assert when trying to use --extra-warnings, which is a flag alias for -W, which is a joined option. llvm-svn: 236434
* [SystemZ] Reclassify f32 subregs of f64 registersUlrich Weigand2015-05-043-6/+8
| | | | | | | | | | | | | | | | | | | | | At the moment, all subregs defined by the SystemZ target can be modified independently of the wider register. E.g. writing to a GR32 does not change the upper 32 bits of the GR64. Writing to an FP32 does not change the lower 32 bits of the FP64. Hoewver, the upcoming support for the vector extension redefines FP64 as one half of a V128. Floating-point operations leave the other half of a V128 in an unpredictable state, so it's no longer the case that writing to an FP32 leaves the bits of the underlying register (the V128) alone. I'd prefer to have separate subreg_ names for this situation, so that it's obvious at a glance whether we're talking about a subreg that leaves the other parts of the register alone. No behavioral change intended. Patch originally by Richard Sandiford. llvm-svn: 236433
* [SystemZ] Clean up AsmParser isMem() handlingUlrich Weigand2015-05-041-35/+41
| | | | | | | | | | | | We know what MemoryKind an operand has at the time we construct it, so we might as well just record it in an unused part of the structure. This makes it easier to add scatter/gather addresses later. No behavioral change intended. Patch originally by Richard Sandiford. llvm-svn: 236432
* [SystemZ] Fix getTargetNodeNameUlrich Weigand2015-05-041-1/+5
| | | | | | | | It seems SystemZTargetLowering::getTargetNodeName got out of sync with some recent changes to the SystemZISD opcode list. Add back all the missing opcodes (and re-sort to the same order as SystemISelLowering.h). llvm-svn: 236430
* ScheduleDAGInstrs should toggle kill flags on bundled instrs.Pete Cooper2015-05-041-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | ScheduleDAGInstrs wasn't setting or clearing the kill flags on instructions inside bundles. This led to code such as this %R3<def> = t2ANDrr %R0 BUNDLE %ITSTATE<imp-def,dead>, %R0<imp-use,kill> t2IT 1, 24, %ITSTATE<imp-def> R6<def,tied6> = t2ORRrr %R0<kill>, ... being transformed to BUNDLE %ITSTATE<imp-def,dead>, %R0<imp-use> t2IT 1, 24, %ITSTATE<imp-def> R6<def,tied6> = t2ORRrr %R0<kill>, ... %R3<def> = t2ANDrr %R0<kill> where the kill flag was removed from the BUNDLE instruction, but not the t2ORRrr inside it. The verifier then thought that R0 was undefined when read by the AND. This change make the toggleKillFlags method also check for bundles and toggle flags on bundled instructions. Setting the kill flag is special cased as we only want to set the kill flag on the last instruction in the bundle. llvm-svn: 236428
* R600/SI: Code cleanupTom Stellard2015-05-041-3/+2
| | | | | | This is a follow-up to r236004 llvm-svn: 236427
* AVX-512: added calling convention for i1 vectors in 32-bit mode.Elena Demikhovsky2015-05-045-62/+62
| | | | | | | Fixed some bugs in extend/truncate for AVX-512 target. Removed VBROADCASTM (masked broadcast) node, since it is not used any more. llvm-svn: 236420
* AVX-512: added integer "add" and "sub" instructions with saturation for SKXElena Demikhovsky2015-05-044-1/+40
| | | | | | | | with intrinsics and tests by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 236418
* AVX-512: Added VPACK* instructions forms for KNL and SKXElena Demikhovsky2015-05-042-0/+83
| | | | | | | and their intrinsics by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 236414
* Replace windows_error calls with mapWindowsError.Yaron Keren2015-05-042-34/+26
| | | | | | | | After r210687, windows_error does nothing but call mapWindowsError. Other Windows/*.inc files directly call mapWindowsError. This patch updates Path.inc and Process.inc to do the same. llvm-svn: 236409
* [TableGen] Replace 'static_cast' with 'cast'.Craig Topper2015-05-041-1/+1
| | | | llvm-svn: 236398
* [TableGen] Formatting cleanup. Mostly removing trailing whitespace and ↵Craig Topper2015-05-042-100/+59
| | | | | | unnecessary curly braces. NFC llvm-svn: 236397
* Masked gather and scatter intrinsics - enabled codegen for KNL.Elena Demikhovsky2015-05-034-3/+238
| | | | llvm-svn: 236394
* [SSE2] Minor tidyup of v16i8 SHL lowering. NFC.Simon Pilgrim2015-05-021-16/+5
| | | | | | Removed code that was replicating v8i16 'shift + mask' implementation that is done more nicely by making use of LowerScalarImmediateShift llvm-svn: 236388
* [DAGCombiner] Enabled vector float/double -> int constant foldingSimon Pilgrim2015-05-022-4/+4
| | | | llvm-svn: 236387
* DebugInfo: Use low_pc relative debug_ranges under fission when the CU has a ↵David Blaikie2015-05-021-1/+1
| | | | | | | | | low_pc Seems we were setting the base address on the wrong DwarfCompileUnit object so it wasn't being used when generating the ranges. llvm-svn: 236377
* Fix spelling.Jim Grosbach2015-05-021-1/+1
| | | | llvm-svn: 236367
* Revert "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"Reid Kleckner2015-05-017-343/+6
| | | | | | This reverts commit r236359. Things are still broken despite testing. :( llvm-svn: 236360
* Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"Reid Kleckner2015-05-017-6/+343
| | | | | | This reverts commit r236340. llvm-svn: 236359
* [AArch64][FastISel] Variant of the logical instructions that use two inputQuentin Colombet2015-05-011-1/+1
| | | | | | | | registers cannot write on SP. rdar://problem/20748715 llvm-svn: 236352
* [Hexagon] Removing variable unused in release.Colin LeMahieu2015-05-011-2/+1
| | | | llvm-svn: 236351
* [Hexagon] Adding expression MC emission and removing XFAIL from test that ↵Colin LeMahieu2015-05-017-9/+646
| | | | | | hits this code path. llvm-svn: 236348
* [AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences.Quentin Colombet2015-05-011-2/+8
| | | | | | rdar://problem/20748715 llvm-svn: 236346
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