summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [AVR] Set UseIntegratedAssemblerDylan McKay2017-02-181-0/+1
| | | | llvm-svn: 295535
* OptDiag: Allow constructing DiagnosticLocation from DISubprogramsJustin Bogner2017-02-182-3/+10
| | | | | | | | This avoids creating a DILocation just to represent a line number, since creating Metadata is expensive. Creating a DiagnosticLocation directly is much cheaper. llvm-svn: 295531
* Don't assume little endian in StreamReader / StreamWriter.Zachary Turner2017-02-1815-152/+75
| | | | | | | In an effort to generalize this so it can be used by more than just PDB code, we shouldn't assume little endian. llvm-svn: 295525
* OptDiag: Decouple backend diagnostics from debug info metadataJustin Bogner2017-02-182-52/+49
| | | | | | | | | This creates and uses a DiagnosticLocation type rather than using DebugLoc for this purpose in the backend diagnostics. This is NFC for now, but will allow us to create locations for diagnostics without having to create new metadata nodes when we don't have a DILocation. llvm-svn: 295519
* MachineRegionInfo: Fix pass initializationMatthias Braun2017-02-183-9/+14
| | | | | | | | | | | | | | | | - Adapt MachineBasicBlock::getName() to have the same behavior as the IR BasicBlock (Value::getName()). - Add it to lib/CodeGen/CodeGen.cpp::initializeCodeGen so that it is linked in the CodeGen library. - MachineRegionInfoPass's name conflicts with RegionInfoPass's name ("region"). - MachineRegionInfo should depend on MachineDominatorTree, MachinePostDominatorTree and MachineDominanceFrontier instead of their respective IR versions. - Since there were no tests for this, add a X86 MIR test. Patch by Francis Visoiu Mistrih<fvisoiumistrih@apple.com> llvm-svn: 295518
* Verifier: Disallow a line number without a file in DISubprogramJustin Bogner2017-02-171-0/+2
| | | | | | | | A line number doesn't make much sense if you don't say where it's from. Add a verifier check for this and update some tests that had bogus debug info. llvm-svn: 295516
* AArch64LoadStoreOptimizer: Correctly clear kill flagsMatthias Braun2017-02-171-2/+4
| | | | | | | | | | | When promoting the Load of a Store-Load pair to a COPY all kill flags between the store and the load need to be cleared. rdar://30402435 Differential Revision: https://reviews.llvm.org/D30110 llvm-svn: 295512
* [PPC] Give unaligned memory access lower cost on processor that supports itGuozhi Wei2017-02-171-0/+4
| | | | | | | | | | | | Newer ppc supports unaligned memory access, it reduces the cost of unaligned memory access significantly. This patch handles this case in PPCTTIImpl::getMemoryOpCost. This patch fixes pr31492. Differential Revision: https://reviews.llvm.org/D28630 This is resubmit of r292680, which was reverted by r293092. The internal application failures were actually caused by a source code bug. llvm-svn: 295506
* [CodeGen] Revert changes in LowLevelType to pre-r295499 to fix broken buildbots.Eugene Zelenko2017-02-171-7/+1
| | | | llvm-svn: 295505
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-1718-116/+271
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* [NewGVN] isOnlyReachableViaThisEdge() is dead now. NFCI.Davide Italiano2017-02-171-18/+0
| | | | llvm-svn: 295503
* [X86] Simplify by pulling out valuetype. NFCI.Simon Pilgrim2017-02-171-2/+2
| | | | llvm-svn: 295502
* [NewGVN] createVariableOrConstant is not required anymore. NFCI.Davide Italiano2017-02-171-8/+0
| | | | llvm-svn: 295500
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-02-176-26/+63
| | | | | | other minor fixes (NFC). llvm-svn: 295499
* [LAA] Remove unused code (NFC)Matthew Simpson2017-02-171-5/+0
| | | | llvm-svn: 295493
* [X86][SSE] Add (V)MOVD folding pattern with zextloadi64i32 load node.Simon Pilgrim2017-02-172-0/+6
| | | | | | Fixes PRPR31309 llvm-svn: 295492
* AMDGPU: Fix crashes on invalid icmp/fcmp intrinsicsMatt Arsenault2017-02-171-5/+9
| | | | llvm-svn: 295489
* WholeProgramDevirt: For VCP use a 32-bit ConstantInt for the byte offset.Peter Collingbourne2017-02-171-1/+1
| | | | | | | | | | | | | | | A future change will cause this byte offset to be inttoptr'd and then exported via an absolute symbol. On the importing end we will expect the symbol to be in range [0,2^32) so that it will fit into a 32-bit relocation. The problem is that on 64-bit architectures if the offset is negative it will not be in the correct range once we inttoptr it. This change causes us to use a 32-bit integer so that it can be inttoptr'd (which zero extends) into the correct range. Differential Revision: https://reviews.llvm.org/D30016 llvm-svn: 295487
* Debug Info: Sort frame index expressions before emitting them.Adrian Prantl2017-02-173-36/+44
| | | | | | | | | | This fixes PR31381, which caused an assertion and/or invalid debug info. This affects debug variables that have multiple fragments in the MMI side (i.e.: in the stack frame) table. rdar://problem/30571676 llvm-svn: 295486
* In Thumb1 mode, the custom lowering for ARMISD::CMPZ could never emit tADDi3Artyom Skrobov2017-02-171-17/+14
| | | | | | | | | | | | Reviewers: jmolloy, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D30097 llvm-svn: 295478
* GlobalISel: verify that generic loads & stores have a mem operand.Tim Northover2017-02-171-0/+8
| | | | | | | The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
* [AArch64] Add Cavium ThunderX supportJoel Jones2017-02-175-2/+415
| | | | | | | | | | | | | | This set of patches adds support for Cavium ThunderX ARM64 processors: * ThunderX * ThunderX T81 * ThunderX T83 * ThunderX T88 Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D28891 llvm-svn: 295475
* WholeProgramDevirt: Examine the function body when deciding whether ↵Peter Collingbourne2017-02-171-12/+41
| | | | | | | | | | functions are readnone. The goal is to get an analysis result even for de-refineable functions. Differential Revision: https://reviews.llvm.org/D29803 llvm-svn: 295472
* OptDiag: Rename DiagnosticInfoWithDebugLoc to WithLocation. NFCJustin Bogner2017-02-171-3/+3
| | | | | | | This generalizes the name in preparation for decoupling the concept from DebugLoc. llvm-svn: 295465
* MC/COFF: Do not emit forward associative section referenceds.Rui Ueyama2017-02-171-26/+53
| | | | | | | | | | | | | | | | MSVC link.exe cannot handle associative sections that refer later sections in the section header. Technically, such COFF object doesn't violate the Microsoft COFF spec, as the spec doesn't say anything about that, but still we should avoid doing that to make it compatible with MS tools. This patch assigns smaller section numbers to non-associative sections and larger numbers to associative sections. This should resolve the compatibility issue. Differential Revision: https://reviews.llvm.org/D30080 llvm-svn: 295464
* [DAGCombiner] split i1 select-of-constants from non-i1 case; NFCISanjay Patel2017-02-171-9/+25
| | | | | | I can't find any tests of the non-i1 code path, so it may be unnecessary at this point. llvm-svn: 295463
* [LV] Remove constant restriction for vector phi creationMatthew Simpson2017-02-171-44/+37
| | | | | | | | | | | | We previously only created a vector phi node for an induction variable if its step had a constant integer type. However, the step actually only needs to be loop-invariant. We only handle inductions having loop-invariant steps, so this patch should enable vector phi node creation for all integer induction variables that will be vectorized. Differential Revision: https://reviews.llvm.org/D29956 llvm-svn: 295456
* Fix signed/unsigned comparison warning.Simon Pilgrim2017-02-171-2/+2
| | | | llvm-svn: 295453
* [ARM] Replace HasT2ExtractPack with HasDSPSam Parker2017-02-176-136/+98
| | | | | | | | | | | Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
* [DAGCombine] Recognise any_extend_vector_inreg and truncation style shuffle ↵Simon Pilgrim2017-02-171-0/+125
| | | | | | | | | | | | | | masks During legalization we are often creating shuffles (via a build_vector scalarization stage) that are "any_extend_vector_inreg" style masks, and also other masks that are the equivalent of "truncate_vector_inreg" (if we had such a thing). This patch is an attempt to match these cases to help undo the effects of just leaving shuffle lowering to handle it - which typically means we lose track of the undefined elements of the shuffles resulting in an unnecessary extension+truncation stage for widened illegal types. The 2011-10-21-widen-cmp.ll regression will be fixed by making SIGN_EXTEND_VECTOR_IN_REG legal in SSE instead of lowering them to X86ISD::VSEXT (PR31712). Differential Revision: https://reviews.llvm.org/D29454 llvm-svn: 295451
* [DAGCombiner] improve readability; NFCISanjay Patel2017-02-171-44/+32
| | | | llvm-svn: 295447
* [ARM] GlobalISel: Clean up some helpersDiana Picus2017-02-171-19/+24
| | | | | | | Return invalid opcodes when some of the helpers in the instruction selection pass can't handle a given combination. llvm-svn: 295446
* [ARM] GlobalISel: Check mappings used by reg bank selectDiana Picus2017-02-171-21/+120
| | | | | | | | Add some asserts to make sure we're using the mappings that we think we're using. This is to keep us from accidentally breaking functionality while moving to TableGen'erated mappings. llvm-svn: 295441
* [ARM] GlobalISel: Use Subtarget in LegalizerDiana Picus2017-02-173-13/+11
| | | | | | | | Start using the Subtarget to make decisions about what's legal. In particular, we only mark floating point operations as legal if we have VFP2, which is something we should've done from the very start. llvm-svn: 295439
* InstCombine: fix extraction when performing vector/array punningEugene Leviant2017-02-171-1/+1
| | | | | | Differential revision: https://reviews.llvm.org/D29491 llvm-svn: 295429
* [IR][X86] Simplify some AutoUpgrade code slightly. NFCCraig Topper2017-02-171-3/+2
| | | | llvm-svn: 295426
* [IR][X86] Rename an AutoUpgrade helper function to more accurately match ↵Craig Topper2017-02-171-6/+6
| | | | | | what intrinsics it handles. NFC llvm-svn: 295425
* [IR][X86] Move X86 specific portions of UpgradeIntrinsicFunction1 to a ↵Craig Topper2017-02-171-233/+248
| | | | | | | | couple helper functions. NFC This enables some early outs to avoid repeatedly using IsX86 check to qualify. I hope to continue to improve this to shorten the lengths of some of the string comparisons. llvm-svn: 295424
* [JumpThreading] Re-enable JumpThreading for guardsSanjoy Das2017-02-172-15/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: JumpThreading for guards feature has been reverted at https://reviews.llvm.org/rL295200 due to the following problem: the feature used the following algorithm for detection of diamond patters: 1. Find a block with 2 predecessors; 2. Check that these blocks have a common single parent; 3. Check that the parent's terminator is a branch instruction. The problem is that these checks are insufficient. They may pass for a non-diamond construction in case if those two predecessors are actually the same block. This may happen if parent's terminator is a br (either conditional or unconditional) to a block that ends with "switch" instruction with exactly two branches going to one block. This patch re-enables the JumpThreading for guards and fixes this issue by adding the check that those found predecessors are actually different blocks. This guarantees that parent's terminator is a conditional branch with exactly 2 different successors, which is now ensured by assertions. It also adds two more tests for this situation (with parent's terminator being a conditional and an unconditional branch). Patch by Max Kazantsev! Reviewers: anna, sanjoy, reames Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30036 llvm-svn: 295410
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-1718-270/+115
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* [XRAY] [x86_64] Adding a Flight Data filetype reader to the llvm-xray Trace ↵Dean Michael Berris2017-02-171-19/+304
| | | | | | | | | | | | | | | | | | | | | | | | implementation. Summary: The file type packs function trace data onto disk from potentially multiple threads that are aggregated and flushed during the course of an instrumented program's runtime. It is named FDR mode or Flight Data recorder as an analogy to plane blackboxes, which instrument a running system without access to IO. The writer code is defined in compiler-rt in xray_fdr_logging.h/cc Reviewers: rSerge, kcc, dberris Reviewed By: dberris Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29697 llvm-svn: 295397
* Bug 31948: Fix assertion when bitcasting constantexpr pointersMatt Arsenault2017-02-171-0/+6
| | | | llvm-svn: 295387
* Handle link of NoDebug CU with a CU that has debug emission enabledTeresa Johnson2017-02-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This is an issue both with regular and Thin LTO. When we link together a DICompileUnit that is marked NoDebug (e.g when compiling with -g0 but applying an AutoFDO profile, which requires location tracking in the compiler) and a DICompileUnit with debug emission enabled, we can have failures during dwarf debug generation. Specifically, when we have inlined from the NoDebug compile unit into the debug compile unit, we can fail during construction of the abstract and inlined scope DIEs. This is because the SPMap does not include NoDebug CUs (they are skipped in the debug_compile_units_iterator). This patch fixes the failures by skipping locations from NoDebug CUs when extracting lexical scopes. Reviewers: dblaikie, aprantl Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D29765 llvm-svn: 295384
* [IR] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-02-176-59/+115
| | | | | | minor fixes (NFC). llvm-svn: 295383
* [pdb] Add the ability to resolve TypeServer PDBs.Zachary Turner2017-02-169-9/+213
| | | | | | | | | | | | | | Some PDBs or object files can contain references to other PDBs where the real type information lives. When this happens, all type indices in the original PDB are meaningless because their records are not there. With this patch we add the ability to pull type info from those secondary PDBs. Differential Revision: https://reviews.llvm.org/D29973 llvm-svn: 295382
* [LSR] Prevent formula with SCEVAddRecExpr type of Reg from Sibling loopsWei Mi2017-02-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In rL294814, we allow formula with SCEVAddRecExpr type of Reg from loops other than current loop. This is good for the case when induction variable of outerloop being used in expr in innerloop. But it is very bad to allow such Reg from sibling loop because we may need to add lsr.iv in other sibling loops when scev expanding those SCEVAddRecExpr type exprs. For the testcase below, one loop can be inserted with a bunch of lsr.iv because of LSR for other loops. // The induction variable j from a loop in the middle will have initial // value generated from previous sibling loop and exit value used by its // next sibling loop. void goo(long i, long j); long cond; void foo(long N) { long i = 0; long j = 0; i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); } The fix is to only allow formula with SCEVAddRecExpr type of Reg from current loop or its parents. Differential Revision: https://reviews.llvm.org/D30021 llvm-svn: 295378
* Fix -Wunused-lambda-capture by removing some unused lambda capturesDavid Blaikie2017-02-161-2/+2
| | | | llvm-svn: 295373
* [MachinePipeliner] Remove redundant destructor. NFC.Benjamin Kramer2017-02-161-8/+1
| | | | llvm-svn: 295372
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-1618-115/+270
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* Change default TimerGroup singleton to use magic staticsErich Keane2017-02-161-16/+3
| | | | | | | | | | | TimerGroup was showing up on a leak in valigrind, and used some pretty complex code to implement a singleton. This patch replaces the implementation with a vastly simpler one. Differential Revision: https://reviews.llvm.org/D28367 llvm-svn: 295370
OpenPOWER on IntegriCloud