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* Use the local we already set up.Eric Christopher2011-09-291-1/+1
| | | | llvm-svn: 140745
* Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.Jakob Stoklund Olesen2011-09-291-81/+53
| | | | | | | | | | | | | | | | | | | | | | | The function needs to scan the implicit operands anyway, so no performance is won by caching the number of implicit operands added to an instruction. This also fixes a bug when adding operands after an implicit operand has been added manually. The NumImplicitOps count wasn't kept up to date. MachineInstr::addOperand() will now consistently place all explicit operands before all the implicit operands, regardless of the order they are added. It is possible to change an MI opcode and add additional explicit operands. They will be inserted before any existing implicit operands. The only exception is inline asm instructions where operands are never reordered. This is because of a hack that marks explicit clobber regs on inline asm as <implicit-def> to please the fast register allocator. This hack can go away when InstrEmitter and FastIsel can add exact <dead> flags to physreg defs. llvm-svn: 140744
* Revert r140731, "Define classes for unary and binary FP instructions and use ↵Jakob Stoklund Olesen2011-09-282-63/+55
| | | | | | | | them to define" It broke the unit tests. Please reapply with tests fixed. llvm-svn: 140735
* Tighten a ARM dag combine condition to avoid an identity transformation, whichEvan Cheng2011-09-281-1/+1
| | | | | | | | ends up introducing a cycle in the DAG. rdar://10196296 llvm-svn: 140733
* Define classes for unary and binary FP instructions and use them to defineAkira Hatanaka2011-09-282-55/+63
| | | | | | multiclasses. llvm-svn: 140731
* Have the SjLjEHPrepare pass do some more heavy lifting.Bill Wendling2011-09-281-34/+55
| | | | | | | | Upon further review, most of the EH code should remain written at the IR level. The part which breaks SSA form is the dispatch table, so that part will be moved to the back-end. llvm-svn: 140730
* PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU ↵Eli Friedman2011-09-281-0/+7
| | | | | | does not support them. llvm-svn: 140723
* Object: Add isSection{Data,BSS}.Michael J. Spencer2011-09-283-0/+58
| | | | llvm-svn: 140721
* Perform the lowering only if there are invokes.Bill Wendling2011-09-281-9/+19
| | | | llvm-svn: 140719
* Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.Bill Wendling2011-09-281-1/+1
| | | | llvm-svn: 140718
* PTX: Fix alignment logicJustin Holewinski2011-09-281-1/+1
| | | | llvm-svn: 140709
* Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.Akira Hatanaka2011-09-281-9/+10
| | | | llvm-svn: 140705
* Remove definitions of branch-on-FP-likely instructions. They are deprecated.Akira Hatanaka2011-09-281-4/+0
| | | | llvm-svn: 140704
* Mips64 predicate definitions. Patch by Liu.Akira Hatanaka2011-09-281-0/+7
| | | | llvm-svn: 140703
* indvars: generalize SCEV getPreStartForSignExtend.Andrew Trick2011-09-281-2/+14
| | | | | | | Handle general Add expressions to avoid leaving around redundant 32-bit IVs. llvm-svn: 140701
* PTX: MC-ize the PTX backend (patch 2 of N)Justin Holewinski2011-09-282-12/+3
| | | | | | Get rid of some of the no-longer-needed parts of PTXAsmPrinter. llvm-svn: 140698
* PTX: MC-ize the PTX back-end (patch 1 of N)Justin Holewinski2011-09-2819-64/+449
| | | | | | | | Lay some groundwork for converting to MC-based asm printer. This is the first of probably many patches to bring the back-end back up-to-date with all of the recent MC changes. llvm-svn: 140697
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-288-12/+128
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* A typeid of zero means a cleanup, not a catch. This case occursDuncan Sands2011-09-281-2/+4
| | | | | | when there is both a catch and a cleanup. Correct the comment. llvm-svn: 140686
* PTX: Simplify code. No functionality change.Benjamin Kramer2011-09-281-13/+5
| | | | llvm-svn: 140680
* PTX: Pass param name strings per const reference.Benjamin Kramer2011-09-282-7/+7
| | | | | | The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++) llvm-svn: 140679
* Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.Bill Wendling2011-09-281-1/+2
| | | | llvm-svn: 140678
* Bitcast the alloca to an i8* to match the intrinsic's signature.Bill Wendling2011-09-281-1/+4
| | | | llvm-svn: 140677
* Create and use an llvm.eh.sjlj.functioncontext intrinsic.Bill Wendling2011-09-282-0/+14
| | | | | | | | This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. llvm-svn: 140676
* In the new EH model, setup the function context and the call site info.Bill Wendling2011-09-281-1/+181
| | | | | | | | | | | | The DWARF exception pass uses the call site information, which is set up here. A pre-RA pass is too late for it to use this information. So create and setup the function context here, and then insert the call site values here (and map the call sites for the DWARF EH pass). This is simpler than the original pass, and doesn't make the CFG lose its SSA-ness. It's a win-win-win-win-lose-win-win situation. llvm-svn: 140675
* Don't conditionalize execution of the SjLj EH prepare pass.Bill Wendling2011-09-281-5/+1
| | | | | | | We may need an SjLj EH preparation pass for some call site information, at least in the short term. llvm-svn: 140674
* indvars should hoist [sz]ext because licm is not rerun.Andrew Trick2011-09-281-17/+27
| | | | llvm-svn: 140670
* PR10628: Fix getModRefInfo so it queries the underlying alias() ↵Eli Friedman2011-09-281-1/+1
| | | | | | implementation correctly while checking nocapture calls. llvm-svn: 140666
* Rename class and clean up source.Jakob Stoklund Olesen2011-09-281-25/+28
| | | | | | No functional change intended. llvm-svn: 140664
* Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.Jakob Stoklund Olesen2011-09-283-1/+1
| | | | | | I'll clean up the source in the next commit. llvm-svn: 140663
* Remove MipsFPRound. Mips1 is no longer supported.Akira Hatanaka2011-09-271-4/+0
| | | | llvm-svn: 140661
* Remove X86-dependent stuff from SSEDomainFix.Jakob Stoklund Olesen2011-09-273-21/+31
| | | | | | | | | This also enables domain swizzling for AVX code which required a few trivial test changes. The pass will be moved to lib/CodeGen shortly. llvm-svn: 140659
* Unbreak CMake build.Ted Kremenek2011-09-272-2/+3
| | | | llvm-svn: 140655
* Implement TII::get/setExecutionDomain() for ARM.Jakob Stoklund Olesen2011-09-272-0/+59
| | | | llvm-svn: 140653
* Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.Jakob Stoklund Olesen2011-09-273-10/+8
| | | | | | | | I am going to unify the SSEDomainFix and NEONMoveFix passes into a single target independent pass. They are essentially doing the same thing. llvm-svn: 140652
* ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.Jim Grosbach2011-09-271-0/+10
| | | | | | | | Add inst alias to handle these assembly forms. Add tests, too. rdar://10178799 llvm-svn: 140647
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-274-2/+127
| | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. llvm-svn: 140646
* Embed patterns in definitions of MFC1 and MTC1 instead of defining them outsideAkira Hatanaka2011-09-271-5/+4
| | | | | | of the instruction definitions using Pat<>. llvm-svn: 140644
* Remove an invalid assert that is really just asserting when the scheduler emitsCameron Zwarich2011-09-271-1/+0
| | | | | | a suboptimal schedule. llvm-svn: 140643
* Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().Jim Grosbach2011-09-273-4/+4
| | | | | | Naming conventions consistency. No functional change. llvm-svn: 140636
* Stop emitting instructions with the name "tmp" they eat up memory and have ↵Benjamin Kramer2011-09-2714-109/+86
| | | | | | | | to be uniqued, without any benefit. If someone prefers %tmp42 to %42, run instnamer. llvm-svn: 140634
* These symbols appear to be visible by SearchForAddressOfSymbol and no longer Chad Rosier2011-09-271-15/+0
| | | | | | | require special case handling. rdar://10117377 llvm-svn: 140629
* Object: Add archive support.Michael J. Spencer2011-09-273-1/+181
| | | | llvm-svn: 140626
* Check that catch clauses have pointer type.Duncan Sands2011-09-271-2/+7
| | | | llvm-svn: 140625
* PTX: Fix case where printed alignment could be 0Justin Holewinski2011-09-271-1/+1
| | | | llvm-svn: 140624
* PTX: Use external symbols to keep track of params and locals. This also fixesJustin Holewinski2011-09-276-55/+64
| | | | | | | a couple of outstanding issues with frame objects occuring as instruction operands. llvm-svn: 140616
* Use existing function.Jakob Stoklund Olesen2011-09-271-13/+1
| | | | llvm-svn: 140615
* Fix function MipsRegisterInfo::getRegisterNumbering.Akira Hatanaka2011-09-271-33/+81
| | | | | | Return numbers of 64-bit registers. llvm-svn: 140609
* Do not add the pass that restores $gp if target is Mips64.Akira Hatanaka2011-09-271-1/+4
| | | | llvm-svn: 140607
* Have the verifier check that all landingpad operands are constants.Duncan Sands2011-09-271-0/+11
| | | | llvm-svn: 140606
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