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* Revert [PowerPC] This reverts commit rL322721Zaara Syeda2018-01-179-275/+12
| | | | | | Failing build bots. Revert the commit now. llvm-svn: 322748
* [MDA] Use common code instead of reimplementing same. [NFC]Philip Reames2018-01-171-10/+2
| | | | llvm-svn: 322747
* [GISel] Make constrainSelectedInstRegOperands() available to the legalizer. NFCAditya Nandakumar2018-01-174-48/+50
| | | | | | https://reviews.llvm.org/D42149 llvm-svn: 322743
* [WebAssembly] Remove debug names from symbol tableSam Clegg2018-01-172-24/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Get rid of DEBUG_FUNCTION_NAME symbols. When we actually debug data, maybe we'll want somewhere to put it... but having a symbol that just stores the name of another symbol seems odd. It means you have multiple Symbols with the same name, one containing the actual function and another containing the name! Store the names in a vector on the WasmObjectFile when reading them in. Also stash them on the WasmFunctions themselves. The names are //not// "symbol names" or aliases or anything, they're just the name that a debugger should show against the function body itself. NB. The WasmObjectFile stores them so that they can be exported in the YAML losslessly, and hence the tests can be precise. Enforce that the CODE section has been read in before reading the "names" section. Requires minor adjustment to some tests. Patch by Nicholas Wilson! Differential Revision: https://reviews.llvm.org/D42075 llvm-svn: 322741
* Use a got to access a hidden weak undefined on MachO.Rafael Espindola2018-01-171-3/+1
| | | | | | | | | | | | | | | | | | | Trying to link __attribute__((weak, visibility("hidden"))) extern int foo; int *main(void) { return &foo; } on OS X fails with ld: 32-bit RIP relative reference out of range (-4294971318 max is +/-2GB): from _main (0x100000FAB) to _foo@0x00001000 (0x00000000) in '_main' from test.o for architecture x86_64 The problem being that 0 cannot be computed as a fixed difference from %rip. Exactly the same issue exists on ELF and we can use the same solution. llvm-svn: 322739
* [ARM] Optimize {s,u}mul.with.overflow.Joel Galenson2018-01-171-5/+32
| | | | | | | | This extends my previous patches to also optimize overflow-checked multiplies during SelectionDAG. Differential revision: https://reviews.llvm.org/D40922 llvm-svn: 322738
* [ARM] Optimize {s,u}{add,sub}.with.overflow.Joel Galenson2018-01-172-23/+76
| | | | | | | | The ARM backend contains code that tries to optimize compares by replacing them with an existing instruction that sets the flags the same way. This allows it to replace a "cmp" with a "adds", generalizing the code that replaces "cmp" with "sub". It also heuristically disables sinking of instructions that could potentially be used to replace compares (currently only if they're next to each other). Differential revision: https://reviews.llvm.org/D38378 llvm-svn: 322737
* [Attributes] Fix crash when attempting to remove alignment from an attribute ↵Daniel Neilson2018-01-171-24/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | list/set Summary: Discovered while working on a patch to move alignment in @llvm.memcpy/move/set from an arg into parameter attributes. The current implementations of AttributeSet::removeAttribute() and AttributeList::removeAttribute crash when attempting to remove the alignment attribute. Currently, these implementations add the to-be-removed attributes to an AttrBuilder and then remove the builder from the list/set. Alignment is special in that it must be added to a builder with an integer value for the alignment; attempts to add alignment to a builder without a value is an error. This change fixes the removeAttribute implementations for AttributeSet and AttributeList to make them able to remove the alignment, and other similar, attributes. Reviewers: rnk, chandlerc, pete, javed.absar, reames Reviewed By: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41951 llvm-svn: 322735
* [X86][BTVER2] Reduce instregex usage (PR35955)Simon Pilgrim2018-01-171-25/+29
| | | | | | Most are just replaced with instrs lists, but a few regexps have been further generalized to match more instructions with a single pattern. llvm-svn: 322734
* [X86] Teach LowerBUILD_VECTOR to recognize pair-wise splats of 32-bit ↵Craig Topper2018-01-171-0/+26
| | | | | | | | | | | | | | elements and use a 64-bit broadcast If we are splatting pairs of 32-bit elements, we can use a 64-bit broadcast to get the job done. We could probably could probably do this with other sizes too, for example four 16-bit elements. Or we could broadcast pairs of 16-bit elements using a 32-bit element broadcast. But I've left that as a future improvement. I've also restricted this to AVX2 only because we can only broadcast loads under AVX. Differential Revision: https://reviews.llvm.org/D42086 llvm-svn: 322730
* [X86] When legalizing (v64i1 select i8, v64i1, v64i1) make sure not to ↵Craig Topper2018-01-171-0/+12
| | | | | | | | | | | | introduce bitcasts to i64 in 32-bit mode We legalize selects of masks with scalar conditions using a bitcast to an integer type. But if we are in 32-bit mode we can't convert v64i1 to i64. So instead split the v64i1 to v32i1 and concat it back together. Each half will then be legalized by bitcasting to i32 which is fine. The test case is a little indirect. If we have the v64i1 select in IR it will get legalized by legalize vector ops which has a run of type legalization after it. That type legalization run is able to fix this i64 bitcast. So in order to avoid that we need a build_vector of a splat which legalize vector ops will ignore. Legalize DAG will then turn that into a select via LowerBUILD_VECTORvXi1. And the select will get legalized. In this case there is no type legalizer run to cleanup the bitcast. This fixes pr35972. llvm-svn: 322724
* [PowerPC] Add handling for ColdCC calling convention and a pass to markZaara Syeda2018-01-179-12/+275
| | | | | | | | | | | | | | | | candidates with coldcc attribute. This patch adds support for the coldcc calling convention for Power. This changes the set of non-volatile registers. It includes a pass to stress test the implementation by marking all static directly called functions with the coldcc attribute through the option -enable-coldcc-stress-test. It also includes an option, -ppc-enable-coldcc, to add the coldcc attribute to functions which are cold at all call sites based on BlockFrequencyInfo when the containing function does not call any non cold functions. Differential Revision: https://reviews.llvm.org/D38413 llvm-svn: 322721
* [ARC] Add missing condition codes.Tatyana Krasnukha2018-01-173-0/+10
| | | | | | | | | | | | | | Summary: Added VS and VC, required for disassembling. Reviewers: petecoup Reviewed By: petecoup Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42172 llvm-svn: 322718
* [SystemZ] Handle BRCTH branches correctly in SystemZLongBranch.cpp.Jonas Paulsson2018-01-171-1/+1
| | | | | | | | BRCTH is capable of a long branch which needs to be recognized during branch relaxation. This is done by checking for ExtraRelaxSize == 0. Review: Ulrich Weigand llvm-svn: 322688
* AMDGPU: Error in SIAnnotateControlFlow instead of assertMatt Arsenault2018-01-171-1/+5
| | | | | | | | This assert typically happens if an unstructured CFG is passed to the pass. This can happen if the pass is run independently without the structurizer. llvm-svn: 322685
* [ARM GlobalISel] Rename local variable. NFCDiana Picus2018-01-171-2/+2
| | | | llvm-svn: 322667
* [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endianPablo Barrio2018-01-171-18/+8
| | | | | | | | | | | | | | | | | | | | | Summary: Loading a vector of 4 half-precision FP sometimes results in an LD1 of 2 single-precision FP + a reversal. This results in an incorrect byte swap due to the conversion from little endian to big endian. In order to generate the correct byte swap, it is easier to generate the correct LD1 of 4 half-precision FP, thus avoiding the subsequent reversal. Reviewers: craig.topper, jmolloy, olista01 Reviewed By: olista01 Subscribers: efriedma, samparker, SjoerdMeijer, rogfer01, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41863 llvm-svn: 322663
* [InstCombine] fix demanded-bits propagation for zext/truncSanjay Patel2018-01-171-1/+1
| | | | | | | | | I was comparing the demanded-bits implementations between InstCombine and TargetLowering as part of investigating questions in D42088 and noticed that this was wrong in IR. We were losing all of the prior known bits when we got back to the 'zext'. llvm-svn: 322662
* [RISCV] Allow RISCVAsmBackend::writeNopData to generate c.nop when supportedAlex Bradbury2018-01-171-8/+18
| | | | | | | | | | When the compressed instruction set is enabled, the 16-bit c.nop can be generated if necessary. Differential Revision: https://reviews.llvm.org/D41221 Patch by Shiva Chen. llvm-svn: 322658
* [ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPRDiana Picus2018-01-171-0/+18
| | | | llvm-svn: 322657
* [AMDGPU] add LDS f32 intrinsicsDaniil Fukalov2018-01-178-11/+85
| | | | | | | | | | | | added llvm.amdgcn.atomic.{add|min|max}.f32 intrinsics to allow generate ds_{add|min|max}[_rtn]_f32 instructions needed for OpenCL float atomics in LDS Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D37985 llvm-svn: 322656
* [AMDGPU][MC][GFX9] Enable inline constants for SDWA operandsDmitry Preobrazhensky2018-01-175-65/+124
| | | | | | | | | See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771 Differential Revision: https://reviews.llvm.org/D42058 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322655
* [ARM GlobalISel] Legalize G_FPEXT and G_FPTRUNCDiana Picus2018-01-172-0/+59
| | | | | | | | | | | Mark G_FPEXT and G_FPTRUNC as legal or libcall, depending on hardware support, but only for conversions between float and double. Also add the necessary boilerplate so that the LegalizerHelper can introduce the required libcalls. This also works only for float and double, but isn't too difficult to extend when the need arises. llvm-svn: 322651
* [Transforms] Support making mutable versions of new-format TBAA access tagsIvan A. Kosarev2018-01-172-16/+29
| | | | | | Differential Revision: https://reviews.llvm.org/D41565 llvm-svn: 322650
* [X86] Don't mutate shuffle arguments after early-out for AVX512Benjamin Kramer2018-01-171-18/+22
| | | | | | | | | | The match* functions have the annoying behavior of modifying its inputs. Save and restore the inputs, just in case the early out for AVX512 is hit. This is still not great and its only a matter of time this kind of bug happens again, but I couldn't come up with a better pattern without rewriting significant chunks of this code. Fixes PR35977. llvm-svn: 322644
* [X86] Constify DebugLoc parameters. No functionality change.Benjamin Kramer2018-01-171-13/+10
| | | | llvm-svn: 322643
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-176-9/+9
| | | | | | "the the" -> "the" llvm-svn: 322636
* Don't emit apple accelerator tables on non-darwin targetsPavel Labath2018-01-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently -glldb turns on emission of apple tables on all targets, but lldb is only really capable of consuming them on darwin. Furthermore, making lldb consume these tables is not straight-forward because of the differences in how the debug info is distributed on darwin vs. elf targets. The darwin debug model assumes that the debug info (along with accelerator tables) will either remain in the .o files or it will be linked into a dsym bundle by a linker that knows how to merge these tables. In the elf world, all present linkers will simply concatenate these accelerator tables into the shared object. Since the tables are not self-terminating, this renders the tables unusable, as the debugger cannot pry the individual tables apart anymore. It might theoretically be possible to make the tables work with split dwarf, as that is somewhat similar to the apple .o model, but unfortunately right now the combination of -glldb and -gsplit-dwarf produces broken object files. Until these issues are resolved there is no point in emitting the apple tables for these targets. At best, it wastes space; at worst, it breaks compilation and prevents the user from getting other benefits of -glldb. Reviewers: probinson, aprantl, dblaikie Subscribers: emaste, dim, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D41986 llvm-svn: 322633
* [SCEV] fix typoJaved Absar2018-01-171-1/+1
| | | | llvm-svn: 322629
* [ThinLTO] - Remove code duplication. NFC.George Rimar2018-01-171-22/+17
| | | | | | | Refactors 3 copies of isExpected. Splitted from D42107. llvm-svn: 322627
* Allow usage of X86-prefixes as separate instrs.Andrew V. Tischenko2018-01-171-0/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D42102 llvm-svn: 322623
* [MC] Fix -stack-size-section on ARMSean Eveson2018-01-171-2/+1
| | | | | | | | Change symbol values in the stack_size section from being 8 bytes, to being a target dependent size. Differential Revision: https://reviews.llvm.org/D42108 llvm-svn: 322619
* [X86] In LowerBUILD_VECTOR, rename ExtVT to EltVT so it makes sense.Craig Topper2018-01-171-7/+7
| | | | llvm-svn: 322616
* [X86] Remove duplicate lines from scheduler models. NFCCraig Topper2018-01-174-8/+0
| | | | llvm-svn: 322615
* [Support] Return an enum instead of an unsigned; NFC.George Burgess IV2018-01-171-2/+2
| | | | | | | | | | | | | | We seem to be (logically) returning ArchExtKinds here in all cases, so the return type should reflect that. The static_cast is necessary because `A.ID` is actually an `unsigned`, presumably since we use `decltype(A)` to represent extended attributes for both ARM and AArch64, which use distinct `ArchExtKinds`. We can't trivially make the same change for ARM, because one of the values it returns is the bitwise-or of two `ARM::ArchExtKind`s. llvm-svn: 322613
* Fix pretty printing the unspecified param of a variadic functionAaron Smith2018-01-171-0/+19
| | | | | | | | | | | | | | | | | | | | | | | Summary: - Fix a bug in PrettyBuiltinDumper that returns "void" as the name for an unspecified builtin type. Since the unspecified param of a variadic function is considered a builtin of unspecified type in PDBs, we set "..." for its name. - Provide a method to determine if a PDBSymbolFunc is variadic in PrettyFunctionDumper since PDBSymbolFunc::getArgument() doesn't return the last unspecified-type param. - Add a pretty-func-dumper.test to test pretty dumping of variadic functions. Reviewers: zturner, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D41801 llvm-svn: 322608
* [hwasan] Rename sized load/store callbacks to be consistent with ASan.Evgeniy Stepanov2018-01-161-1/+1
| | | | | | | | | | | | Summary: __hwasan_load is now __hwasan_loadN. Reviewers: kcc Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D42138 llvm-svn: 322601
* [X86][BTVER2] Fix scheduling of VCMPSD/VCMPSS instructionsSimon Pilgrim2018-01-161-2/+2
| | | | | | For some reason they don't have a trailing i like the packed equivalents. llvm-svn: 322600
* [CallSiteSplitting] Pass list of (BB, Conditions) pairs to splitCallSite.Florian Hahn2018-01-161-76/+71
| | | | | | | | | | | | | | | This removes some duplication from splitCallSite and makes it easier to add additional code dealing with each predecessor. It also allows us to split for more than 2 predecessors, although that is not enabled for now. Reviewers: junbuml, mcrosier, davidxl, davide Reviewed By: junbuml Differential Revision: https://reviews.llvm.org/D41858 llvm-svn: 322599
* [X86][BTVER2] Use instrs instead of instregex for low match counts (PR35955)Simon Pilgrim2018-01-161-30/+22
| | | | llvm-svn: 322598
* [X86][BTVER2] Use instrs instead of instregex for single use matches (PR35955)Simon Pilgrim2018-01-161-36/+33
| | | | llvm-svn: 322597
* Specify inline for isWhitespace in CommandLine.cppRui Ueyama2018-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Takuto Ikuta. In chromium's component build, there are many directive sections and commandline parsing takes much time. This patch is for speed up of lld in RelWithDebInfo build by forcing inline heavily called isWhitespace function. 10 times link perf stats of blink_core.dll changed like below. master: TotalSeconds: 9.8764878 TotalSeconds: 10.1455242 TotalSeconds: 10.075279 TotalSeconds: 10.3397347 TotalSeconds: 9.8361665 TotalSeconds: 9.9544441 TotalSeconds: 9.8960686 TotalSeconds: 9.8877865 TotalSeconds: 10.0551879 TotalSeconds: 10.0492254 Avg: 10.01159047 with this patch: TotalSeconds: 8.8696762 TotalSeconds: 9.1021585 TotalSeconds: 9.0233893 TotalSeconds: 9.1886175 TotalSeconds: 9.156954 TotalSeconds: 9.0978564 TotalSeconds: 9.1316824 TotalSeconds: 8.8354606 TotalSeconds: 9.2549431 TotalSeconds: 9.4473085 Avg: 9.11080465 llvm-svn: 322595
* [ExecutionEngine] Rename JITSymbol::isStrongDefinition to isStrong.Lang Hames2018-01-162-4/+4
| | | | | | For symmetry with isWeak, isCommon. llvm-svn: 322594
* [PPC] Add a new register XER aliased to CARRYGuozhi Wei2018-01-161-2/+6
| | | | | | | | | | When "xer" is specified as clobbered register in inline assembler, clang can accept it, but llvm simply ignore it when lowered to machine instructions. It may cause problems later in scheduler. This patch adds a new register XER aliased to CARRY, and adds it to register class CARRYRC. Now PPCTargetLowering::getRegForInlineAsmConstraint can return correct register number for inline asm constraint "{xer}", and scheduler behave correctly. Differential Revision: https://reviews.llvm.org/D41967 llvm-svn: 322591
* [CodeGen] Skip some instructions that shouldn't affect shrink-wrappingFrancis Visoiu Mistrih2018-01-161-5/+5
| | | | | | | | | | | r320606 checked for MI.isMetaInstruction which skips all DBG_VALUEs. This also skips IMPLICIT_DEFs and other instructions that may def / read a register. Differential Revision: https://reviews.llvm.org/D42119 llvm-svn: 322584
* [GlobalISel][TableGen] Add support for SDNodeXFormVolkan Keles2018-01-162-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
* [SLP] Fix for PR32164: Improve vectorization of reverse order of extract ↵Alexey Bataev2018-01-161-10/+17
| | | | | | | | | | | | | | operations. Summary: Sometimes vectorization of insertelement instructions with extractelement operands may produce an extra shuffle operation, if these operands are in the reverse order. Patch tries to improve this situation by the reordering of the operands to remove this extra shuffle operation. Reviewers: mkuper, hfinkel, RKSimon, spatel Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D33954 llvm-svn: 322579
* [X86][MMX] Accept UNDEF upper bits for MOVD GR32->MMXSimon Pilgrim2018-01-161-3/+4
| | | | llvm-svn: 322574
* [LiveDebugValues] recognize spilled reg killed in instruction after spillPetar Jovanovic2018-01-161-7/+30
| | | | | | | | | | | Current condition for spill instruction recognition in LiveDebugValues does not recognize case when register is spilled and killed in next instruction. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D41226 llvm-svn: 322554
* [X86][MMX] Improve MMX constant generationSimon Pilgrim2018-01-161-3/+12
| | | | | | Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
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