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* [ORC][C-API] Expose LLVMOrc{Unr,R}egisterJITEventListener().Andres Freund2018-05-241-0/+11
| | | | | | | | Reviewed By: lhames Differential Revision: https://reviews.llvm.org/D44890 llvm-svn: 333229
* [ORC] Add ability [un]register JITEventListener on Orc C stack.Andres Freund2018-05-241-1/+40
| | | | | | | | Reviewed By: lhames Differential Revision: https://reviews.llvm.org/D44890 llvm-svn: 333228
* [ORC] Extend object layer callbacks so JITEventListener can be supported.Andres Freund2018-05-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | Currently RTDyldObjectLinkingLayer makes it hard to support JITEventListeners. Which in turn means debugging and profiling JIT generated code hard. Supporting JITEventListeners at minimum requries a freed callback (added). As listeners expect the ObjectFile to be passed as well, an adaptor between RTDyldObjectLinkingLayer and JITEventListeners would currently need to also maintain ObjectFiles for all loaded modules. To make that less awkward, extend the callbacks to pass the ObjectFile to both Finalized and Freed callbacks. That requires extending the lifetime of the object file when callbacks are present. Reviewed By: lhames Differential Revision: https://reviews.llvm.org/D44890 llvm-svn: 333227
* [ValueTracking] Teach computeKnownBits that the result of an absolute value ↵Craig Topper2018-05-241-0/+6
| | | | | | | | | | | | pattern that uses nsw flag is always positive. If the nsw flag is used in the absolute value then it is undefined for INT_MIN. For all other value it will produce a positive number. So we can assume the result is positive. This breaks some InstCombine abs/nabs combining tests because we simplify the second compare from known bits rather than as the whole pattern. Looks like we can probably fix it by adding a neg+abs/nabs combine to just swap the select operands. Need to check alive to make sure there are no corner cases. Differential Revision: https://reviews.llvm.org/D47041 llvm-svn: 333226
* [InstCombine] Enable more reassociations using FMF 'reassoc' + 'nsz'Warren Ristow2018-05-241-1/+2
| | | | | | | | | | | Reassociation of math ops in some contexts (especially vector contexts) has generally only been happening when the 'fast' FMF was set. This enables reassoication when only the finer grained controls 'reassoc' and 'nsz' are set. Differential Revision: https://reviews.llvm.org/D47335 llvm-svn: 333221
* AMDGPU: Split R600 AsmPrinter code into its own classTom Stellard2018-05-246-161/+303
| | | | | | | | | | | | Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D47245 llvm-svn: 333219
* [AArch64] Improve orr+movk sequences for MOVi64imm.Eli Friedman2018-05-241-115/+96
| | | | | | | | | | | | | | The existing code has three different ways to try to lower a 64-bit immediate to the sequence ORR+MOVK. The result is messy: it misses some possible sequences, and the order of the checks means we sometimes emit two MOVKs when we only need one. Instead, just use a simple loop to try all possible two-instruction ORR+MOVK sequences. Differential Revision: https://reviews.llvm.org/D47176 llvm-svn: 333218
* Add handling for GlobalAliases in ExecutionEngine::getConstantValue.Lang Hames2018-05-241-0/+3
| | | | | | | | Patch by Brad Moody. Thanks Brad! https://reviews.llvm.org/D42160 llvm-svn: 333217
* [ORC] Add findSymbolIn() wrapper to C bindings, take #2.Andres Freund2018-05-242-0/+30
| | | | | | | | | | | | | | | | Re-appply r333147, reverted in r333152 due to a pre-existing bug. As D47308 has been merged in r333206, the OSX issue should now be resolved. In many cases JIT users will know in which module a symbol resides. Avoiding to search other modules can be more efficient. It also allows to handle duplicate symbol names between modules. Reviewed By: lhames Differential Revision: https://reviews.llvm.org/D44889 llvm-svn: 333215
* [AArch64] Take advantage of variable shift/rotate amount implicit mod operation.Geoff Berry2018-05-241-0/+111
| | | | | | | | | | | | | | | | Summary: Optimize code generated for variable shifts/rotates by taking advantage of the implicit and/mod done on the variable shift amount register. Resolves bug 27582 and bug 37421. Reviewers: t.p.northover, qcolombet, MatzeB, javed.absar Subscribers: rengolin, kristof.beyls, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46844 llvm-svn: 333214
* [ORC] Perform name mangling in findSymbolIn(), as done in findSymbol().Andres Freund2018-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | The lack of name mangling caused a unittest failure after r333147 (in TestEagerIRCompilation), as OSX prefixes symbol names with '_'. The lack of name mangling therefore leads to a NULL pointer being returned and then called, hence the failure. While it may look like it, this isn't an actual behavioral change, as findSymbolIn() previously was not exposed externally, and essentially dead code. Which explains why nobody noticed the issue previously. Reviewers: lhames Reviewed By: lhames Subscribers: chandlerc, llvm-commits Differential Revision: https://reviews.llvm.org/D47308 llvm-svn: 333206
* [X86][SSE] Pull out (AND (XOR X, -1), Y) matching into a helper function. NFC.Simon Pilgrim2018-05-241-11/+26
| | | | llvm-svn: 333201
* [LICM] Preserve DT and LoopInfo specificallyJun Bum Lim2018-05-241-2/+6
| | | | | | | | | | | | | | | | | | | Summary: In LICM, CFG could be changed in splitPredecessorsOfLoopExit(), which update only DT and LoopInfo. Therefore, we should preserve only DT and LoopInfo specifically, instead of all analyses that depend on the CFG (setPreservesCFG()). This change should fix PR37323. Reviewers: uabelho, davide, dberlin, Ka-Ka Reviewed By: dberlin Subscribers: mzolotukhin, bjope, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46775 llvm-svn: 333198
* Fix unused variable warnings. NFCI.Simon Pilgrim2018-05-241-3/+0
| | | | llvm-svn: 333195
* [InstCombine] Combine XOR and AES instructions on ARM/ARM64.Chad Rosier2018-05-241-0/+17
| | | | | | | | | | | The ARM/ARM64 AESE and AESD instructions have a builtin XOR as the first step in the instruction. Therefore, if the AES key is zero and the AES data was previously XORed, it can be combined into a single instruction. Differential Revision: https://reviews.llvm.org/D47239 Patch by Michael Brase! llvm-svn: 333193
* [X86][SSE] Pull out OR(AND(~MASK,X),AND(MASK,Y)) matching into a helper ↵Simon Pilgrim2018-05-241-19/+34
| | | | | | | | function. NFC. First stage towards matching more variants of the bitselect pattern for combineLogicBlendIntoPBLENDV (PR37549) llvm-svn: 333191
* [X86][BtVer2] Added Jaguar cpu cycle counter to permit llvm-exegesis latency ↵Simon Pilgrim2018-05-241-0/+4
| | | | | | | | | testing Ideally we'd be able to test a CPU by using __builtin_readcyclecounter()/RDTSC instead (PR37193) if a model/cycle-counter is not specified. NOTE: Jaguar PMCs don't give good coverage of resource pipes specified in the model (at the macro-vs-micro-op levels) but we should be able to cover at least a few resources. llvm-svn: 333190
* [NFC][VPlan] Wrap PlainCFGBuilder with an anonymous namespace.Andrei Elovikov2018-05-241-0/+2
| | | | | | | | | | | | | | | | Summary: It's internal to the VPlanHCFGBuilder and should not be visible outside of its translation unit. Reviewers: dcaballe, fhahn Reviewed By: fhahn Subscribers: rengolin, bollu, tschuett, llvm-commits, rkruppe Differential Revision: https://reviews.llvm.org/D47312 llvm-svn: 333187
* [Support] Move header to WithColor headerJonas Devlieghere2018-05-241-1/+0
| | | | | | | Forgot to move the CommandLine.h include form the implementation to the header and didn't notice the failure with my local modules build. llvm-svn: 333177
* [Support] Add color cl category.Jonas Devlieghere2018-05-241-2/+4
| | | | | | | | | This commit adds a color category so tools can document this option and enables it for dwarfdump and dsymuttil. rdar://problem/40498996 llvm-svn: 333176
* [ScheduleDAGInstrs / buildSchedGraph] Clear subregister entries also.Jonas Paulsson2018-05-241-7/+8
| | | | | | | | | | | | | | | In addPhysRegDeps, subregister entries of the defined register were previously not removed from Uses or Defs, which resulted in extra redundant edges for subregs around the register definition. This is principally NFC (in very rare cases some node got a different height). This makes the DAG more readable and efficient in some cases. Review: Andy Trick https://reviews.llvm.org/D46838 llvm-svn: 333165
* [mips] Remove duplicated code from the expandLoadInst. NFCSimon Atanasyan2018-05-241-36/+17
| | | | llvm-svn: 333164
* [mips] Remove redundant argument from expandLoadInst/expandStoreInst. NFCSimon Atanasyan2018-05-241-15/+13
| | | | llvm-svn: 333163
* [mips] Add precondition asserts to the expandLoadInst/expandStoreInst. NFCSimon Atanasyan2018-05-241-12/+23
| | | | llvm-svn: 333162
* [mips] Cleanup the code a bit. NFCSimon Atanasyan2018-05-241-15/+25
| | | | llvm-svn: 333161
* [demangler] Add ItaniumPartialDemangler::isCtorOrDtorFangrui Song2018-05-241-0/+32
| | | | | | | | | | Reviewers: erik.pilkington, ruiu, echristo, pcc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47248 llvm-svn: 333159
* [RISCV] Support linker relax function call from auipc and jalr to jalShiva Chen2018-05-244-2/+17
| | | | | | | | | | | | | To do this: 1. Add fixup_riscv_relax fixup types which eventually will transfer to R_RISCV_RELAX relocation types. 2. Insert R_RISCV_RELAX relocation types to auipc function call expression when linker relaxation enabled. Differential Revision: https://reviews.llvm.org/D44886 llvm-svn: 333158
* [NaryReassociate] Detect deleted instr with WeakVHKarl-Johan Karlsson2018-05-241-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If NaryReassociate succeed it will, when replacing the old instruction with the new instruction, also recursively delete trivially dead instructions from the old instruction. However, if the input to the NaryReassociate pass contain dead code it is not save to recursively delete trivially deadinstructions as it might lead to deleting the newly created instruction. This patch will fix the problem by using WeakVH to detect this rare case, when the newly created instruction is dead, and it will then restart the basic block iteration from the beginning. This fixes pr37539 Reviewers: tra, meheff, grosser, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47139 llvm-svn: 333155
* AMDGPU/R600: Remove code for handling AMDGPUISD::CLAMPTom Stellard2018-05-248-56/+28
| | | | | | | | | | | | | | | | Summary: We don't generate AMDGPUISD::CLAMP for R600 now that llvm.AMDGPU.clamp is gone. Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D47181 llvm-svn: 333153
* Revert r333147 "[ORC] Add findSymbolIn() wrapper to C bindings."Andres Freund2018-05-242-30/+0
| | | | | | | | | | | This reverts r333147 until https://reviews.llvm.org/D47308 is ready to be reviewed. r333147 exposed a behavioural difference between OrcCBindingsStack::findSymbolIn() and OrcCBindingsStack::findSymbol(), where only the latter does name mangling. After r333147 that causes a test failure on OSX, because the new test looks for main using findSymbolIn() but the mangled name is _main. llvm-svn: 333152
* [PowerPC] Remove the match pattern in the definition of LXSDX/STXSDXLei Huang2018-05-241-2/+2
| | | | | | | | | | | | | | The match pattern in the definition of LXSDX is xoaddr, so the Pseudo instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post RA based on the register pressure. To avoid ambiguity, we need to remove the select pattern for LXSDX, same as what was done for LXSD. STXSDX also have the same issue. Patch by Qing Shan Zhang (steven.zhang). Differential Revision: https://reviews.llvm.org/D47178 llvm-svn: 333150
* [ORC] Add findSymbolIn() wrapper to C bindings.Andres Freund2018-05-242-0/+30
| | | | | | | | | | | | In many cases JIT users will know in which module a symbol resides. Avoiding to search other modules can be more efficient. It also allows to handle duplicate symbol names between modules. Reviewed By: lhames Differential Revision: https://reviews.llvm.org/D44889 llvm-svn: 333147
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-236-17/+157
| | | | | | | This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
* [DebugInfo] Maintain DI for sunken bitcastsVedant Kumar2018-05-231-0/+1
| | | | | | | | | | | | When a bitcast is being sunk in -codegenprepare pass, its DI wasn't copied over to the newly created instruction. This patch fixes that bug. Patch by Kareem Ergawy! Differential Revision: https://reviews.llvm.org/D47282 llvm-svn: 333133
* [RISCV] Set CostPerUse for registersSameer AbuAsal2018-05-231-0/+11
| | | | | | | | | | | | | | | | | | | Summary: Set CostPerUse higher for registers that are not used in the compressed instruction set. This will influence the greedy register allocator to reduce the use of registers that can't be encoded in 16 bit instructions. This affects register allocation even when compressed instruction isn't targeted, we see no major negative codegen impact. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang Differential Revision: https://reviews.llvm.org/D47039 llvm-svn: 333132
* [RuntimeDyld][MachO] Add support for MachO::ARM64_RELOC_POINTER_TO_GOT reloc.Lang Hames2018-05-231-8/+48
| | | | llvm-svn: 333130
* [LKH] Add a new IRTransformLayer.Lang Hames2018-05-232-0/+35
| | | | llvm-svn: 333129
* [LKH] Add ObjectTransformLayer2.Lang Hames2018-05-232-0/+35
| | | | llvm-svn: 333128
* [LKH] Add a new IRCompileLayer.Lang Hames2018-05-233-1/+46
| | | | llvm-svn: 333127
* [GlobalISel] NFCI, Getting GlobalISel ~5% fasterRoman Tereshin2018-05-233-25/+20
| | | | | | | | | | | | by replacing DenseMap with IndexedMap for LLTs within MRI, as benchmarked by cross-compiling sqlite3 amalgamation for AArch64 on x86 machine. Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46809 llvm-svn: 333125
* [Power9]Legalize and emit code for W vector extract and convert to QPLei Huang2018-05-231-5/+37
| | | | | | | | | Implemente patterns to extract [Un]signed Word vector element and convert to quad-precision. Differential Revision: https://reviews.llvm.org/D46536 llvm-svn: 333115
* [Power9]Legalize and emit code for DW vector extract and convert to QPLei Huang2018-05-231-0/+27
| | | | | | | | | Implemente patterns to extract [Un]signed DWord vector element and convert to quad-precision. Differential Revision: https://reviews.llvm.org/D46333 llvm-svn: 333112
* StructurizeCFG: Adjust the loop depth for a subregion to order the nodes ↵Changpeng Fang2018-05-231-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | correctly Summary: StructurizeCFG::orderNodes basically uses a reverse post-order (RPO) traversal of the region list to get the order. The only problem with it is that sometimes backedges for outer loops will be visited before backedges for inner loops. To solve this problem, a loop depth based approach has been used to make sure all blocks in this loop has been visited before moving on to outer loop. However, we found a problem for a SubRegion which is a loop itself: --> BB1 --> BB2 --> BB3 --> In this case, BB2 is a SubRegion (loop), and thus its loopdepth is different than that of BB1 and BB3. This fact will lead BB2 to be placed in the wrong order. In this work, we treat the SubRegion as a special case and use its exit block to determine the loop and its depth to guard the sorting. Reviewers: arsenm, jlebar Differential Revision: https://reviews.llvm.org/D46912 llvm-svn: 333111
* [CodeGen][AArch64] Use RegUnits to track register aliases. (NFC)Chad Rosier2018-05-231-40/+27
| | | | | | | | Use RegUnits to track register aliases in AArch64RedundantCopyElimination. Differential Revision: https://reviews.llvm.org/D47269 llvm-svn: 333107
* [InstCombine] Fold unfolded masked merge pattern with variable mask!Roman Lebedev2018-05-231-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Finally fixes [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]. Now that the backend is all done, we can finally fold it! The canonical unfolded masked merge pattern is ```(x & m) | (y & ~m)``` There is a second, equivalent variant: ```(x | ~m) & (y | m)``` Only one of them (the or-of-and's i think) is canonical. And if the mask is not a constant, we should fold it to: ```((x ^ y) & M) ^ y``` https://rise4fun.com/Alive/ndQw Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: nicholas, RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D46814 llvm-svn: 333106
* [Dominators] Add PDT constructor from FunctionJakub Kuderski2018-05-232-5/+4
| | | | | | | | | | | | | | | | Summary: This patch adds a PDT constructor from Function and lets codes previously using a local class to do this use PostDominatorTree class directly. Reviewers: davide, kuhar, grosser, dberlin Reviewed By: kuhar Author: NutshellySima Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46709 llvm-svn: 333102
* [InstCombine] Negate ABS/NABS patterns by swapping the select operands to ↵Craig Topper2018-05-231-0/+16
| | | | | | | | remove the negation Differential Revision: https://reviews.llvm.org/D47236 llvm-svn: 333101
* Silence warnings introduced with r333093Petar Jovanovic2018-05-231-1/+1
| | | | | | | | r333093 introduced several warnings (-Wlogical-not-parentheses, -Wbool-compare). Adding parentheses in MipsSEInstrInfo::isCopyInstr() to silence it. llvm-svn: 333097
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-2324-27/+166
| | | | | | | | | | | | | This property is needed in order to follow values movement between registers. This property is used in TII to implement method that returns true if simple copy like instruction is recognized, along with source and destination machine operands. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D45204 llvm-svn: 333093
* Remove DEBUG macro.Nicola Zaghen2018-05-234-6/+6
| | | | | | | | | | Now that the LLVM_DEBUG() macro landed on the various sub-projects the DEBUG macro can be removed. Also change the new uses of DEBUG to LLVM_DEBUG. Differential Revision: https://reviews.llvm.org/D46952 llvm-svn: 333091
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