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* [ORC] Remove the optional MaterializationResponsibility argument from lookup.Lang Hames2018-05-211-16/+10
| | | | | | | | The lookup function provides blocking symbol resolution for JIT clients (not layers themselves) so it does not need to track symbol dependencies via a MaterializationResponsibility. llvm-svn: 332897
* [ORC] Add IRLayer and ObjectLayer interfaces and related MaterializationUnits.Lang Hames2018-05-212-0/+111
| | | | llvm-svn: 332896
* [DAGCombiner] Use computeKnownBits to match rotate patterns that have had ↵Craig Topper2018-05-211-7/+18
| | | | | | | | | | | | | | | | their amount masking modified by simplifyDemandedBits SimplifyDemandedBits can remove bits from the masks for the shift amounts we need to see to detect rotates. This patch uses zeroes from computeKnownBits to fill in some of these mask bits to make the match work. As currently written this calls computeKnownBits even when the mask hasn't been simplified because it made the code simpler. If we're worried about compile time performance we can improve this. I know we're talking about making a rotate intrinsic, but hopefully we can go ahead and do this change and just make sure the rotate intrinsic also handles it. Differential Revision: https://reviews.llvm.org/D47116 llvm-svn: 332895
* [X86] Simplify some X86 address mode folding code, NFCIReid Kleckner2018-05-211-83/+52
| | | | | | | | This code should really do exactly the same thing for 32-bit x86 and 64-bit small code models, with the exception that RIP-relative addressing can't use base and index registers. llvm-svn: 332893
* [X86] Remove masking from vpternlog intrinsics. Use a select in IR instead.Craig Topper2018-05-213-42/+37
| | | | | | | | This removes 6 intrinsics since we no longer need separate mask and maskz intrinsics. Differential Revision: https://reviews.llvm.org/D47124 llvm-svn: 332890
* Fix a make_unique ambiguity.Peter Collingbourne2018-05-211-1/+1
| | | | llvm-svn: 332889
* [InstCombine] remove fptrunc (select) code; NFCISanjay Patel2018-05-211-17/+0
| | | | | | | This pattern is handled within commonCastTransforms(), so the code here is dead AFAICT. llvm-svn: 332887
* LTO: Replace split dwarf implementation that uses objcopy with one that uses ↵Peter Collingbourne2018-05-211-61/+17
| | | | | | | | | | direct emission. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47091 llvm-svn: 332884
* CodeGen: Add a dwo output file argument to addPassesToEmitFile and hook it ↵Peter Collingbourne2018-05-215-10/+16
| | | | | | | | | | up to dwo output. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47089 llvm-svn: 332881
* MC: Introduce an ELF dwo object writer and teach llvm-mc about it.Peter Collingbourne2018-05-212-15/+103
| | | | | | | | Part of PR37466. Differential Revision: https://reviews.llvm.org/D47051 llvm-svn: 332875
* [DebugInfo] Use absolute addresses in location listsJonas Devlieghere2018-05-213-11/+24
| | | | | | | | | | | Rather than relying on the user to do the address calculating in DW_AT_location we should just dump the absolute address. rdar://problem/38513870 Differential revision: https://reviews.llvm.org/D47152 llvm-svn: 332873
* MC: Extract a derived class from ELFObjectWriter. NFCI.Peter Collingbourne2018-05-211-13/+19
| | | | | | | | | | This class will be used to create regular, non-split ELF files. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47049 llvm-svn: 332870
* MC: Separate creating a generic object writer from creating a target object ↵Peter Collingbourne2018-05-2159-305/+254
| | | | | | | | | | | | | writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
* MC: Extract ELFObjectWriter's ELF writing functionality into an ELFWriter ↵Peter Collingbourne2018-05-211-350/+368
| | | | | | | | | | | class. NFCI. The idea is that we will be able to use this class to create multiple files. Differential Revision: https://reviews.llvm.org/D47048 llvm-svn: 332867
* Fix ubsan bounds check failure.Peter Collingbourne2018-05-211-1/+2
| | | | llvm-svn: 332866
* [EarlyCSE] Improve EarlyCSE of some absolute value cases.Craig Topper2018-05-212-4/+14
| | | | | | | | | | Change matchSelectPattern to return X and -X for ABS/NABS in a well defined order. Adjust EarlyCSE to account for this. Ensure the SPF result is some kind of min/max and not abs/nabs in one place in InstCombine that made me nervous. Prevously we returned the two operands of the compare part of the abs pattern. The RHS is always going to be a 0i, 1 or -1 constant. This isn't a very meaningful thing to return for any one. There's also some freedom in the abs pattern as to what happens when the value is equal to 0. This freedom led to early cse failing to match when different constants were used in otherwise equivalent operations. By returning the input and its negation in a defined order we can ensure an exact match. This also makes sure both patterns use the exact same subtract instruction for the negation. I believe CSE should evebntually make this happen and properly merge the nsw/nuw flags. But I'm not familiar with CSE and what order it does things in so it seemed like it might be good to really enforce that they were the same. Differential Revision: https://reviews.llvm.org/D47037 llvm-svn: 332865
* MC: Remove stream and output functions from MCObjectWriter. NFCI.Peter Collingbourne2018-05-213-5/+3
| | | | | | | | Part of PR37466. Differential Revision: https://reviews.llvm.org/D47043 llvm-svn: 332864
* MC: Have the object writers return the number of bytes written. NFCI.Peter Collingbourne2018-05-215-17/+27
| | | | | | | | | | This removes the last external use of the stream. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47042 llvm-svn: 332863
* [AMDGPU] Add divergence analysis as a dependency for ISelStanislav Mekhanoshin2018-05-211-0/+1
| | | | | | | | | | AMDGPUDAGToDAGISel adds DivergenceAnalysis in getAnalysisUsage but does not list it in pass dependencies which may lead to crash. Differential Revision: https://reviews.llvm.org/D47151 llvm-svn: 332862
* MC: Change object writers to use endian::Writer. NFCI.Peter Collingbourne2018-05-215-355/+364
| | | | | | | | Part of PR37466. Differential Revision: https://reviews.llvm.org/D47040 llvm-svn: 332861
* [VPlan] Reland r332654 and silence unused func warningDiego Caballero2018-05-219-42/+839
| | | | | | | | | | r332654 was reverted due to an unused function warning in release build. This commit includes the same code with the warning silenced. Differential Revision: https://reviews.llvm.org/D44338 llvm-svn: 332860
* MC: Change MCAssembler::writeSectionData and writeFragmentPadding to take a ↵Peter Collingbourne2018-05-216-65/+50
| | | | | | | | | | | | | | raw_ostream. NFCI. Also clean up a couple of hacks where we were writing the section contents to another stream by setting the object writer's stream, writing and setting it back. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47038 llvm-svn: 332858
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an ↵Peter Collingbourne2018-05-2124-182/+164
| | | | | | | | | | | | | MCObjectWriter. NFCI. To make this work I needed to add an endianness field to MCAsmBackend so that writeNopData() implementations know which endianness to use. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47035 llvm-svn: 332857
* AMDGPU/GlobalISel: Address post-commit review comments for r332379Tom Stellard2018-05-211-1/+1
| | | | | | MCRegisterInfo::getPhysRegSize() will be deprecated. llvm-svn: 332856
* [InstCombine] Fix PR37526: MinMax patterns produce an infinite loop.Alexey Bataev2018-05-211-3/+8
| | | | | | | | | | | | | | | | | Summary: This patch fixes PR37526 by simplifying the newly generated LoadInst instructions. If the pointer address is a bitcast from the pointer to the NewType, we can just remove this extra bitcast instead of creating the new one. This fixes the PR37526 + may speed up the whole compilation process. Reviewers: spatel, RKSimon, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47144 llvm-svn: 332855
* [X86][BtVer2] Add a 'J' prefix to the PRF/RCU defs. NFCAndrea Di Biagio2018-05-211-3/+3
| | | | | | | This is to keep the Jaguar model's naming convention. Processor resources all have a 'J' prefix in the BtVer2 scheduling model. llvm-svn: 332851
* [LLVM-C] Add DIBuilder Bindings For ObjC ClassesRobert Widmann2018-05-211-0/+38
| | | | | | | | | | | | | | Summary: Add LLVMDIBuilderCreateObjCIVar, LLVMDIBuilderCreateObjCProperty, and LLVMDIBuilderCreateInheritance to allow declaring metadata for Objective-C class hierarchies and their associated properties and instance variables. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: harlanhaskins, llvm-commits Differential Revision: https://reviews.llvm.org/D47123 llvm-svn: 332850
* [X86] - Avoid SFB pass - fix bug in updating the offsets for newly created ↵Lama Saba2018-05-211-2/+2
| | | | | | | copies Change-Id: I169ab6fe7e187727c0298c2a1e2868a683f3e688 llvm-svn: 332849
* [DWARF] Refactor callback usage for .debug_line error handlingJames Henderson2018-05-212-24/+26
| | | | | | | | | | | Change the "recoverable" error callback to take an Error instaed of a string. Reviewed by: JDevlieghere Differential Revision: https://reviews.llvm.org/D46831 llvm-svn: 332845
* [X86][SSE] Add an assert to ensure that rotation amount is converted to a scaleSimon Pilgrim2018-05-211-0/+1
| | | | | | Missed in rL332832 where we added SSE v4i32 rotations for PR37426. llvm-svn: 332844
* ARM: be conservative when asked load/store alignment of weird type.Tim Northover2018-05-211-0/+4
| | | | | | | Chances are we'll be asked again after type legalization, but before that point it's better to claim misaligned accesses aren't allowed than to assert. llvm-svn: 332840
* revert r332610, it breaks cfi, see D46326Nico Weber2018-05-212-82/+40
| | | | llvm-svn: 332838
* [mips] Revert Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-215-332/+327
| | | | | | | | Revert this patch due buildbot failure. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332837
* [CVP] Require DomTree for new Pass ManagerDavid Green2018-05-211-9/+13
| | | | | | | | | We were previously using a DT in CVP through SimplifyQuery, but not requiring it in the new pass manager. Hence it would crash if DT was not already available. This now gets DT directly and plumbs it through to where it is used (instead of using it through SQ). llvm-svn: 332836
* Fix up a few grammar issues.Eric Christopher2018-05-212-2/+2
| | | | llvm-svn: 332835
* [mips] Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-215-327/+332
| | | | | | | | | | | | | | MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332834
* [X86][SSE] Support v4i32 rotations (PR37426)Simon Pilgrim2018-05-211-50/+119
| | | | | | | | | | As suggested by Fabian on PR37426, we can use PMULUDQ to perform v4i32 vector rotations as the upper 32bits of the multiply will contain the 'wrapped' bits of the rotation. v8i16/v16i8 rotations would be straightforward to add to lowerRotate in the future - ideally we'd mostly share code with the vector shifts lowering. Differential Revision: https://reviews.llvm.org/D46954 llvm-svn: 332832
* [LLVM-C] Improve Bindings For AliasesRobert Widmann2018-05-201-0/+45
| | | | | | | | | | | | | | Summary: Add wrappers for a module's alias iterators and a getter and setter for the aliasee value. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: llvm-commits, harlanhaskins Differential Revision: https://reviews.llvm.org/D46808 llvm-svn: 332826
* [X86] Remove mask arguments from permvar builtins/intrinsics. Use a select ↵Craig Topper2018-05-204-67/+65
| | | | | | | | in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
* Revert 332750, llvm part (see comment on D46910).Nico Weber2018-05-202-2/+2
| | | | llvm-svn: 332823
* [mips] Add microMIPSR6 ll/sc instructions.Simon Dardis2018-05-206-15/+64
| | | | | | | | | | Previously the compiler was using the microMIPSR3 variants, incorrectly. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46948 llvm-svn: 332820
* [InstCombine] choose 1 form of abs and nabs as canonicalSanjay Patel2018-05-201-0/+51
| | | | | | | | | | | | | | | We already do this for min/max (see the blob above the diff), so we should do the same for abs/nabs. A sign-bit check (<s 0) is used as a predicate for other IR transforms and it's likely the best for codegen. This might solve the motivating cases for D47037 and D47041, but I think those patches still make sense. We can't guarantee this canonicalization if the icmp has more than one use. Differential Revision: https://reviews.llvm.org/D47076 llvm-svn: 332819
* [GlobalMerge] Exit early if only one global is to be mergedHaicheng Wu2018-05-191-1/+9
| | | | | | | | To save some compilation time and prevent some unnecessary changes. Differential Revision: https://reviews.llvm.org/D46640 llvm-svn: 332813
* Re-revert "[Option] Fix PR37006 prefix choice in findNearest"Brian Gesiak2018-05-191-24/+24
| | | | | | | | Summary: Reverting due to a test failure in an llvm-mt test on some buildbots, namely http://green.lab.llvm.org/green/job/clang-stage2-configure-Rlto/26020/. llvm-svn: 332812
* [LLVM-C] Use Length-Providing Value Name Getters and SettersRobert Widmann2018-05-191-0/+10
| | | | | | | | | | | | | | | | Summary: - Provide LLVMGetValueName2 and LLVMSetValueName2 that return and take the length of the provided C string respectively - Deprecate LLVMGetValueName and LLVMSetValueName Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: llvm-commits, harlanhaskins Differential Revision: https://reviews.llvm.org/D46890 llvm-svn: 332810
* [IRCE] Fix miscompile with range checks against negative valuesMax Kazantsev2018-05-191-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the patch rL329547, we have lifted the over-restrictive limitation on collected range checks, allowing to work with range checks with the end of their range not being provably non-negative. However it appeared that the non-negativity of this value was assumed in the utility function `ClampedSubtract`. In particular, its reasoning is based on the fact that `0 <= SINT_MAX - X`, which is not true if `X` is negative. The function `ClampedSubtract` is only called twice, once with `X = 0` (which is OK) and the second time with `X = IRC.getEnd()`, where we may now see the problem if the end is actually a negative value. In this case, we may sometimes miscompile. This patch is the conservative fix of the miscompile problem. Rather than rejecting non-provably non-negative `getEnd()` values, we will check it for non-negativity in runtime. For this, we use function `smax(smin(X, 0), -1) + 1` that is equal to `1` if `X` is non-negative and is equal to 0 if `X` is negative. If we multiply `Begin, End` of safe iteration space by this function calculated for `X = IRC.getEnd()`, we will get the original `[Begin, End)` if `IRC.getEnd()` was non-negative (and, thus, `ClampedSubtract` worked correctly) and the empty range `[0, 0)` in case if ` IRC.getEnd()` was negative. So we in fact prohibit execution of the main loop if at least one of range checks was made against a negative value (and we figured it out in runtime). It is still better than what we have before (non-negativity had to be proved in compile time) and prevents us from miscompile, however it is sometiles too restrictive for unsigned range checks against a negative value (which in fact can be eliminated). Once we re-implement `ClampedSubtract` in a way that it handles negative `X` correctly, this limitation can be lifted, too. Differential Revision: https://reviews.llvm.org/D46860 Reviewed By: samparker llvm-svn: 332809
* [MergeICmps] Don't crash when memcmp is not availableBenjamin Kramer2018-05-191-0/+4
| | | | | | Fixes clang crashing with -fno-builtin, PR37527. llvm-svn: 332808
* Fix MSVC unused variable warning. NFCI.Simon Pilgrim2018-05-191-5/+4
| | | | | | AMDGPURegisterInfo::getSubRegFromChannel is a static method - we don't need to get the AMDGPURegisterInfo instance. llvm-svn: 332807
* Un-revert "[Option] Fix PR37006 prefix choice in findNearest"Brian Gesiak2018-05-191-24/+24
| | | | | | | | | | | | | Summary: In https://reviews.llvm.org/rL332804 I loosed the assertion in the Clang driver test that forced me to revert https://reviews.llvm.org/rL332299. Once this lands I should be able to narrow down what caused PS4 buildbots to fail, and reinstate the check in that test. Test Plan: check-llvm & check-clang llvm-svn: 332805
* Fix evaluator for non-zero alloca addr spaceYaxun Liu2018-05-191-1/+2
| | | | | | | | | | | | | | The evaluator goes through BB and creates global vars as temporary values to evaluate results of LLVM instructions. It creates undef for alloca, however it assumes alloca in addr space 0. If the next instruction is addrspace cast to 0, then we get an invalid cast instruction. This patch let the temp global var have an address space matching alloca addr space, so that the valuation can be done. Differential Revision: https://reviews.llvm.org/D47081 llvm-svn: 332794
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