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* [SelectionDAG] Check membership of register in class for singleNirav Dave2019-01-151-6/+1
| | | | | | | | | register constraints. NFCI. Now that X86's ST(7) constraints are fixed this check can be reinstated. llvm-svn: 351207
* [X86] Fix register class for assembly constraints to ST(7). NFCI.Nirav Dave2019-01-152-4/+13
| | | | | | | | Modify getRegForInlineAsmConstraint to return special singleton register class when a constraint references ST(7) not RFP80 for which ST(7) is not a member. llvm-svn: 351206
* [X86] Bailout of lowerVectorShuffleAsPermuteAndUnpack for shuffle-with-zero ↵Simon Pilgrim2019-01-151-5/+4
| | | | | | | | | | (PR40306) If we're shuffling with a zero vector, then we are better off not doing VECTOR_SHUFFLE(UNPCK()) as we lose track of those zero elements. We were already doing this for SSSE3 targets as we have PSHUFB, but its worth doing for all targets. llvm-svn: 351203
* [DAGCombiner] reduce buildvec of zexted extracted element to shuffleSanjay Patel2019-01-151-0/+75
| | | | | | | | | | | | | | | The motivating case for this is shown in the first regression test. We are transferring to scalar and back rather than just zero-extending with 'vpmovzxdq'. That's a special-case for a more general pattern as shown here. In all tests, we're avoiding the vector-scalar-vector moves in favor of vector ops. We aren't producing optimal shuffle code in some cases though, so the patch is limited to reduce regressions. Differential Revision: https://reviews.llvm.org/D56281 llvm-svn: 351198
* Revert r351138 "[ORC] Move ORC Core symbol map and set types into their ownLang Hames2019-01-153-256/+233
| | | | | | | | header: CoreTypes.h." This commit broke some bots. Reverting while I investigate. llvm-svn: 351195
* [SimpleLoopUnswitch] Increment stats counter for unswitching switch instructionZaara Syeda2019-01-151-1/+4
| | | | | | | | | | | Increment statistics counter NumSwitches at unswitchNontrivialInvariants() for unswitching a non-trivial switch instruction. This is to fix a bug that it increments NumBranches even for the case of switch instruction. There is no functional change in this patch. Differential Revision: https://reviews.llvm.org/D56408 llvm-svn: 351193
* [InstCombine] Don't undo 0 - (X * Y) canonicalization when combining subs.Florian Hahn2019-01-151-4/+3
| | | | | | | | | Otherwise instcombine gets stuck in a cycle. The canonicalization was added in D55961. This patch fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=12400 llvm-svn: 351187
* [NFC] Remove some code duplicationMax Kazantsev2019-01-151-26/+9
| | | | llvm-svn: 351185
* [NFC] Remove obsolete enum RangeCheckKindMax Kazantsev2019-01-151-59/+16
| | | | llvm-svn: 351183
* [NFC] Decrease if nestMax Kazantsev2019-01-151-18/+14
| | | | llvm-svn: 351180
* [NFC] Move some functions to LoopUtilsMax Kazantsev2019-01-152-42/+42
| | | | llvm-svn: 351179
* [WebAssembly] Support multilibs for wasm32 and add a wasm OS that uses itDan Gohman2019-01-151-0/+2
| | | | | | | | | | | | This adds support for multilib paths for wasm32 targets, following [Debian's Multiarch conventions], and also adds an experimental OS name in order to test it. [Debian's Multiarch conventions]: https://wiki.debian.org/Multiarch/ Differential Revision: https://reviews.llvm.org/D56553 llvm-svn: 351163
* [WebAssembly] Expand SIMD shifts while V8's implementation disagreesThomas Lively2019-01-151-1/+31
| | | | | | | | | | | | | | | | Summary: V8 currently implements SIMD shifts as taking an immediate operation, which disagrees with the spec proposal and the toolchain implementation. As a stopgap measure to get things working, unroll all vector shifts. Since this is a temporary measure, there are no tests. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, dmgreen, llvm-commits Differential Revision: https://reviews.llvm.org/D56520 llvm-svn: 351151
* AMDGPU: Add a fast path for icmp.i1(src, false, NE)Marek Olsak2019-01-153-0/+15
| | | | | | | | | | | | | | | | | Summary: This allows moving the condition from the intrinsic to the standard ICmp opcode, so that LLVM can do simplifications on it. The icmp.i1 intrinsic is an identity for retrieving the SGPR mask. And we can also get the mask from and i1, or i1, xor i1. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52060 llvm-svn: 351150
* [AArch64] Adjust the feature set for ExynosEvandro Menezes2019-01-151-0/+1
| | | | | | Enable the fusion of arithmetic and logic instructions for Exynos M4. llvm-svn: 351149
* [X86] Avoid clobbering ESP/RSP in the epilogue.Reid Kleckner2019-01-151-1/+2
| | | | | | | | | | | | | | | | | Summary: In r345197 ESP and RSP were added to GR32_TC/GR64_TC, allowing them to be used for tail calls, but this also caused `findDeadCallerSavedReg` to think they were acceptable targets for clobbering. Filter them out. Fixes PR40289. Patch by Geoffry Song! Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D56617 llvm-svn: 351146
* [EarlyIfConversion] Don't if-convert unconditional branches.Eli Friedman2019-01-151-0/+7
| | | | | | | | | | | | | A block ending in an unconditional branch can have two successors if one is a landing pad. In practice, I think this only has an effect on Windows because landing pads are never empty for Itanium unwinding. (Alternatively, I could add a check to AArch64InstrInfo::canInsertSelect, but this seems more obvious.) Differential Revision: https://reviews.llvm.org/D56468 llvm-svn: 351142
* [AArch64] Explicitly use v1i64 type for llvm.aarch64.neon.abs.i64 .Eli Friedman2019-01-151-3/+13
| | | | | | | | | | | | | | Otherwise, with D56544, the intrinsic will be expanded to an integer csel, which is probably not what the user expected. This matches the general convention of using "v1" types to represent scalar integer operations in vector registers. While I'm here, also add some error checking so we don't generate illegal ABS nodes. Differential Revision: https://reviews.llvm.org/D56616 llvm-svn: 351141
* [AArch64] Add new target feature to fuse arithmetic and logic operationsEvandro Menezes2019-01-143-7/+116
| | | | | | | | | This feature enables the fusion of some arithmetic and logic instructions together. Differential revision: https://reviews.llvm.org/D56572 llvm-svn: 351139
* [ORC] Move ORC Core symbol map and set types into their own header: CoreTypes.h.Lang Hames2019-01-143-233/+256
| | | | | | | This will allow other utilities (including a future RuntimeDyld replacement) to use these types without pulling in the major Core types (JITDylib, etc.). llvm-svn: 351138
* [X86] Fix unused variable warning in Release builds. NFC.Benjamin Kramer2019-01-141-2/+2
| | | | llvm-svn: 351136
* Revert "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors"Nikita Popov2019-01-143-35/+4
| | | | | | | | | This reverts commit r351125. I missed test changes in an SLPVectorizer test, due to the cost model changes. Reverting for now. llvm-svn: 351129
* [Object] Return a symbol_iterator, rather than a basic_symbol_iterator, fromLang Hames2019-01-141-1/+1
| | | | | | | | | | | | | | MachOObjectFile::getSymbolByIndex. ObjectFile derivatives should prefer symbol_iterator/SymbolRef over basic_symbol_iterator/BasicSymbolRef where possible, as the former retain their link to the ObjectFile (rather than a SymbolicFile) and provide more functionality. No test for this: Existing code is working, and we don't have (m)any libObject unit tests. I'll think about how we can test more systematically going forward. llvm-svn: 351128
* [WebAssembly][FastISel] Do not assume naive CmpInst loweringThomas Lively2019-01-141-7/+5
| | | | | | | | | | | | | | Summary: Fixes https://bugs.llvm.org/show_bug.cgi?id=40172. See test/CodeGen/WebAssembly/PR40172.ll for an explanation. Reviewers: dschuff, aheejin Subscribers: nikic, llvm-commits, sunfish, jgravelle-google, sbc100 Differential Revision: https://reviews.llvm.org/D56457 llvm-svn: 351127
* [CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectorsNikita Popov2019-01-143-4/+35
| | | | | | | | | | | Related to https://bugs.llvm.org/show_bug.cgi?id=40123. Rather than scalarizing, expand a vector USUBSAT into UMAX+SUB, which produces much better code for X86. Differential Revision: https://reviews.llvm.org/D56636 llvm-svn: 351125
* [opaque pointer types] Update GetElementPtr creation APIs toJames Y Knight2019-01-141-7/+41
| | | | | | | | | | consistently accept a pointee-type argument. Note: this also adds a new C API and soft-deprecates the old C API. Differential Revision: https://reviews.llvm.org/D56559 llvm-svn: 351124
* [opaque pointer types] Update LoadInst creation APIs to consistentlyJames Y Knight2019-01-142-57/+24
| | | | | | | | | | accept a return-type argument. Note: this also adds a new C API and soft-deprecates the old C API. Differential Revision: https://reviews.llvm.org/D56558 llvm-svn: 351123
* [opaque pointer types] Update InvokeInst creation APIs to consistentlyJames Y Knight2019-01-141-3/+16
| | | | | | | | | | accept a callee-type argument. Note: this also adds a new C API and soft-deprecates the old C API. Differential Revision: https://reviews.llvm.org/D56557 llvm-svn: 351122
* [opaque pointer types] Update CallInst creation APIs to consistentlyJames Y Knight2019-01-142-20/+30
| | | | | | | | | | accept a callee-type argument. Note: this also adds a new C API and soft-deprecates the old C API. Differential Revision: https://reviews.llvm.org/D56556 llvm-svn: 351121
* [SanitizerCoverage][NFC] Use appendToUsed instead of includeJonathan Metzman2019-01-141-16/+7
| | | | | | | | | | | | | | | | | | | Summary: Use appendToUsed instead of include to ensure that SanitizerCoverage's constructors are not stripped. Also, use isOSBinFormatCOFF() to determine if target binary format is COFF. Reviewers: pcc Reviewed By: pcc Subscribers: hiraditya Differential Revision: https://reviews.llvm.org/D56369 llvm-svn: 351118
* [X86] Silence a -Wparentheses warning on gcc. NFCCraig Topper2019-01-141-1/+1
| | | | llvm-svn: 351111
* [X86][SSSE3] Bailout of lowerVectorShuffleAsPermuteAndUnpack for ↵Simon Pilgrim2019-01-141-8/+14
| | | | | | | | shuffle-with-zero (PR40306) If we have PSHUFB and we're shuffling with a zero vector, then we are better off not doing VECTOR_SHUFFLE(UNPCK()) as we lose track of those zero elements. llvm-svn: 351103
* Ignore PhiNodes when mapping sample profile dataDavid Callahan2019-01-141-3/+3
| | | | | | | | | | | | | | Summary: Like branch instructions, phi nodes frequently do not have debug information related to the block they are in and so they should be ignored. Reviewers: danielcdh, twoh, Kader, wmi Reviewed By: wmi Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D55094 llvm-svn: 351102
* Revert "Merge branch 'arcpatch-D55094'"David Callahan2019-01-141-3/+3
| | | | | | | | | This reverts commit a9788dd6587d67c856df74eedff5a6ad34ce8320, reversing changes made to f1309ffebf718d16aec4fab83380556c660e2825. unintended merge pushed llvm-svn: 351095
* [x86] lower extracted add/sub to horizontal vector mathSanjay Patel2019-01-141-19/+55
| | | | | | | | | | | | | | add (extractelt (X, 0), extractelt (X, 1)) --> extractelt (hadd X, X), 0 This is the integer sibling to D56011. There's an additional restriction to only to do this transform in the case where we don't have extra extracts from the source vector. Without that, we can fail to match larger horizontal patterns that are more beneficial than this minimal case. An improvement to the more general h-op lowering may allow us to remove the restriction here in a follow-up. llvm-svn: 351093
* Merge branch 'arcpatch-D55094'David Callahan2019-01-141-3/+3
| | | | llvm-svn: 351092
* Revert "[VFS] Allow multiple RealFileSystem instances with independent CWDs."Amara Emerson2019-01-141-73/+30
| | | | | | This reverts commit r351079, r351069 and r351050 as it broken the greendragon bots on macOS. llvm-svn: 351091
* cmake: Don't install plugins used for examples or testsTom Stellard2019-01-141-1/+1
| | | | | | | | | | | | | | | | Summary: This patch drops install targets for LLVMHello.so, TestPlugin.so, and BugpointPasses.so. Reviewers: chandlerc, beanz, thakis, philip.pfaffe Reviewed By: chandlerc Subscribers: SquallATF, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D55965 llvm-svn: 351087
* [WebAssembly] Remove old intrinsicsDan Gohman2019-01-141-29/+0
| | | | | | | | | This removes the old grow_memory and mem.grow-style intrinsics, leaving just the memory.grow-style intrinsics. Differential Revision: https://reviews.llvm.org/D56645 llvm-svn: 351084
* Reapply r345008 "Split MachinePipeliner code into header and cpp files"Adrian Prantl2019-01-141-595/+18
| | | | | | | | | | | | | | Split MachinePipeliner code into header and cpp files to allow inheritance from SwingSchedulerDAG. This reapplies https://reviews.llvm.org/D56084 after moving the implementation of the dump functions into the .cpp files. This fixes a linker error when building with Clang modules enables and local submodule visibility disabled. Original patch by Lama Saba <lama.saba@intel.com>! llvm-svn: 351077
* Remove NameLen argument from newly-introduced IR C APIs.James Y Knight2019-01-141-6/+5
| | | | | | | | | | | | | | | | | | | | | Normally, changing the function signatures of C APIs is disallowed, but as these two are brand new last week, and haven't been released yet, it is okay in this instance. As per discussion in D56556, we will not add NameLen arguments to IR building APIs, for the following reasons: 1. We do not want to deprecate all of the IR building APIs, just to add a NameLen argument to each one. 2. Consistency is important, so adding it just to new ones is unfortunate. 3. The IR names are completely optional, useful for readability of IR only. There is no value in ever supporting nul bytes. Differential Revision: https://reviews.llvm.org/D56669 llvm-svn: 351076
* Reland "Refactor GetRegistersForValue. NFCI."Nirav Dave2019-01-141-55/+44
| | | | | | Remove over-strictification class membership check. llvm-svn: 351074
* [DAGCombiner] Add (sub_sat x, x) -> 0 combineSimon Pilgrim2019-01-141-0/+4
| | | | llvm-svn: 351073
* [DAGCombiner] Enable sub saturation constant foldingSimon Pilgrim2019-01-142-1/+8
| | | | llvm-svn: 351072
* [DAGCombiner] Add add/sub saturation undef handlingSimon Pilgrim2019-01-142-0/+14
| | | | | | | | Match ConstantFolding.cpp: (add_sat x, undef) -> -1 (sub_sat x, undef) -> 0 llvm-svn: 351070
* [VFS] Fix unused variable warning. NFCSam McCall2019-01-141-1/+1
| | | | llvm-svn: 351069
* [DAGCombiner] Enable add saturation constant foldingSimon Pilgrim2019-01-142-2/+5
| | | | llvm-svn: 351060
* [mips] Optimize shifts for types larger than GPR size (mips2/mips3)Aleksandar Beserminji2019-01-144-0/+118
| | | | | | | | | | | | | With this patch, shifts are lowered to optimal number of instructions necessary to shift types larger than the general purpose register size. This resolves PR/32293. Thanks to Kyle Butt for reporting the issue! Differential Revision: https://reviews.llvm.org/D56320 llvm-svn: 351059
* [DebugInfo] Remove un-necessary logic from HoistThenElseCodeToIfJeremy Morse2019-01-141-12/+1
| | | | | | | | | | | | | | | | | Following PR39807, the way in which SimplifyCFG hoists common code on branch paths was fixed in r347782. However this left extra code hanging around HoistThenElseCodeToIf that wasn't necessary and needlessly complicated matters -- we no longer need to look up through the 'if' basic block to find a location for hoisted 'select' insts, we can instead use the location chosen by applyMergedLocation. This patch deletes that extra logic, and updates a regression test to reflect the new logic (selects get the merged location, not a previous insts location). Differential Revision: https://reviews.llvm.org/D55272 llvm-svn: 351058
* [DAGCombiner] Add add saturation constant folding tests.Simon Pilgrim2019-01-141-2/+3
| | | | | | Exposes an issue with sadd_sat for computeOverflowKind, so I've disabled it for now. llvm-svn: 351057
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