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* Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.Patrik Hagglund2012-12-112-2/+2
| | | | llvm-svn: 169840
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-111-1/+1
| | | | llvm-svn: 169839
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-114-12/+12
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 169838
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-1110-73/+68
| | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. llvm-svn: 169837
* [CMake] Remove dependencies to intrinsics_gen I introduced in r169724.NAKAMURA Takumi2012-12-113-3/+3
| | | | llvm-svn: 169819
* Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma2012-12-111-148/+46
| | | | llvm-svn: 169814
* Fix PR14565. Don't if-convert loops that have switch statements in them.Nadav Rotem2012-12-111-0/+4
| | | | llvm-svn: 169813
* Stylistic tweak.Evan Cheng2012-12-111-9/+8
| | | | llvm-svn: 169811
* Fix a miscompile in the DAG combiner. Previously, we would incorrectlyChandler Carruth2012-12-111-2/+6
| | | | | | | | | | | | | | | | | | | | | | | try to reduce the width of this load, and would end up transforming: (truncate (lshr (sextload i48 <ptr> as i64), 32) to i32) to (truncate (zextload i32 <ptr+4> as i64) to i32) We lost the sext attached to the load while building the narrower i32 load, and replaced it with a zext because lshr always zext's the results. Instead, bail out of this combine when there is a conflict between a sextload and a zext narrowing. The rest of the DAG combiner still optimize the code down to the proper single instruction: movswl 6(...),%eax Which is exactly what we wanted. Previously we read past the end *and* missed the sign extension: movl 6(...), %eax llvm-svn: 169802
* Fall back to the selection dag isel to select tail calls.Chad Rosier2012-12-114-10/+14
| | | | | | | | | | | | | | | | | | | This shouldn't affect codegen for -O0 compiles as tail call markers are not emitted in unoptimized compiles. Testing with the external/internal nightly test suite reveals no change in compile time performance. Testing with -O1, -O2 and -O3 with fast-isel enabled did not cause any compile-time or execution-time failures. All tests were performed on my x86 machine. I'll monitor our arm testers to ensure no regressions occur there. In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While it's theoretically true that this is just an optimization, it's an optimization that we very much want to happen even at -O0, or else ARC applications become substantially harder to debug. Part of rdar://12553082 llvm-svn: 169796
* Refactor out the abbreviation handling into a separate class thatEric Christopher2012-12-102-24/+57
| | | | | | | | | | | | controls each of the abbreviation sets (only a single one at the moment) and computes offsets separately as well for each set of DIEs. No real function change, ordering of abbreviations for the skeleton CU changed but only because we're computing in a separate order. Fix the testcase not to care. llvm-svn: 169793
* Some enhancements for memcpy / memset inline expansion.Evan Cheng2012-12-108-41/+139
| | | | | | | | | | | | | | | | | | | | | 1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 llvm-svn: 169791
* Optimistically analyse Phi cyclesArnold Schwaighofer2012-12-101-41/+13
| | | | | | | | | | Analyse Phis under the starting assumption that they are NoAlias. Recursively look at their inputs. If they MayAlias/MustAlias there must be an input that makes them so. Addresses bug 14351. llvm-svn: 169788
* Defer call to InitSections until after MCContext has been initialized. IfLang Hames2012-12-103-2/+5
| | | | | | | | InitSections is called before the MCContext is initialized it could cause duplicate temporary symbols to be emitted later (after context initialization resets the temporary label counter). llvm-svn: 169785
* Rearrange vars and make comments more obvious.Eric Christopher2012-12-101-3/+5
| | | | llvm-svn: 169780
* Remove blank line at top of file.Eric Christopher2012-12-101-1/+0
| | | | llvm-svn: 169779
* Fix a coding style nit.Eric Christopher2012-12-101-2/+2
| | | | llvm-svn: 169776
* Enable the loop vectorizer only on O2 and above. (Still disabled by default)Nadav Rotem2012-12-101-1/+1
| | | | llvm-svn: 169774
* LegalizeDAG: Allow type promotion of scalar loadsTom Stellard2012-12-101-3/+2
| | | | llvm-svn: 169773
* LegalizeDAG: Allow type promotion for scalar storesTom Stellard2012-12-101-3/+4
| | | | llvm-svn: 169772
* Split the LoopVectorizer into H and CPP.Nadav Rotem2012-12-102-951/+993
| | | | llvm-svn: 169771
* Cleanup formatting, comments and naming.Eli Bendersky2012-12-101-21/+21
| | | | llvm-svn: 169762
* [mips] Set HWEncoding field of registers. Use delete functionAkira Hatanaka2012-12-105-130/+30
| | | | | | getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. llvm-svn: 169760
* Use the somewhat semantic term "split dwarf" it more matches what'sEric Christopher2012-12-102-30/+32
| | | | | | going on and makes a lot of the terminology in comments make more sense. llvm-svn: 169758
* Delete the FissionCU.Eric Christopher2012-12-101-0/+3
| | | | llvm-svn: 169757
* Reorder fission variables.Eric Christopher2012-12-102-5/+11
| | | | llvm-svn: 169756
* Don't use a red zone for code coverage if the user specified `-mno-red-zone'.Bill Wendling2012-12-101-4/+17
| | | | | | | | | The `-mno-red-zone' flag wasn't being propagated to the functions that code coverage generates. This allowed some of them to use the red zone when that wasn't allowed. <rdar://problem/12843084> llvm-svn: 169754
* Add support for reverse induction variables. For example:Nadav Rotem2012-12-101-90/+191
| | | | | | | while (i--) sum+=A[i]; llvm-svn: 169752
* This patch adds statistics for other non-DWARF fragments emitted byEli Bendersky2012-12-101-2/+13
| | | | | | | | | the assembler. This is useful in order to know how the numbers add up, since in particular the Align fragments account for a non-trivial portion of the emitted fragments (especially on -O0 which sets relax-all). llvm-svn: 169747
* Use GetUnderlyingObjects in mischedHal Finkel2012-12-101-92/+143
| | | | | | | | | | | | | | | | misched used GetUnderlyingObject in order to break false load/store dependencies, and the -enable-aa-sched-mi feature similarly relied on GetUnderlyingObject in order to ensure it is safe to use the aliasing analysis. Unfortunately, GetUnderlyingObject does not recurse through phi nodes, and so (especially due to LSR) all of these mechanisms failed for induction-variable-dependent loads and stores inside loops. This change replaces uses of GetUnderlyingObject with GetUnderlyingObjects (which will recurse through phi and select instructions) in misched. Andy reviewed, tested and simplified this patch; Thanks! llvm-svn: 169744
* Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."Chandler Carruth2012-12-101-2/+1
| | | | | | Accidental commit... git svn betrayed me. Sorry for the noise. llvm-svn: 169741
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-101-1/+2
| | | | | | | | | | | | | | | | | | | Summary: Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D195 llvm-svn: 169740
* Fix a typo in my previous commit -- bloomfield is 0x1A not 0x2A.Chandler Carruth2012-12-101-1/+1
| | | | | | | Thanks to the PaX folks for noticing in review! We need some tests here, any sugestions welcome... llvm-svn: 169739
* Address a FIXME and update the fast unaligned memory feature for newerChandler Carruth2012-12-102-13/+21
| | | | | | | | | | | | | | | Intel chips. The model number rules were determined by inspecting Intel's documentation for their newer chip model numbers. My understanding is that all of the newer Intel chips have fast unaligned memory access, but if anyone is concerned about a particular chip, just shout. No tests updated; it's not clear we have dedicated tests for the chips' various features, but if anyone would like tests (or can point me at some existing ones), I'm happy to oblige. llvm-svn: 169730
* Add a new visitor for walking the uses of a pointer value.Chandler Carruth2012-12-103-219/+218
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This visitor provides infrastructure for recursively traversing the use-graph of a pointer-producing instruction like an alloca or a malloc. It maintains a worklist of uses to visit, so it can handle very deep recursions. It automatically looks through instructions which simply translate one pointer to another (bitcasts and GEPs). It tracks the offset relative to the original pointer as long as that offset remains constant and exposes it during the visit as an APInt offset. Finally, it performs conservative escape analysis. However, currently it has some limitations that should be addressed going forward: 1) It doesn't handle vectors of pointers. 2) It doesn't provide a cheaper visitor when the constant offset tracking isn't needed. 3) It doesn't support non-instruction pointer values. The current functionality is exactly what is required to implement the SROA pointer-use visitors in terms of this one, rather than in terms of their own ad-hoc base visitor, which was always very poorly specified. SROA has been converted to use this, and the code there deleted which this utility now provides. Technically speaking, using this new visitor allows SROA to handle a few more cases than it previously did. It is now more aggressive in ignoring chains of instructions which look like they would defeat SROA, but in fact do not because they never result in a read or write of memory. While this is "neat", it shouldn't be interesting for real programs as any such chains should have been removed by others passes long before we get to SROA. As a consequence, I've not added any tests for these features -- it shouldn't be part of SROA's contract to perform such heroics. The goal is to extend the functionality of this visitor going forward, and re-use it from passes like ASan that can benefit from doing a detailed walk of the uses of a pointer. Thanks to Ben Kramer for the code review rounds and lots of help reviewing and debugging this patch. llvm-svn: 169728
* Teach DAG combine to handle vector add/sub with vectors of all 0s.Craig Topper2012-12-101-0/+10
| | | | llvm-svn: 169727
* [CMake] Update dependencies to intrinsics_gen corresponding to r169711.NAKAMURA Takumi2012-12-104-5/+5
| | | | llvm-svn: 169724
* Fix PR14548: SROA was crashing on a mixture of i1 and i8 loads and stores.Chandler Carruth2012-12-101-2/+2
| | | | | | | | | | | | | | | | | | | When SROA was evaluating a mixture of i1 and i8 loads and stores, in just a particular case, it would tickle a latent bug where we compared bits to bytes rather than bits to bits. As a consequence of the latent bug, we would allow integers through which were not byte-size multiples, a situation the later rewriting code was never intended to handle. In release builds this could trigger all manner of oddities, but the reported issue in PR14548 was forming invalid bitcast instructions. The only downside of this fix is that it makes it more clear that SROA in its current form is not capable of handling mixed i1 and i8 loads and stores. Sometimes with the previous code this would work by luck, but usually it would crash, so I'm not terribly worried. I'll watch the LNT numbers just to be sure. llvm-svn: 169719
* Reorganize FastMathFlags to be a wrapper around unsigned, and streamline ↵Michael Ilseman2012-12-094-22/+22
| | | | | | some interfaces. llvm-svn: 169712
* LoopVectorize: support vectorizing intrinsic callsPaul Redmond2012-12-092-2/+74
| | | | | | | | | - added function to VectorTargetTransformInfo to query cost of intrinsics - vectorize trivially vectorizable intrinsic calls such as sin, cos, log, etc. Reviewed by: Nadav llvm-svn: 169711
* Have the bitcode reader/writer just use FPMathOperator's fast math enum directlyMichael Ilseman2012-12-092-10/+10
| | | | llvm-svn: 169710
* test commit.Paul Redmond2012-12-091-1/+1
| | | | llvm-svn: 169709
* Use m_OneUse pattern instead of hasOneUse() method.Jakub Staszak2012-12-091-7/+4
| | | | | | No functionality change. llvm-svn: 169703
* Remove trailing spaces.Jakub Staszak2012-12-091-80/+80
| | | | llvm-svn: 169701
* Switch SROA to pop Uses off the back of its visitors' queues.Chandler Carruth2012-12-091-10/+8
| | | | | | | | This will more closely match the behavior of the new PtrUseVisitor that I am adding. Hopefully this will not change the actual behavior in any way, but by making the processing order more similar help in debugging. llvm-svn: 169697
* Remove extra blank line.Craig Topper2012-12-091-1/+0
| | | | llvm-svn: 169692
* - Re-enable population count loop idiom recognization Shuxin Yang2012-12-094-20/+536
| | | | | | | - fix a bug which cause sigfault. - add two testing cases which was causing crash llvm-svn: 169687
* Teach DAG combine to handle vector logical operations with vectors of all 1s ↵Craig Topper2012-12-081-0/+30
| | | | | | or all 0s. These cases can show up when vectors are split for legalizing. Fix some tests that were dependent on these cases not being combined. llvm-svn: 169684
* Revert the patches adding a popcount loop idiom recognition pass.Chandler Carruth2012-12-084-533/+20
| | | | | | | | | | | | | | There are still bugs in this pass, as well as other issues that are being worked on, but the bugs are crashers that occur pretty easily in the wild. Test cases have been sent to the original commit's review thread. This reverts the commits: r169671: Fix a logic error. r169604: Move the popcnt tests to an X86 subdirectory. r168931: Initial commit adding the pass. llvm-svn: 169683
* Simplify code. Sort includes. No functionality change.Benjamin Kramer2012-12-081-6/+6
| | | | llvm-svn: 169676
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