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* [X86] Stop passing two arguments by reference. NFCCraig Topper2018-03-011-1/+1
| | | | | | I think these used to be out parameters, but they haven't been for a while. llvm-svn: 326417
* [RuntimeDyld][MachO] Fix assertion in encodeAddend, add missing directive toLang Hames2018-03-011-3/+5
| | | | | | | | | | | | test case. r326290 fixed the assertion for decodeAddend, but not encodeAddend. The regression test failed to catch this because it was missing the subsections_via_symbols flag, so the desired relocation was not applied. This patch also fixes the formatting of the assertion from r326290. llvm-svn: 326406
* [IPSCCP] do not break musttail invariant (PR36485)Reid Kleckner2018-03-011-1/+55
| | | | | | | | | | | | | | | | | Do not replace results of `musttail` calls with a constant if the call itself can't be removed. Do not zap returns of `musttail` callees, if the call site can't be removed and replaced with a constant. Do not zap returns of `musttail`-calling blocks, this breaks invariant too. Patch by Fedor Indutny Differential Revision: https://reviews.llvm.org/D43695 llvm-svn: 326404
* [GlobalISel][AArch64] Adding -disable-gisel-legality-check CL optionRoman Tereshin2018-03-013-27/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently it's impossible to test InstructionSelect pass with MIR which is considered illegal by the Legalizer in Assert builds. In early stages of porting an existing backend from SelectionDAG ISel to GlobalISel, however, we would have very basic CallLowering, Legalizer, and RegBankSelect implementations, but rather functional Instruction Select with quite a few patterns selectable due to the semi-automatic porting process borrowing them from SelectionDAG ISel. As we are trying to define legality as a property of being selectable by the instruction selector, it would be nice to be able to easily check what the selector can do in its current state w/o the legality check provided by the Legalizer getting in the way. It also seems beneficial to have a regression testing set up that would not allow the selector to silently regress in its support of the MIR not supported yet by the previous passes in the GlobalISel pipeline. This commit adds -disable-gisel-legality-check command line option to llc that disables those legality checks in RegBankSelect and InstructionSelect passes. It also adds quite a few MIR test cases for AArch64's Instruction Selector. Every one of them would fail on the legality check at the moment, but will select just fine if the check is disabled. Every test MachineFunction is intended to exercise a specific selection rule and that rule only, encoded in the MachineFunction's name by the rule's number, ID, and index of its GIM_Try opcode in TableGen'erated MatchTable (-optimize-match-table=false). Reviewers: ab, dsanders, qcolombet, rovka Reviewed By: bogner Subscribers: kristof.beyls, volkan, aditya_nandakumar, aemerson, rengolin, t.p.northover, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D42886 llvm-svn: 326396
* [DWARF] Emit a split line table only if there are split type units.Paul Robinson2018-03-012-0/+7
| | | | | | A .debug_info.dwo section doesn't use the .debug_line.dwo section. llvm-svn: 326395
* [DAE] don't remove args of musttail target/callerReid Kleckner2018-03-011-3/+37
| | | | | | | | | | | | | `musttail` requires identical signatures of caller and callee. Removing arguments breaks `musttail` semantics. PR36441 Patch by Fedor Indutny Differential Revision: https://reviews.llvm.org/D43708 llvm-svn: 326394
* [X86] Make sure we don't combine (fneg (fma X, Y, Z)) to a target specific ↵Craig Topper2018-03-011-1/+1
| | | | | | | | | | node when there are no FMA instructions. This would cause a 'cannot select' error at isel when we should have emitted a lib call and an xor. Fixes PR36553. llvm-svn: 326393
* [NVPTX] Lower loads from global constants using ld.global.nc (aka LDG).Justin Lebar2018-02-281-14/+18
| | | | | | | | | | | | | | | Summary: After D43914, loads from global variables in addrspace(1) happen with ld.global. But since they're constants, even better would be to use ld.global.nc, aka ldg. Reviewers: tra Subscribers: jholewinski, sanjoy, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D43915 llvm-svn: 326390
* [NVPTX] Use addrspacecast instead of target-specific intrinsics in ↵Justin Lebar2018-02-281-51/+9
| | | | | | | | | | | | | | | | | | | NVPTXGenericToNVVM. Summary: NVPTXGenericToNVVM was using target-specific intrinsics to do address space casts. Using the addrspacecast instruction is (a lot) simpler. But it also has the advantage of being understandable to other passes. In particular, InferAddrSpaces is able to understand these address space casts and remove them in most cases. Reviewers: tra Subscribers: jholewinski, sanjoy, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D43914 llvm-svn: 326389
* [MIRParser] Accept overloaded intrinsic names w/o type suffixesRoman Tereshin2018-02-281-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function::lookupIntrinsicID is somewhat forgiving as it comes to overloaded intrinsics' names: it returns an ID as soon as the name provided has a prefix that matches a registered intrinsic's name w/o actually checking that the rest of the name encodes all the concrete arg types, let alone that those types are compatible with the intrinsic's definition. That's probably fine and comes in handy in MIR serialization: we don't care about IR types at MIR level and every intrinsic should be selectable based on its ID and low-level types (LLTs) of its operands, including the overloaded ones, so there is no point in serializing mangled IR types as part of the intrinsic's name. However, lookupIntrinsicID is somewhat inconsistent in its forgiveness: if the name provided is actually an exact match, it will refuse to return the ID if the intrinsic is overloaded. There is probably no real reason for that and it renders MIRParser incapable to deserialize MIR MIRPrinter serialized. This commit fixes it. Reviewers: rnk, aditya_nandakumar, qcolombet, thegameg, dsanders, marcello.maggioni Reviewed By: bogner Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D43267 llvm-svn: 326387
* [InstCombine] simplify code for X * -1.0 --> -X; NFCSanjay Patel2018-02-281-7/+3
| | | | | | I've added random FMF to one of the tests to show those are propagated. llvm-svn: 326377
* [GlobalOpt] don't change CC of musttail calle(e|r)Jonas Devlieghere2018-02-281-1/+24
| | | | | | | | | | | | | | | When the function has musttail call - its cc is fixed to be equal to the cc of the musttail callee. In such case (and in the case of the musttail callee), GlobalOpt should not change the cc to fastcc as it will break the invariant. This fixes PR36546 Patch by: Fedor Indutny (indutny) Differential revision: https://reviews.llvm.org/D43859 llvm-svn: 326376
* [X86] Lower extract_element from k-registers by bitcasting from v16i1 to i16 ↵Craig Topper2018-02-283-28/+20
| | | | | | | | and extending/truncating. This is equivalent to what isel was doing anyway but by canonicalizing earlier we can remove some patterns. llvm-svn: 326375
* [X86][AVX512] Improve support for signed saturation truncation storesSimon Pilgrim2018-02-281-0/+20
| | | | | | | | Matches what we already manage for unsigned saturation truncation stores Differential Revision: https://reviews.llvm.org/D43629 llvm-svn: 326372
* [Hexagon] Implement target feature +reserved-r19Krzysztof Parzyszek2018-02-283-0/+8
| | | | llvm-svn: 326364
* [InstCombine] Split the FP constant code out of lookThroughFPExtensions and ↵Craig Topper2018-02-281-15/+20
| | | | | | | | | | | | | | use nullptr as a sentinel Currently this code's control flow very much assumes that there are no meaningful checks after determining that it's a ConstantFP. So whenever it wants to stop it just does "return V". But V is also the variable name it uses when it wants to return a new value. So 'return V' appears multiple times with different meanings. This patch just moves all the code into a helper function and returns nullptr when it wants to stop. I've split this from D43774 while I try to figure out how to best handle the vector case there. But this change by itself at least seemed like a readability improvement. Differential Revision: https://reviews.llvm.org/D43833 llvm-svn: 326361
* Fix llvm-config --system-libs output on FreeBSD and NetBSDDimitry Andric2018-02-281-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For various reasons, CMake's detection mechanism for `backtrace()` returns an absolute path `/usr/lib/libexecinfo.so` on FreeBSD and NetBSD. Since `tools/llvm-config/CMakeLists.txt` only checks if system libraries start with `-`, this causes `llvm-config --system-libs` to produce the following incorrect output: ``` -lrt -l/usr/lib/libexecinfo.so -ltinfo -lpthread -lz -lm ``` Fix it by removing the path and the `lib` prefix, to make it look like a regular short library name, suitable for appending to a `-l` link flag. This also fixes the `Bindings/Go/go.test` test case, since that always died with "unable to find library -l/usr/lib/libexecinfo.so". Reviewers: chandlerc, emaste, joerg, krytarowski Reviewed By: krytarowski Subscribers: hans, bdrewery, mgorny, hintonda, llvm-commits Differential Revision: https://reviews.llvm.org/D42702 llvm-svn: 326358
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-283-7/+47
| | | | | | | | | | | | | | | | | Summary: For use by LLPC SPV_AMD_shader_ballot extension. The v_writelane instruction was already implemented for use by SGPR spilling, but I had to add an extra dummy operand tied to the destination, to represent that all lanes except the selected one keep the old value of the destination register. .ll test changes were due to schedule changes caused by that new operand. Differential Revision: https://reviews.llvm.org/D42838 llvm-svn: 326353
* Fixed spelling mistake in comments of LLVM Analysis passesVedant Kumar2018-02-284-14/+14
| | | | | | | | Patch by Reshabh Sharma! Differential Revision: https://reviews.llvm.org/D43861 llvm-svn: 326352
* [InstrProfiling] Emit the runtime hook when no counters are loweredVedant Kumar2018-02-281-12/+13
| | | | | | | | | | | | | | | | | | | | | | The API verification tool tapi has difficulty processing frameworks which enable code coverage, but which have no code. The profile lowering pass does not emit the runtime hook in this case because no counters are lowered. While the hook is not needed for program correctness (the profile runtime doesn't have to be linked in), it's needed to allow tapi to validate the exported symbol set of instrumented binaries. It was not possible to add a workaround in tapi for empty binaries due to an architectural issue: tapi generates its expected symbol set before it inspects a binary. Changing that model has a higher cost than simply forcing llvm to always emit the runtime hook. rdar://36076904 Differential Revision: https://reviews.llvm.org/D43794 llvm-svn: 326350
* [NVPTX] Removed always-true predicates in NVPTX.Artem Belevich2018-02-285-216/+132
| | | | | | | | | | | NVPTX stopped supporting GPUs older than sm_20 (Fermi) quite a while back. Removal of support of pre-Fermi GPUs made a lot of predicates in the NVPTX backend pointless as they can't ever be false any more. It's time to retire them. NFC intended. Differential Revision: https://reviews.llvm.org/D43843 llvm-svn: 326349
* [GlobalISel] Print/Parse FailedISel MachineFunction propertyRoman Tereshin2018-02-285-13/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FailedISel MachineFunction property is part of the CodeGen pipeline state as much as every other property, notably, Legalized, RegBankSelected, and Selected. Let's make that part of the state also serializable / de-serializable, so if GlobalISel aborts on some of the functions of a large module, but not the others, it could be easily seen and the state of the pipeline could be maintained through llc's invocations with -stop-after / -start-after. To make MIR printable and generally to not to break it too much too soon, this patch also defers cleaning up the vreg -> LLT map until ResetMachineFunctionPass. To make MIR with FailedISel: true also machine verifiable, machine verifier is changed so it treats a MIR-module as non-regbankselected and non-selected if there is FailedISel property set. Reviewers: qcolombet, ab Reviewed By: dsanders Subscribers: javed.absar, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42877 llvm-svn: 326343
* [TLS] use emulated TLS if the target supports only this modeChih-Hung Hsieh2018-02-2813-11/+21
| | | | | | | | | | | | | | | Emulated TLS is enabled by llc flag -emulated-tls, which is passed by clang driver. When llc is called explicitly or from other drivers like LTO, missing -emulated-tls flag would generate wrong TLS code for targets that supports only this mode. Now use useEmulatedTLS() instead of Options.EmulatedTLS to decide whether emulated TLS code should be generated. Unit tests are modified to run with and without the -emulated-tls flag. Differential Revision: https://reviews.llvm.org/D42999 llvm-svn: 326341
* [WebAssembly] Reorder symbol table to match MC orderNicholas Wilson2018-02-281-41/+40
| | | | | | | | This removes a TODO introduced in rL325860 Differential Revision: https://reviews.llvm.org/D43685 llvm-svn: 326334
* [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operationsPablo Barrio2018-02-281-0/+61
| | | | | | | | | | | | | | | | | | | Summary: Expressions of the form x < 0 ? 0 : x; and x < -1 ? -1 : x can be lowered using bit-operations instead of branching or conditional moves In thumb-mode this results in a two-instruction sequence, a shift followed by a bic or or while in ARM/thumb2 mode that has flexible second operand the shift can be folded into a single bic/or instructions. In most cases this results in smaller code and possibly less branches, and in no case larger than before. Patch by Martin Svanfeldt Reviewers: fhahn, pbarrio, rogfer01 Reviewed By: pbarrio, rogfer01 Subscribers: chrib, yroux, eugenis, efriedma, rogfer01, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42574 llvm-svn: 326333
* [InstCombine] move invariant call out of loop; NFCSanjay Patel2018-02-281-4/+4
| | | | | | We really shouldn't need a 2-loop here at all, but that's another cleanup. llvm-svn: 326330
* [InstCombine] move constant check into foldBinOpIntoSelectOrPhi; NFCISanjay Patel2018-02-286-34/+29
| | | | | | | | Also, rename 'foldOpWithConstantIntoOperand' because that's annoyingly vague. The constant check is redundant in some cases, but it allows removing duplication for most of the calls. llvm-svn: 326329
* [DEBUGINFO] Add flag for DWARF2 or less to use sections as references.Alexey Bataev2018-02-283-11/+50
| | | | | | | | | | | | | | | | | Summary: Some targets does not support labels inside debug sections, but support references in form `section +|- offset`. Patch adds initial support for this. Also, this patch disables emission of all additional debug sections that may have labels inside of it (like pub sections and string tables). Reviewers: probinson, echristo Subscribers: JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D43627 llvm-svn: 326328
* [WebAssembly] Fix copy-paste error in debugging stringNicholas Wilson2018-02-281-1/+1
| | | | llvm-svn: 326326
* [mips] Begin reworking instruction predicates for ISAs/encodings (1/N)Simon Dardis2018-02-283-22/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS backend has inconsistent usage of instruction predicates for assembly and code generation. The issue arises from supporting three encodings, two (MIPS and microMIPS) of which have a near 1:1 instruction mapping across ISA revisions and a third encoding with a more restricted set of instructions (MIPS16e). To enforce consistent usage, each of the ISA_* adjectives has (or will have) the relevant encoding attached to it along the relevant ISA revision where the instruction is defined. Each instruction, pattern or alias will then have the correct ISA adjective attached to it, and the base instruction description classes will have any predicates relating to ISA encoding or revision removed. Pseudo instructions will also be guarded for the encoding or ABI that they are supported in. Finally, the hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods of MipsSubtarget will be changed such that only one can be true at any one time. The result of this is that code generation and assembly will produce the correct encoding up front, while code generated from pseudo instructions and other inserted sequences of instructions will be able to rely on the mapping tables to produce the correct encoding. This should fix numerous bugs where the result 'happens' to be correct but has edge cases where microMIPS and MIPS have subtle differences (e.g. microMIPSR6 using 'j', 'jal' instructions.) This patch starts the process by changing most of the ISA adjectives to make use of the EncodingPredicate member of PredicateControl. Follow on patches will annotate instructions with their correct ISA adjective and eliminate the usage of "let Predicates = [..]", "let AdditionalPredicates = [..]" and "isCodeGenOnly = 1" in the cases where it was used to control instruction availability. Contributions from Nitesh Jain. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41434 llvm-svn: 326322
* [GlobalIsel][X86] Support G_INTTOPTR instruction.Alexander Ivchenko2018-02-282-1/+6
| | | | | | | | | | | Add legalization/selection for x86/x86_64 and corresponding tests. Reviewed By: igorb Differential Revision: https://reviews.llvm.org/D43622 llvm-svn: 326320
* Fix typo. NFCXin Tong2018-02-281-1/+1
| | | | llvm-svn: 326319
* [MergeICmp] Fix a bug in MergeICmp that can lead to a block being processed ↵Xin Tong2018-02-281-0/+13
| | | | | | | | | | | | | | | | | | | | | more than once. Summary: Fix a bug in MergeICmp that can lead to a BCECmp block being processed more than once and eventually lead to a broken LLVM module. The problem is that if the non-constant value is not produced by the last block, the producer will be processed once when the its parent block is processed and second time when the last block is processed. We end up having 2 same BCECmpBlock in the merge queue. And eventually lead to a broken LLVM module. Reviewers: courbet, davide Reviewed By: courbet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43825 llvm-svn: 326318
* [Dominators] Remove verifyDomTree and add some verifying for Post Dom TreesDavid Green2018-02-289-60/+45
| | | | | | | | | | | | Removes verifyDomTree, using assert(verify()) everywhere instead, and changes verify a little to always run IsSameAsFreshTree first in order to print good output when we find errors. Also adds verifyAnalysis for PostDomTrees, which will allow checking of PostDomTrees it the same way we check DomTrees and MachineDomTrees. Differential Revision: https://reviews.llvm.org/D41298 llvm-svn: 326315
* [GlobalIsel][X86] Support G_PTRTOINT instruction.Alexander Ivchenko2018-02-282-10/+30
| | | | | | | | | | | Add legalization/selection for x86/x86_64 and corresponding tests. Reviewed By: igorb Differential Revision: https://reviews.llvm.org/D43617 llvm-svn: 326311
* [X86] Don't use EXTRACT_ELEMENT from v1i1 with i8/i32 result type when we ↵Craig Topper2018-02-283-15/+58
| | | | | | | | | | need to guarantee zeroes in the upper bits of return. An extract_element where the result type is larger than the scalar element type is semantically an any_extend of from the scalar element type to the result type. If we expect zeroes in the upper bits of the i8/i32 we need to mae sure those zeroes are explicit in the DAG. For these cases the best way to accomplish this is use an insert_subvector to pad zeroes to the upper bits of the v1i1 first. We extend to either v16i1(for i32) or v8i1(for i8). Then bitcast that to a scalar and finish with a zero_extend up to i32 if necessary. We can't extend past v16i1 because that's the largest mask size on KNL. But isel is smarter enough to know that a zext of a bitcast from v16i1 to i16 can use a KMOVW instruction. The insert_subvectors will be dropped during isel because we can determine that the producing instruction already zeroed the upper bits of the k-register. llvm-svn: 326308
* [X86] Change the masked FPCLASS implementation to use AND instead of OR to ↵Craig Topper2018-02-282-10/+8
| | | | | | | | | | | | | | | | | | | | | | combine the mask results. While the description for the instruction does mention OR, its talking about how the individual classification test results are ORed together. The incoming mask is used as a zeroing write mask. If the bit is 1 the classification is written to the output. The bit is 0 the output is 0. This equivalent to an AND. Here is pseudocode from the intrinsics guide FOR j := 0 to 1 i := j*64 IF k1[j] k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0]) ELSE k[j] := 0 FI ENDFOR k[MAX:2] := 0 llvm-svn: 326306
* [ARM] Cortex-A57 scheduler fix for ARM backend (missed 16-bit, ↵Andrew Zhogin2018-02-281-5/+33
| | | | | | | | | | | | v8.1/v8.2/v8.3, thumb and pseudo instructions) Added missed scheduling info for ARM Cortex A57 (AArch32) to have CompleteModel with this checkCompleteness fix: https://reviews.llvm.org/D43235. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D43808 llvm-svn: 326304
* [RuntimeDyld][MachO] Support ARM64_RELOC_BRANCH26 for BL instructions byLang Hames2018-02-281-2/+4
| | | | | | relaxing an assertion. llvm-svn: 326290
* [WebAssembly] Remove DataSize from linking metadata sectionSam Clegg2018-02-273-15/+3
| | | | | | | | | | | Neither the linker nor the runtime need this information anymore. We were originally using this to model BSS size but the plan is now to use the segment metadata to allow for BSS segments. Differential Revision: https://reviews.llvm.org/D41366 llvm-svn: 326267
* [Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiplyKrzysztof Parzyszek2018-02-271-2/+13
| | | | llvm-svn: 326263
* [Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAXKrzysztof Parzyszek2018-02-271-2/+4
| | | | | | | | | Absence of memory operands is treated as "aliasing everything", so dropping them is sufficient. Recommit r326256 with a fixed testcase. llvm-svn: 326262
* [CodeView] Lower __restrict and other pointer qualifiers correctlyReid Kleckner2018-02-274-19/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Qualifiers on a pointer or reference type may apply to either the pointee or the pointer itself. Consider 'const char *' and 'char * const'. In the first example, the pointee data may not be modified without casts, and in the second example, the pointer may not be updated to point to new data. In the general case, qualifiers are applied to types with LF_MODIFIER records, which support the usual const and volatile qualifiers as well as the __unaligned extension qualifier. However, LF_POINTER records, which are used for pointers, references, and member pointers, have flags for qualifiers applying to the *pointer*. In fact, this is the only way to represent the restrict qualifier, which can only apply to pointers, and cannot qualify regular data types. This patch causes LLVM to correctly fold 'const' and 'volatile' pointer qualifiers into the pointer record, as well as adding support for '__restrict' qualifiers in the same place. Based on a patch from Aaron Smith Differential Revision: https://reviews.llvm.org/D43060 llvm-svn: 326260
* Revert "[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX"Krzysztof Parzyszek2018-02-271-4/+2
| | | | | | This reverts r326256. One testcase needs to be updated. llvm-svn: 326259
* [Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAXKrzysztof Parzyszek2018-02-271-2/+4
| | | | | | | Absence of memory operands is treated as "aliasing everything", so dropping them is sufficient. llvm-svn: 326256
* [AsmPrinter] Handle qualified unnamed types in CodeView printerShoaib Meenai2018-02-271-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When attempting to compile the following Objective-C++ code with CodeView debug info: void (^b)(void) = []() {}; The generated debug metadata contains a structure like the following: !43 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_1", scope: !6, file: !6, line: 1, size: 168, elements: !44) !44 = !{!45, !46, !47, !48, !49, !52} ... !52 = !DIDerivedType(tag: DW_TAG_member, scope: !6, file: !6, line: 1, baseType: !53, size: 8, offset: 160, flags: DIFlagPublic) !53 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !54) !54 = !DICompositeType(tag: DW_TAG_class_type, file: !6, line: 1, flags: DIFlagFwdDecl) Note that the member node (!52) is unnamed, but rather than pointing to a DICompositeType directly, it points to a DIDerivedType with tag DW_TAG_const_type, which then points to the DICompositeType. However, the CodeView assembly printer currently assumes that the base type for an unnamed member will always be a DICompositeType, and attempts to perform that cast, which triggers an assertion failure, since in this case the base type is actually a DIDerivedType, not a DICompositeType (and we would have to get the base type of the DIDerivedType to reach the DICompositeType). I think the debug metadata being generated by the frontend is correct (or at least plausible), and the CodeView printer needs to handle this case. This patch teaches the CodeView printer to unwrap any qualifier types. The qualifiers are just dropped for now. Ideally, they would be applied to the added indirect members instead, but this occurs infrequently enough that adding the logic to handle the qualifiers correctly isn't worth it for now. A FIXME is added to note this. Additionally, Reid pointed out that the underlying assumption that an unnamed member must be a composite type is itself incorrect and may not hold for all frontends. Therefore, after all qualifiers have been stripped, check if the resulting type is in fact a DICompositeType and just return if it isn't, rather than assuming the type and crashing if that assumption is violated. Differential Revision: https://reviews.llvm.org/D43803 llvm-svn: 326255
* [codeview] Remove unused variableReid Kleckner2018-02-271-1/+0
| | | | llvm-svn: 326253
* AMDGPU: Add fast fmaf feature to gfx702Konstantin Zhuravlyov2018-02-271-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D43790 llvm-svn: 326252
* [ValueTracking] Teach cannotBeOrderedLessThanZeroImpl to look through ↵Craig Topper2018-02-271-0/+6
| | | | | | | | | | ExtractElement. This is similar to what's done in computeKnownBits and computeSignBits. Don't do anything fancy just collect information valid for any element. Differential Revision: https://reviews.llvm.org/D43789 llvm-svn: 326237
* [ARM] Another f16 litpool fixSjoerd Meijer2018-02-271-2/+6
| | | | | | | | | | | | | We were always setting the block alignment to 2 bytes in Thumb mode and 4-bytes in ARM mode (r325754, and r325012), but this could cause reducing the block alignment when it already had been aligned (e.g. in Thumb mode when the block is a CPE that was already 4-byte aligned). Patch by Momchil Velikov, I've only added a test. Differential Revision: https://reviews.llvm.org/D43777 llvm-svn: 326232
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