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* ARM assembly aliases for add negative immediates using sub.Jim Grosbach2012-04-053-5/+72
| | | | | | | | | | 'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out. Thumb1 aliases for adding a negative immediate to the stack pointer, also. rdar://11192734 llvm-svn: 154123
* Patch to set is_stmt a little better for prologue lines in a function.Eric Christopher2012-04-051-2/+5
| | | | | | | | | This enables debuggers to see what are interesting lines for a breakpoint rather than any line that starts a function. rdar://9852092 llvm-svn: 154120
* Don't break the IV update in TLI::SimplifySetCC().Jakob Stoklund Olesen2012-04-051-15/+27
| | | | | | | | | | | | | | | | | | | LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> llvm-svn: 154119
* Fix accidentally inverted logic from r152803, and make theDan Gohman2012-04-051-1/+1
| | | | | | testcase slightly less trivial. This fixes rdar://11171718. llvm-svn: 154118
* Treat f16 the same as f80/f128 for the purposes of generating constants ↵Owen Anderson2012-04-051-1/+2
| | | | | | during instruction selection. llvm-svn: 154113
* Added support for unpredictable ADC/SBC instructions on ARM, and also fixed ↵Silviu Baranga2012-04-051-4/+4
| | | | | | some corner cases involving the PC register as an operand for these instructions. llvm-svn: 154101
* Added support for handling unpredictable arithmetic instructions on ARM.Silviu Baranga2012-04-051-0/+2
| | | | llvm-svn: 154100
* BBVectorize: Add the const modifier to the VectorizeConfig because we won'tHongbin Zheng2012-04-051-1/+1
| | | | | | modify it. llvm-svn: 154098
* Introduce the VectorizeConfig class, with which we can control the behaviorHongbin Zheng2012-04-051-32/+60
| | | | | | | | | of the BBVectorizePass without using command line option. As pointed out by Hal, we can ask the TargetLoweringInfo for the architecture specific VectorizeConfig to perform vectorizing with architecture specific information. llvm-svn: 154096
* Add the function "vectorizeBasicBlock" which allow users vectorize aHongbin Zheng2012-04-051-5/+19
| | | | | | | BasicBlock in other passes, e.g. we can call vectorizeBasicBlock in the loop unroll pass right after the loop is unrolled. llvm-svn: 154089
* ARM assembly aliases for two-operand V[R]SHR instructions.Jim Grosbach2012-04-051-5/+36
| | | | | | rdar://11189467 llvm-svn: 154087
* In MemoryBuffer::getOpenFile() make sure that the buffer is null-terminated ifArgyrios Kyrtzidis2012-04-051-0/+11
| | | | | | | | | | | | | the caller requested a null-terminated one. When mapping the file there could be a racing issue that resulted in the file being larger than the FileSize passed by the caller. We already have an assertion for this in MemoryBuffer::init() but have a runtime guarantee that the buffer will be null-terminated, so do a copy that adds a null-terminator. Protects against crash of rdar://11161822. llvm-svn: 154082
* ARM assembly parsing for 'msr' plain 'cpsr' operand.Jim Grosbach2012-04-051-1/+2
| | | | | | | | Plain 'cpsr' is an alias for 'cpsr_fc'. rdar://11153753 llvm-svn: 154080
* Pass the right sign to TLI->isLegalICmpImmediate.Jakob Stoklund Olesen2012-04-051-2/+11
| | | | | | | | | | | | | | | | | | LSR can fold three addressing modes into its ICmpZero node: ICmpZero BaseReg + Offset => ICmp BaseReg, -Offset ICmpZero -1*ScaleReg + Offset => ICmp ScaleReg, Offset ICmpZero BaseReg + -1*ScaleReg => ICmp BaseReg, ScaleReg The first two cases are only used if TLI->isLegalICmpImmediate() likes the offset. Make sure the right Offset sign is passed to this method in the second case. The ARM version is not symmetric. <rdar://problem/11184260> llvm-svn: 154079
* Reapply 154038 without the failing test.Akira Hatanaka2012-04-041-3/+3
| | | | llvm-svn: 154062
* Revert r154038. It was causing make check failures.Owen Anderson2012-04-041-3/+3
| | | | llvm-svn: 154054
* REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub ↵Pete Cooper2012-04-041-1/+2
| | | | | | register indices on the source registers. No simple test case llvm-svn: 154051
* Fix a C++11 UDL conflict.Benjamin Kramer2012-04-041-1/+1
| | | | | | Still not fixed in the standard ;) llvm-svn: 154044
* f16 FREM can now be legalized by promoting to f32Pete Cooper2012-04-041-0/+1
| | | | llvm-svn: 154039
* Fix LowerGlobalAddress to produce instructions with the correct relocationAkira Hatanaka2012-04-041-3/+3
| | | | | | types for N32 ABI. Add new test case and update existing ones. llvm-svn: 154038
* Fix LowerJumpTable to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | | types for N32 ABI. Test case will be updated after the patch that fixes TargetLowering::getPICJumpTableRelocBase is checked in. llvm-svn: 154036
* Fix LowerConstantPool to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | types for N32 ABI and update test case. llvm-svn: 154034
* Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.Jakob Stoklund Olesen2012-04-045-5/+30
| | | | | | | | | | A MOVCCr instruction can be commuted by inverting the condition. This can help reduce register pressure and remove unnecessary copies in some cases. <rdar://problem/11182914> llvm-svn: 154033
* Remove spurious debug output.Jakob Stoklund Olesen2012-04-041-1/+0
| | | | llvm-svn: 154032
* Fix LowerBlockAddress to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | types for N32 ABI and update test case. llvm-svn: 154031
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-0431-409/+245
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* LoopUnrollPass: Use variable "Threshold" instead of "CurrentThreshold" whenHongbin Zheng2012-04-041-2/+2
| | | | | | | reducing unroll count, otherwise the reduced unroll count is not taking the "OptimizeForSize" attribute into account. llvm-svn: 154007
* Move yaml::Stream's dtor out of line so it can see Scanner's dtor.Benjamin Kramer2012-04-041-0/+2
| | | | llvm-svn: 154004
* Remove default case from switch that was already covering all cases.Craig Topper2012-04-041-1/+0
| | | | llvm-svn: 153996
* Removed useless switch for default case when switch was covering all the ↵Pete Cooper2012-04-041-1/+0
| | | | | | enum values llvm-svn: 153984
* Sorry about that. MSVC seems to accept just about any random string you give ↵Michael J. Spencer2012-04-031-2/+2
| | | | | | it ;/ llvm-svn: 153979
* Add YAML parser to Support.Michael J. Spencer2012-04-032-0/+2116
| | | | llvm-svn: 153977
* Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it ↵Pete Cooper2012-04-032-0/+34
| | | | | | would crash if it encountered a 1 element VSELECT. Solution is slightly more complicated than just creating a SELET as we have to mask or sign extend the vector condition if it had different boolean contents from the scalar condition. Fixes <rdar://problem/11178095> llvm-svn: 153976
* Removed one last bad continue statement meant to be removed in r153914.Pete Cooper2012-04-031-1/+0
| | | | llvm-svn: 153975
* Fix an issue in SimplifySetCC() specific to vector comparisons.Chad Rosier2012-04-031-2/+10
| | | | | | | | | | | When folding X == X we need to check getBooleanContents() to determine if the result is a vector of ones or a vector of negative ones. I tried creating a test case, but the problem seems to only be exposed on a much older version of clang (around r144500). rdar://10923049 llvm-svn: 153966
* Fix thinko check for number of operands to be the one that actuallyEric Christopher2012-04-031-1/+1
| | | | | | | | | might have more than 19 operands. Add a testcase to make sure I never screw that up again. Part of rdar://11026482 llvm-svn: 153961
* ARMDisassembler: drop bogus dependency on ARMCodeGenDylan Noblesmith2012-04-032-3/+2
| | | | | | | And indirectly, a dependency on most of the core LLVM optimization libraries. llvm-svn: 153957
* Object: drop bogus VMCore dependencyDylan Noblesmith2012-04-031-1/+1
| | | | llvm-svn: 153956
* The speedup doesn't appear to have been from this, but was an anomaly of my ↵Bill Wendling2012-04-031-1/+0
| | | | | | testing machine. llvm-svn: 153951
* Reserve space for the eventual filling of the vector. This gives a small ↵Bill Wendling2012-04-031-4/+3
| | | | | | speedup. llvm-svn: 153949
* Make PPCCompilationCallbackC function to be static, so there will be no need ↵Anton Korobeynikov2012-04-031-3/+5
| | | | | | | | to issue call via PLT when LLVM is built as shared library. This mimics the X86 backend towards the approach. llvm-svn: 153938
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-035-41/+49
| | | | llvm-svn: 153935
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-034-0/+0
| | | | | | lib/Target/Mips/Disassembler. llvm-svn: 153926
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-0313-925/+104
| | | | llvm-svn: 153925
* MIPS disassembler support.Akira Hatanaka2012-04-0313-104/+925
| | | | | | Patch by Vladimir Medic. llvm-svn: 153924
* Add a line number for the scope of the function (starting at the firstEric Christopher2012-04-033-5/+20
| | | | | | | | | | brace) so that we get more accurate line number information about the declaration of a given function and the line where the function first starts. Part of rdar://11026482 llvm-svn: 153916
* Fixes to r153903. Added missing explanation of behaviour when the ↵Pete Cooper2012-04-031-5/+5
| | | | | | VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created llvm-svn: 153914
* Moved LiveRangeEdit.h so that it can be called from other parts of the ↵Pete Cooper2012-04-029-210/+8
| | | | | | backend, not just libCodeGen llvm-svn: 153906
* Allocate virtual registers in ascending order.Jakob Stoklund Olesen2012-04-021-2/+2
| | | | | | | | | This is just the fallback tie-breaker ordering, the main allocation order is still descending size. Patch by Shamil Kurmangaleev! llvm-svn: 153904
* Refactored the LiveRangeEdit interface so that MachineFunction, ↵Pete Cooper2012-04-028-93/+76
| | | | | | TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method. llvm-svn: 153903
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