| Commit message (Collapse) | Author | Age | Files | Lines |
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ambiguity
errors like the one corrected by r135261. Migrate all LLVM callers of the old
constructor to the new one.
llvm-svn: 135431
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llvm-svn: 135426
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to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
llvm-svn: 135424
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at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
[take 2]
llvm-svn: 135423
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For -disable-iv-rewrite, perform LFTR without generating a new
"canonical" induction variable. Instead find the "best" existing
induction variable for use in the loop exit test and compute the final
value of that IV for use in the new loop exit test. In short,
convert to a simple eq/ne exit test as long as it's cheap to do so.
llvm-svn: 135420
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llvm-svn: 135418
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moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
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Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
llvm-svn: 135414
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When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.
We need the value number entering the instruction.
<rdar://problem/9793765>
llvm-svn: 135413
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not interfere with BackedgeTakenCount computation.
llvm-svn: 135412
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preheader for the sole purpose of LFTR, since LFTR itself is usually not
a clear optimization.
llvm-svn: 135409
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definitions.
llvm-svn: 135407
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llvm-svn: 135404
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virtual registers are used.
llvm-svn: 135403
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previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.
llvm-svn: 135390
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When trying to rematerialize a value before an instruction that has an
early-clobber redefine of the virtual register, make sure to look up the
correct value number.
Early-clobber defs are moved one slot back, so getBaseIndex is needed to
find the used value number.
Bugpoint was unable to reduce the test case for this, see PR10388.
llvm-svn: 135378
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llvm-svn: 135375
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mallocs.
llvm-svn: 135366
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llvm-svn: 135364
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llvm-svn: 135362
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llvm-svn: 135360
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llvm-svn: 135358
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llvm-svn: 135354
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llvm-svn: 135353
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llvm-svn: 135352
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llvm-svn: 135343
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llvm-svn: 135339
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assertion I added in r135333. Check for the existence of a preheader
before expanding a recurrence.
llvm-svn: 135335
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llvm-svn: 135334
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related bug fixes and corresponding assertions for uninitialized data
and missing NULL check. Test cases will be included with the new LFTR.
llvm-svn: 135333
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llvm-svn: 135332
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This should unbreak the build-self-4-mingw32 tester. I have a very
complicated test case that I will try to clean up.
llvm-svn: 135329
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fixing some objc llvm-test crashes with LTO.
llvm-svn: 135324
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llvm-svn: 135323
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llvm-svn: 135320
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tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
llvm-svn: 135319
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and just use the ones from TargetLowering directly.
llvm-svn: 135318
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1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.
2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.
3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.
4) Tidy up code to be more clear and explicit about AVX.
llvm-svn: 135313
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comming together with other tests.
llvm-svn: 135312
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llvm-svn: 135311
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This gets rid of some of the gory splitting details in RAGreedy and
makes them available to future SplitKit clients.
Slightly generalize the functionality to support multi-way splitting.
Specifically, SplitEditor::splitLiveThroughBlock() supports switching
between different register intervals in a block.
llvm-svn: 135307
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llvm-svn: 135305
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llvm-svn: 135303
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lexical scope.
llvm-svn: 135302
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not isEquality().
llvm-svn: 135296
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to simplify the path towards an auto-generated disassembler.
llvm-svn: 135290
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- No ELF or COFF implementation yet, I don't have a way to test that.
Should be straightforward to add though.
llvm-svn: 135288
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is named after a common idiom (i.e., memset/memcpy). Otherwise, we can run into
infinite recursion. Ideally, the user should use the correct -fno-builtin flag,
but in case they don't we should play nicely.
rdar://9763412
llvm-svn: 135286
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the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly.
llvm-svn: 135283
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llvm-svn: 135282
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