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* Add additional check to ensure that iv is canonicalized.Devang Patel2008-09-031-0/+1
| | | | llvm-svn: 55682
* Check iteration count.Devang Patel2008-09-031-0/+4
| | | | llvm-svn: 55680
* Let tblgen only generate fastisel routines, not the class definition. This ↵Evan Cheng2008-09-034-39/+28
| | | | | | makes it easier for targets to define its own fastisel class. llvm-svn: 55679
* While removing PHI, use basicblock to identify incoming value.Devang Patel2008-09-031-2/+3
| | | | llvm-svn: 55678
* s/FP_AlwaysInline/FN_NOTE_AlwaysInline/gDevang Patel2008-09-025-23/+23
| | | | llvm-svn: 55676
* If all IV uses are extending integer IV then change the type of IV itself, ↵Devang Patel2008-09-021-0/+201
| | | | | | if possible. llvm-svn: 55674
* respect inline=never and inline=always notes.Devang Patel2008-09-021-1/+8
| | | | llvm-svn: 55673
* 80 col violations.Evan Cheng2008-09-021-2/+4
| | | | llvm-svn: 55668
* Read and write function notes.Devang Patel2008-09-022-0/+4
| | | | llvm-svn: 55657
* Use bitwise AND.Devang Patel2008-09-021-2/+2
| | | | llvm-svn: 55656
* Print function notes.Devang Patel2008-09-021-1/+9
| | | | llvm-svn: 55647
* Parse function notes.Devang Patel2008-09-025-1408/+1566
| | | | llvm-svn: 55646
* Initialize function notes.Devang Patel2008-09-021-0/+2
| | | | llvm-svn: 55645
* Fix some bugs in the code sequences for atomics.Dale Johannesen2008-09-021-10/+10
| | | | llvm-svn: 55643
* Ensure that HandlePHINodesInSuccessorBlocks is run for all blocks,Dan Gohman2008-09-021-3/+9
| | | | | | | even in FastISel mode in the case where FastISel successfully selects all the instructions. llvm-svn: 55641
* plug a little memleak in verifyFunction()Nuno Lopes2008-09-021-1/+3
| | | | | | # first commit to llvm, so whatch out :) llvm-svn: 55631
* MMI may be null.Evan Cheng2008-09-021-1/+3
| | | | llvm-svn: 55626
* Add Mac OS X compatible JIT callback routine.Evan Cheng2008-09-021-5/+29
| | | | llvm-svn: 55625
* Revamp ARM JIT.Evan Cheng2008-09-021-490/+375
| | | | llvm-svn: 55624
* Change getBinaryCodeForInstr prototype. First operand MachineInstr& should ↵Evan Cheng2008-09-022-12/+15
| | | | | | be const. Make corresponding changes. llvm-svn: 55623
* Provide two overloads of AnalyzeNewNode.Gabor Greif2008-09-012-17/+24
| | | | | | | | | | | The first can update the SDNode in an SDValue while the second is called with SDNode* and returns a possibly updated SDNode*. This patch has no intended functional impact, but helps eliminating ugly temporary SDValues. llvm-svn: 55608
* Even though no caller actually uses the new valueDuncan Sands2008-09-011-1/+2
| | | | | | | (what matters is that it is added to the worklist), it seems more logical to return it. llvm-svn: 55606
* Add a small pass that sets the readnone/readonlyDuncan Sands2008-09-011-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | attributes on functions, based on the result of alias analysis. It's not hardwired to use GlobalsModRef even though this is the only (AFAIK) alias analysis that results in this pass actually doing something. Enable as follows: opt ... -globalsmodref-aa -markmodref ... Advantages of this pass: (1) records the result of globalsmodref in the bitcode, meaning it is available for use by later passes (currently the pass manager isn't smart enough to magically make an advanced alias analysis available to all later passes), which may expose more optimization opportunities; (2) hopefully speeds up compilation when code is optimized twice, for example when a file is compiled to bitcode, then later LTO is done on it: marking functions readonly/readnone when producing the initial bitcode should speed up alias analysis during LTO; (3) good for discovering that globalsmodref doesn't work very well :) Not currently turned on by default. llvm-svn: 55604
* Control flow instruction encodings.Evan Cheng2008-09-012-17/+71
| | | | llvm-svn: 55601
* ldm / stm instruction encodings.Evan Cheng2008-09-012-6/+28
| | | | llvm-svn: 55599
* AXI2 and AXI3 instruction encodings.Evan Cheng2008-09-012-10/+94
| | | | llvm-svn: 55598
* Reorganize instruction formats again; AXI1 encoding.Evan Cheng2008-09-011-34/+35
| | | | llvm-svn: 55597
* addrmode3 instruction encodings.Evan Cheng2008-09-012-42/+208
| | | | llvm-svn: 55596
* Reorganize some instruction format definitions. No functionality change.Evan Cheng2008-09-011-18/+29
| | | | llvm-svn: 55594
* Rest of addrmode2 instruction encodings.Evan Cheng2008-09-012-14/+106
| | | | llvm-svn: 55593
* Addr2 word / byte load encodings.Evan Cheng2008-08-312-4/+24
| | | | llvm-svn: 55591
* Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.Evan Cheng2008-08-311-4/+5
| | | | llvm-svn: 55590
* fix a bunch of 80-col violationsGabor Greif2008-08-315-33/+65
| | | | llvm-svn: 55588
* Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTRBill Wendling2008-08-311-3/+7
| | | | | | | | instructions in CellSPU as "Expand" so that they won't be generated. I added a "FIXME" so that this hack can be addressed and reverted once ISD::ROTR is supported in the .td files. llvm-svn: 55582
* Expand for ROTR with MVT::i64.Bill Wendling2008-08-311-0/+1
| | | | | | Dale, Could you please review this? llvm-svn: 55581
* Cosmetic changes to Machine LICM. No functionality change.Bill Wendling2008-08-311-31/+36
| | | | llvm-svn: 55578
* Another situation where ROTR is cheaper than ROTL.Bill Wendling2008-08-311-3/+3
| | | | llvm-svn: 55577
* For this pattern, ROTR is the cheaper option.Bill Wendling2008-08-311-4/+4
| | | | llvm-svn: 55576
* - Fix comment so that it describes how the code really works:Bill Wendling2008-08-311-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> // (rotl x, y) // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> // (rotr x, (sub 32, y)) Example: (x == 0xDEADBEEF and y == 4) (x << 4) | (x >> 28) => 0xEADBEEF0 | 0x0000000D => 0xEADBEEFD (rotl x, 4) => 0xEADBEEFD (rotr x, 28) => 0xEADBEEFD - Fix comment and code for second version. It wasn't using the rot* propertly. // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> // (rotr x, y) // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> // (rotl x, (sub 32, y)) (x << 28) | (x >> 4) => 0xD0000000 | 0x0DEADBEE => 0xDDEADBEE (rotl x, 4) => 0xEADBEEFD (rotr x, 28) => (0xEADBEEFD) llvm-svn: 55575
* typoGabor Greif2008-08-301-1/+1
| | | | llvm-svn: 55574
* fix some 80-col violationsGabor Greif2008-08-301-19/+23
| | | | llvm-svn: 55571
* PR2731: C and Ocaml bindings for setTailCall and isTailCall.Gordon Henriksen2008-08-301-0/+10
| | | | | | Based on patch by Giorgos Korfiatis. llvm-svn: 55570
* Fix ConstantExpr::getInsertElement.Gordon Henriksen2008-08-301-2/+1
| | | | | | | Breakage was exposed in the Ocaml bindings tests after Chris uncommented an assertion in r55084. llvm-svn: 55566
* fix some 80-col violationsGabor Greif2008-08-302-3/+5
| | | | llvm-svn: 55565
* Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer ↵Evan Cheng2008-08-302-4/+83
| | | | | | the implicit defs onto the remat'ed instruction. llvm-svn: 55564
* Fold isRematerializable checks into isSafeToReMat.Evan Cheng2008-08-301-1/+3
| | | | llvm-svn: 55563
* For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But ↵Evan Cheng2008-08-301-1/+1
| | | | | | various passes cannot handle remating these. llvm-svn: 55562
* Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 ↵Evan Cheng2008-08-303-0/+116
| | | | | | shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
* Fix an issue where a use might be selected before a def, and then we didn't ↵Owen Anderson2008-08-301-8/+23
| | | | | | | | | | | respect the pre-chosen vreg assignment when selecting the def. This is the naive solution to the problem: insert a copy to the pre-chosen vreg. Other solutions might be preferable, such as: 1) Passing the dest reg into FastEmit_. However, this would require the higher level code to know about reg classes, which they don't currently. 2) Selecting blocks in reverse postorder. This has some compile time cost for computing the order, and we'd need to measure its impact. llvm-svn: 55555
* Add ppc partial-word ATOMIC_CMP_SWAP.Dale Johannesen2008-08-301-4/+143
| | | | llvm-svn: 55554
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